Analog to Digital Converter

1. Field of the Invention

The present invention relates generally to an analog to digital converter and is directed more particularly to a novel analog to digital converter which is high in conversion efficiency.

2. Description of the Prior Art

In the prior art, when, for example, a luminance signal is converted from analog to digital form, an analog to digital (hereinafter referred to as A/D) converter of the serial parallel type such as shown in FIG. 1 may be employed.

The prior art A/D converter shown in FIG. 1 is used to carry out the A/D conversion to produce a digital signal of 8-bits. In this case, an analog input voltage V.sub.in is applied to a first A/D converter 1 with a 3 bit output corresponding to D.sub.7 to D.sub.5 the upper 3 bits of the 8 bit representation of the Vin. This 3-bit digital output D.sub.7 to D.sub.5 is supplied to a digital to analog (hereinbelow referred to as D/A) converter 2 and then converted thereby to an analog voltage V.sub.m. This voltage V.sub.m and the input voltage V.sub.in are both applied to a subtracting circuit 3 from which a difference voltage V.sub.s =V.sub.in -V.sub.m is derived. This difference voltage V.sub.s is applied to an A/D converter 4 with a five bit output corresponding to D.sub.4 to D.sub.0, the lower 5 bits of the 8 bit representation of Vin. The digital outputs D.sub.7 to D.sub.5 and D.sub.4 to D.sub.0 are delivered through a latch 5 as an A/D converted output of 8-bits.

With the above serial-parallel type A/D converter, when the input voltage V.sub.in converted to a digital output of (m+n) bits, wherein m=3 and n=5 in the above example, that the total number of voltage comparing circuits required in the A/D converters 1 and 4 is only 2.sup.m =2.sup.n -2. Therefore, when the A/D converter is formed as an integrated circuit, the number of voltage comparing circuits and its chip size can be reduced and its power consumption can be also reduced.

With this serial-parallel type A/D converter, however, the upper bit converter 1 requires the same accuracy as that of the lower bit converter 4. The reason is as follows.

That is, suppose the digital output bits D.sub.7 to D.sub.0 are to be increased by "1" from "31" to "32". In that case, the bits D.sub.7 to D.sub.0 change from "00011111" to "00100000", so that the lower bits D.sub.4 to D.sub.0 change from "11111" to "00000", while the upper bits D.sub.7 to D.sub.5 are changed from "000" to "001". Accordingly, when the converter shown in FIG. 1 is used, and the input voltage V.sub.in is increased from "31" to "32", the outputs D.sub.7 to D.sub.5 from the converter 1 change by "1" from "000" to "001". However, when the input voltage V.sub.in is changed from the value "28" to "29" , the outputs D.sub.7 to D.sub.5 from the converter should not change from "000" to "001". This is true not only for the case when the input voltage V.sub.in is increased from "31" to "32" but also for the case when the input voltage V.sub.in is increased from "63" to "64", i.e. from 2.sup.k-1 to 2.sup.k, such that there is a carry from the bits D.sub.4 to D.sub.O to the bits D.sub.7 to D.sub.5. Further, the above is true for a case where the input voltage V.sub.in is decreased and the bits D.sub.7 to D.sub.5 are shifted to the bits D.sub.4 to D.sub.0. Accordingly, even though the converter 1 has an output of 3-bits, the converter 1 requires 5 bit accuracy just as the converter 4.

If the converter 1 does not have this accuracy, the conversion contains the above-mentioned error, and the outputs D.sub.7 to D.sub.0 do not increase regularly over at the junction between D.sub.7 to D.sub.5 and D.sub.4 to D.sub.0.

To avoid the above defect, a prior art converter such as shown in FIG. 2 is proposed which compensates for the lack of accuracy of the converter 1. In this example, the converter 4 includes an extra, redundant bit to have 6-bits, and the 6 bits D.sub.5 to D.sub.0 output therefrom are added with the outputs D.sub.7 to D.sub.5 from the converter 1 in an adding circuit 6 such that bit D.sub.5 from converter 1 and bit D.sub.5 from converter 4 have the same weight, i.e. represent the same power of 2.

According to the converter shown in FIG. 2, even if the converter 1 is poor in accuracy, the correct digital outputs D.sub.7 to D.sub.0 can be obtained from the adding circuit 6 (the reason for this is conventional and will be omitted).

In the converter shown in FIG. 2, however, since the redundant bit is added, A/D conversion of 9 bits (512 steps) is allowable, i.e. 6 bits in converter 4 and 3 bits in converter 1, but only A/D conversion of 8 bits (256 steps) is actually performed, namely a half of the capacity is wasted.

It is an object of the present invention to provide a novel analog to digital (A/D) converter for converting an analog signal to a digital signal exactly.

A further object of the invention is to provide an efficient A/D converter with no redundant bits.

According to an aspect of the present invention there is provided an analog to digital converter, which comprises:

a first analog to digital converter for converting a first analog signal to a first digital signal;

a code converter for converting said first digital signal to a second digital signal;

a digital to analog converter for converting said second digital signal to a second analog signal;

a subtractor for subtracting said second analog signal from said first analog signal;

a second analog to digital converter for converting an output signal of said subtractor to a third digital signal; and

an adder for adding said second digital signal and said third digital signal.

The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like references designate the same elements and parts.

FIGS. 1 and 2 are respectively block diagrams of prior art A/D converters;

FIG. 3 is a block diagram of an embodiment of the A/D converter according to the present invention;

FIG. 4 is a tabulation for illustrating the relation between a signal Q.sub.11 and a signal Q.sub.17 ; and

FIG. 5 is a graph showing the relation between an input signal V.sub.in and an output signal Q.sub.14.

The present invention will be hereinbelow described with reference to the attached drawings. The novel A/D converter according to the present invention is free from the defects of the prior art serial to parallel type A/D converter.

An example of the A/D converter according to the invention will be now described with reference to FIG. 3.

In the embodiment of the invention shown in FIG. 3, the analog input voltage V.sub.in is applied to an A/D converter 11 with a 3 bit output to be converted to a digital value Q.sub.11 of 3-bits thereby. In this case, let it be assumed that the conversion accuracy (scattering upon conversion) of the converter 11 is within .+-.2 LSB (least significant bit) of the final digital outputs D.sub.7 to D.sub.0. With this accuracy the value "28" of the lower 5 bits D.sub.4 to D.sub.0 may result in a change of "1" in the upper 3 bits and so is assumed to generate a "1" in the signal Q.sub.11.

The signal Q.sub.11 is supplied to a code-converter 17 formed of, for example, a ROM (read only memory), the output of which is a digital value Q.sub.17 having 8 bits equal to 28 times the value Q.sub.11 as shown in FIG. 4. This signal Q.sub.17 is supplied to a D/A converter 12 to be converted to an analog voltage V.sub.12. This voltage V.sub.12 is applied to a subtracting circuit 13 which is also supplied with the input voltage V.sub.in so that the subtracting circuit 13 produces a difference voltage V.sub.13 =V.sub.in -V.sub.12.

The voltage V.sub.13 is applied to an A/D converter 14 of with a 5 bit output and converted to a digital value Q.sub.14. This signal Q.sub.14 is supplied to an adding circuit 16 to which the signal Q.sub.17 from the converter 17 is also supplied so that the adding circuit 16 produces an added signal Q.sub.16 =Q.sub.14 +Q.sub.17 having 8 bits.

With the A/D converter of the invention constructed as described above, the output signal Q.sub.16 becomes as follows: ##EQU1## Thus, this signal Q.sub.16 is the A/D converted representation of the input voltage V.sub.in.

Now, the reasons for the above relations will be explained with reference to the graph of FIG. 5. As shown in FIG. 5, the output signal Q.sub.11 from the A/D converter 11 is assumed to include the scattering of .+-.2 LSB so that for the signal Q.sub.11 to be erroneously shifted to the next higher or lower value, an error width of 4 LSB is required. If the input voltage V.sub.in exists within this width or interval of 4 LSB, it is uncertain whether an error value of the signal Q.sub.11 becomes the lower or higher value.

Further, since the output signal Q.sub.17 from the code converter 17 is provided by merely code-converting the signal Q.sub.11, the signal Q.sub.17 also includes the same error for the input voltage V.sub.in and further the voltage V.sub.12 provided by A/D converting the signal Q.sub.17 so contains the same error. Accordingly, the difference voltage V.sub.13 =V.sub.in -V.sub.12 from the subtracting circuit 13 varies in sawteeth form with the input voltage V.sub.in and also includes uncertain widths of 4 LSB at step junctions.

Since the signal Q.sub.14 provided by A/D converting the voltage V.sub.13 is added to the signal Q.sub.17 to form the output signal Q.sub.16, the uncertain widths of 4 LSB are cancelled in the signal Q.sub.16 and hence this signal does not contain this error.

As described above, according to the present invention, even if any error exists in the upper bits from A/D converter 11, the output signal Q.sub.16 is not affected any thereby. Further, the redundant bit required in the prior art A/D converter shown in FIG. 2 is unnecessary in the A/D converter of this invention, so that the A/D converter of the invention has excellent efficiency.

In the embodiment of this invention, assuming that the number of bits in the output of first analog to digital converter (11) is m, which is 3 in this embodiment, and the number of bits in the output of second analog to digital converter (14) is n, which is 5 in this embodiment, the dynamic range becomes as follows;

under the condition that there is .+-.2 LSB uncertain width at the step transitions portions.

It should be herein noted that

is equivalent to the mutliplying factor of code converter (17). In other words, if the multiplying factor of the code converter (17) is expressed as T, T is obtained subtracting the uncertain widths of 4 LSB from the total number of steps 32 (2.sup.5 in the second analog to digital converter). Therefore T is not arbitrary, but must be determined on basis of the number of bits in the first and second analog to digital converters and the error of the first analog to digital converter. This means that if the multiplying factor T lies in the range

it will be possible to operate the present analog to digital converter efficiently and exactly. Thus, the dynamic range of this A/D converter is narrower than the inherent value or 256 steps of 8-bits. However, when, for example, a luminance signal is A/D converted, the narrower dynamic range is enough and the above 228 steps are sufficient. If, however, 256 steps are required, an A/D converter having an larger output may be used as the A/D converter 11.

With the above embodiment of the invention, the input voltage V.sub.in is converted into the digital signal Q.sub.16 ranging from "0" to "227", but if a different Q.sub.17 =Q.sub.11 .times.8+16 is used, the signal Q.sub.16 ranges from "16" to "243" and hence the unused range can be distributed at the upper and lower sides of the signal Q.sub.16.

The above description is given on a single preferred embodiment of the invention, but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirit or scope of the novel concepts of the invention, so that the scope of the invention should be determined by the appended claims.