Transit Vehicle Speed Maintaining Control Apparatus and Method

It is known to automatically control with a programmed microprocessor the speed of a passenger vehicle, such as a mass transit vehicle, while the vehicle is moving along a roadway track. A prior art passenger vehicle control apparatus and method, including hardware and software, to control the speed of such a vehicle in response to a P signal effort request is disclosed in U.S. Pat. No. 4,217,643 to L. W. Anderson et al, the disclosure of which is incorporated herein by reference.

A general description of microprocessor operation and related peripheral devices, including the INTEL 8080 Microprocessor, is provided in the INTEL Component Data Catalog currently available from INTEL Corporation, Santa Clara, Calif. 95051.

A passenger vehicle speed control apparatus and method responsive to a desired command speed provides a delayed switching of the speed control operation from the brake mode to the lower mode in response to the effort control signal and to result in a reduction in the operative mode changes and to provide a more stable speed maintaining control of the vehicle in relation to various track grade changes, and particularly in relation to a downhill grade of the roadway track.

FIG. 1 is a functional schematic of a prior art speed maintaining control system;

FIG. 2 shows the value of the effort request P signal in relation to power mode and brake mode operation of the prior art speed control apparatus;

FIG. 3 is a curve illustrating a typical prior art speed control operation including brake mode to power mode to brake mode control changes for a transit vehicle;

FIG. 4 is a functional schematic of the brake mode and power mode vehicle speed control system of the present invention;

FIG. 5 is a curve illustrating the improved operational power mode to brake mode vehicle speed control of the present invention;

FIG. 6 is a set of curve plots to illustrate the operation of the prior art speed control apparatus;

FIG. 7 is a set of curve plots to illustrate the improved operation of the present invention;

FIG. 8 shows the time delay in the P signal value before changing from brake mode to power mode of the present invention;

FIG. 9 is a flow chart to illustrate the speed maintaining control program of the present invention; and

FIGS. 10A and B comprise a flowchart to illustrate the speed error determination program of the present invention.

In FIG. 1 there is provided a functional schematic of a prior art speed maintaining control apparatus, including a proportional and integral controller 10 which responds to a speed error signal 12 from a comparator 14 responsive to one of a brake reference velocity signal 16 or a power reference velocity signal 18 through operation of a selector 20 that responds to the brake mode or the power mode control signal from output 22 of a power brake controller 24. An input action velocity or command speed control signal 26 is supplied to a first comparator 28, which provides the brake reference velocity signal 16 as 2 KPH below the value of the action velocity signal 26 and is operative with a comparator 30 which provides the power reference velocity signal 18 as 4 KPH below the action velocity signal 26.

The PI controller 10 provides an output first effort request P signal 32 to a jerk limiter 34 which provides an output second effort request P signal 36 to the propulsion and brake equipment 38 of a transit vehicle. The output signal 22 from the power brake controller 24 is either a brake mode control signal having a zero value or a power mode control signal having a one value. The actual speed 40 of the vehicle is fed back as an input to the power brake controller 24. When the actual speed 40 is above the brake reference velocity VELRB signal 16, the comparator 42 provides an output to cause the power brake controller 24 to provide the brake mode control signal to the propulsion and brake equipment 38. When the actual speed signal 40 is less than the power reference velocity VELRP signal 18, the comparator 44 provides an output signal 22 to the power brake controller 24 such that the power mode control signal is supplied to the propulsion and brake equipment 38.

In the typical speed maintaining control operation of a transit vehicle, particularly while the vehicle is going down a roadway track grade and with a prior art speed control apparatus, the speed control will respond to an increase in the vehicle speed 40 above the brake reference velocity 16 to provide a brake mode of operation and the difference between the brake reference velocity and the vehicle speed will determine the P signal 36 during this brake mode operation. Then the speed control will respond to the decrease in the vehicle speed below the power reference velocity 18 to provide the power mode of operation and the difference between the power reference velocity and the vehicle speed 40 will determine the P signal during this power mode operation. The speed maintaining control operation will oscillate back and forth in this manner between the brake mode and the power mode as the transit vehicles moves along the roadway track.

The desired vehicle speed profiles for the roadway track is determined by speed code information provided to the respective track circuits in the form of command speed codes. The speed maintaining control apparatus including a PI controller performs the vehicle speed maintaining function in response to a track circuit command speed to determine a power mode and a brake mode of operation within that track circuit. The characteristics of the power and brake controller output signal 22 are such that if this signal is a logic one this permits the train vehicle to be in the power mode and if this signal is a logic zero the train vehicle is in the brake mode.

The P signal as shown in FIG. 2 has a mid scale range of 60 milliamps, when the train vehicle essentially coasts with this 60 milliamp signal being provided. When the P signal value is from 60 up to 100 milliamps, this is the normal power mode range, and from 60 down to 20 milliamps is the normal brake mode range. A P signal of 20 milliamps would call for full service brakes, and a P signal of 100 milliamps would call for maximum acceleration. The P signal and the brake controller output signal from the power and brake controller are put on train lines and go to each car vehicle in a multiple car vehicle train. The P signal and the brake controller output signal go to the propulsion and brake equipment 38 on each car, which then converts these signals into motor current and brake pressure. The vehicle motors and the vehicle brakes control the actual train velocity. The train velocity is sensed by tachometers physically mounted on the motor axles, and which provide the actual speed feedback signal 40. The function of the speed maintaining apparatus shown in FIG. 1 is to first determine the desired speed of the vehicle in accordance with the input command speed signal, and then to control the vehicle speed through the P signal 36 and the brake control signal 22 such that the tachometer feedback 40 agrees with the desired input command speed 26.

In FIG. 3 there is shown a curve illustrating the typical prior art speed maintaining control operation for a transit vehicle. The input command speed VELAC, which is signal 26 in FIG. 1, is the desired action velocity for the vehicle moving down the roadway track. The brake reference velocity VELRB, which is the signal 16 shown in FIG. 1, is in the order of 2 KPH below the input command speed 26. The power reference velocity VELRP, which is the signal 18 shown in FIG. 1, is in the order of 4 KPH below the input command speed 26. The typical operation of the prior art speed control apparatus is shown by the curve 50 corresponding to the actual speed of the vehicle, where the speed goes below the power reference velocity 18 such that the power mode is provided and the P signal is increased in value in an effort to increase the speed of the vehicle, and this continues in conjunction with the power mode signal being output to the propulsion and brake equipment 38 until the actual speed 50 goes above the brake reference velocity 16. When this happens the power and brake controller 24 provides the brake mode control signal 22 to the propulsion and brake equipment 38 and the brakes are applied in accordance with the P signal, which reduces below the 60 milliamp level, such that the speed of the vehicle decreases until the speed goes below the power reference velocity 18. When this happens the power mode output signal 22 is provided by the power and brake controller 24 and the P signal goes above the 60 milliamp level to increase the speed of the vehicle until the speed goes above the brake reference velocity 16, at which time the power and brake controller 24 again provides the brake mode output signal 22 and the P signal decreases below the 60 milliamp level such that the brakes are applied. This operation repeatedly continues as the vehicle moves along the roadway track.

The speed control apparatus of the present invention as shown in FIG. 4, provides a predetermined delay in the change from brake mode to power mode to correct the undesired control oscillation as shown in FIG. 3 between the power mode and the brake mode, and particularly in relation to the vehicle going down a negative roadway track grade. When in the brake mode, instead of changing from the brake mode back to the power mode in response to the actual speed 40 going below the power reference velocity 18, the comparator 64 is responsive to the P signal going above a predetermined value such as 73 milliamps, and the control operation stays in the brake mode until the P signal reaches this predetermined value, such as 73 milliamps, before changing to the power mode.

In the operation of the power and brake controller 24, as shown in FIG. 4, when the actual speed 40 goes above the brake reference velocity 16 a brake mode zero output signal is provided at the output 22. The PI controller 10 calculates the P signal which is proportional to the speed error SPDER 12 between the actual speed 40 and one of the reference inputs 16 and 18. For example, when in the brake mode of operation, the selector 20 chooses the brake reference VELRB at input 16, and when in the power mode of operation the selector 20 chooses the power reference velocity VELRP at input 18, and in this way the PI controller 10 requests more power for the power mode and more brake effort for the brake mode.

In FIG. 4 the functional schematic illustrates the operational hardware equivalent of the software program included in the appendix. The components in FIG. 4 that correspond with those in FIG. 1 have been indicated with the same reference numbers. A delay member 60 is responsive to the first P signal 32 and supplies a modified P control signal 62 to one input of the comparator 64 for determining a change from the brake mode to the power mode of operation. The second input 66 of the comparator 64 is provided with a predetermined reference, such as a signal corresponding to 73 milliamps. The jerk limiter 34 is chosen to have a time constant of 2 which is two times slower then the time constant of the delay member 60. As shown in FIG. 8, the input 62 will thusly have a value of 73 milliamps after the provided delay time T2 while the second P signal 35 that is supplied to the propulsion and brake equipment 38 will have a value of 73 milliamps after time T1. Thusly, in the brake mode when the delay time T2 is over and the input 62 reaches the 73 milliamps, the comparator 64 will provide an output to the power brake controller 24 that will change the output state to request a change from the brake mode to the power mode of operation.

The power mode of operation and the change from power mode to brake mode are substantially the same as was previously described in relation to the control apparatus embodiment shown in FIG. 1.

FIG. 5 illustrates the improved brake mode to power mode vehicle speed control of the present invention, where the vehicle speed 70 is seen to increase above the brake reference velocity 16 as shown at 74. When the vehicle speed is above the brake reference velocity 16, the brake mode is provided and the brakes are applied, such that the vehicle which can be going down a negative roadway track guide will then decrease in speed in response to the brakes. Assuming a negative grade, the vehicle will increase in speed still in the brake mode but with little or no brakes applied because the P signal responding to the small speed error between the actual speed and the brake reference velocity is requesting a modest brake effort. As the speed error increases above the brake reference velocity at 76 the brakes will again be applied in the brake mode and in response to the P signal until the speed is below the brake reference velocity 16 at which time the vehicle speed will decrease until the P signal approaches the 60 milliamp value to release the brakes at which time the speed will increase again due to the negative track grade until the speed goes above the brake reference velocity, at which time the brakes will be applied in response to a decrease in the P signal to again slow down the vehicle. But it is noted in FIG. 5 that the actual speed need not go below the power reference velocity 18, especially when the negative grade is present.

In FIG. 6 there is shown the typical prior art speed maintaining operation, with the vehicle speed being controlled by a repetitive switching back and forth between brake mode and power mode of operation as shown by curve 80. The P signal effort request 36 to the propulsion and brake equipment 38 is shown by the curve 82. The input command speed VELAC is shown by the curve 84. The speed error SPDER signal 12 is shown by the curve 86. The vehicle actual speed 40 shown in FIG. 4 is illustrated by the curve 88.

In FIG. 7 there is shown the improved speed maintaining operation of the present invention, with the transition from brake mode to power mode being delayed by an amount which is time proportional to the difference error between the reference velocity and the actual speed of the vehicle that is grade sensitive. By delaying the brake mode back to power mode transition as shown by curve 81, the speed control system stability is improved as shown by the speed error curve 87 and the vehicle speed curve 89, which are more stable for the less disturbance of the propulsion and brake equipment 38 shown in FIG. 4 over a wide range of negative grade roadway track. The example of FIG. 7 illustrates speed maintaining on a 5% downgrade track.

In FIG. 9 there is shown a flow chart of the speed maintaining constant control program, as shown in the Appendix, which is provided for the preferred embodiment of the present invention, which includes a programmed microprocessor control system. At block 90 the brake reference velocity VELRB is determined as the input command speed VELAC minus 2 KPH as shown in FIGS. 3 and 5. At block 92 the power reference velocity VELRP is determined as the input speed command or action velocity VELAC minus 4 KPH. At block 94 a check is made to see if the performance modification velocity VELPM is greater than the power reference velocity VELRP. If not, at block 96 the power reference velocity is set equal to the performance modification velocity, and if yes, the block 96 is bypassed. At block 98 the input reference velocity VELRF to the speed error comparator 14 is set equal to the power reference velocity VELRP. At block 100 a determination is made to see if the actual speed of the vehicle is less than the brake reference velocity VELRB. As shown in FIGS. 3 and 5, this determines if the vehicle speed is greater than VELRB such that the brake mode of operation is desired as required to keep the actual speed between the brake reference velocity 16 and the power reference velocity 18. If not, then the brake mode of operation is provided. And if yes, a check is made at block 102 to see if the speed maintaining operation is in the power mode. If yes, the power mode is set at block 104 and the constants K1, K2 and K3 for the PI controller 10 are set for the power mode at block 106. If not, at block 108 the delay P signal is computed to maintain the vehicle speed in the brake mode and to delay a change back to the power mode. At block 110 a check is made to see if the delay P signal is greater than 73 milliamps. If yes, a change to the power mode is provided at block 104, and if not, the operation remains in the brake mode. At block 112 to set the brake mode, the reference velocity VELRF is set equal to the brake reference velocity VELRB. At block 114 the brake mode is set, and at block 116 the constants K1, K2 and K3 for the PI controller 10 are set for the brake mode of operation. At block 118 the IN PROFILE flag is reset and the program goes to the speed error program 120, which is shown in FIG. 10.

The PI controller operation is illustrated by the flow chart of the speed error program shown in FIG. 10. At block 130 the underspeed flag is reset. At block 132, the speed error which is the difference between the reference velocity VELRF and the actual speed SPEED is computed and checked for the underspeed and overspeed status. If SPEED is greater than VELRF, the overspeed flag is set on block 134. Blocks 136 to 140 provide the calculation and the scaling of the speed error to the system monitor. At block 142 a check is made to see if the error issued at block 132 is greater than 7.5 KPH. If yes, at block 144 this difference error is set equal to 7.5 KPH, and if not, the actual error is used. In block 146 the speed error SPDER used as the input of the PI controller is saved.

Beginning at block 148, the integral part of the PI controller operation is calculated. At block 148 the parameter PI1 is calculated as equal to the constant K2 times SPDER. At block 150 the proportional parameter PP is calculated as equal to the constant K1 times 16 times SPDER. At block 152 a check is made to see if the parameter PP is greater than 102. If yes, PP is set equal to 102 at block 154, and if not, at block 156 the proportional part is updated.

At block 158 there is calculated the limit on the positive integral. At block 160 the limit on the integral negative is calculated. At block 162 the +PImax and the -PImax are updated. At block 164 a check is made to see if the overspeed flag is set. If yes, at block 166 the integral parameter PI is calculated as equal to PI-PI1. At block 168 a check is made to see if PI is greater than 0. If yes, the program goes to block 174, and if not, at block 170 a check is made to see if PI is greater than the negative limit PImax. If not, the program goes to block 174, and if yes, at block 172 PI is set equal to that limit. At block 174 the output PSIG1 of the PI controller is calculated as equal to 153-PP+PI-K3. At block 176 a check is made to see if PSIG1 is greater than 20 milliamps. If yes, program operation is done, and if not, at block 178 the output PSIG1 is set equal to 20 milliamps, which is the lowest value of the P signal effort request as shown in FIG. 2.

At block 164, if the overspeed flag is not set, at block 180 the integral parameter PI is calculated as equal to PI+PI1. At block 182 a check is made to see if PI is less than 0. If yes, the program goes to block 188, and if not, at block 184 a check is made to see if PI is greater than the limit positive PImax. If no, the program goes to block 188, and if yes, at block 186 PI is set equal to this limit PImax. At block 188 the output PSIG1 is calculated as 153+PP+PI-K3. At block 190 the integral part is updated.

A program listing suitable for operation with an INTEL 8080 Microprocessor is shown in the Appendix and functions in accordance with the program flow charts shown in FIGS. 9 and 10. ##SPC1##