ADPCM Encoder/Decoder With Zero Code Suppression

This invention relates to ADPCM (adaptive differential pulse code modulation) encoders and decoders.

Reference is directed to a related U.S. patent application Ser. No. 555,357 filed simultaneously herewith by P. Chow, A. Weirich, and L. Strawczynski entitled "ADPCM encoder/decoder with improved tracking", and to a related United States patent application Ser. No. 555,359 filed simultaneously herewith by A. Weirich, L. Strawczynski, and E. Munter entitled "ADPCM encoder/decoder with signalling bit insertion". The disclosure of each of these copending applications is hereby incorporated herein by reference.

In order to reduce the bandwidth required for digital transmission of voice frequency signals, it is known to convert an 8-bit PCM voice frequency signal to a 4-bit ADPCM signal. Two such ADPCM signals can be transmitted in the same bandwidth as one PCM signal. Furthermore, in many circumstances such ADPCM signals can be transmitted in place of PCM signals over existing transmission links using existing equipment, which is merely supplemented by ADPCM encoders and decoders for converting between PCM and ADPCM signals at the ends of the transmission links.

For conversion from PCM to ADPCM signals without undue signal degradation, it is known to use an encoder which comprises an adaptive predictor and an adaptive quantizer. The quantizer produces the ADPCM signal from the difference between the incoming PCM signal and a predicted signal produced by the adaptive predictor. Adaptation of the quantizer is controlled by the ADPCM signal, which is also supplied to an inverse adaptive quantizer to produce a reconstructed difference signal which controls the adaptive predictor. Similarly, the decoder comprises an inverse adaptive quantizer to produce a reconstructed difference signal from the ADPCM signal, and an adaptive predictor responsive to the reconstructed difference signal for producing a predicted signal, the latter two signals being combined to produce the decoded PCM signal. Ideally, predictor coefficients of the adaptive predictors in the encoder and decoder are identical at all timess. Any departure from this is referred to as mistracking.

A problem arises in that it is common in PCM transmission systems to facilitate clock signal extraction by using zero code suppression techniques, in accordance with which for example code words having eight zero bits are replaced by code words having at least one non-zero bit. If these techniques were applied to ADPCM signals, the inverse adaptive quantizers in the encoder and decoder would be supplied with different signals, giving rise to mistracking and consequent degradation of the PCM signal reproduced by the decoder. This problem is exacerbated by the fact that the frequency of occurrence of all-zero 4-bit ADPCM code words is much higher than that of all-zero 8-bit PCM code words, resulting in a much higher rate of zero code suppression.

An object of this invention is to provide an improved ADPCM encoder and decoder and method of ADPCM coding by means of which the above problem is avoided or reduced.

According to one aspect of this invention there is provided an ADPCM decoder, for decoding an ADPCM signal produced by quantizing an error signal zero magnitudes of which are quantized as a predetermined non-zero ADPCM code, comprising: an inverse quantizer for producing a reconstructed error signal from the ADPCM signal; means for producing a reconstructed signal from the reconstructed error signal and a predicted signal; an adaptive predictor for producing the predicted signal from the reconstructed signal and the reconstructed error signal in dependence upon predictor coefficients, the adaptive predictor including means for adapting the predictor coefficients in dependence upon a leakage function and in dependence upon the reconstructed signal and the reconstructed error signal; and means for inhibiting adaptation of the predictor coefficients in dependence upon the reconstructed signal and the reconstructed error signal when the ADPCM signal has the predetermined non-zero ADPCM code.

The decoder preferably comprises means for producing an adaptive quantizing-step-size signal from the ADPCM signal, wherein the inverse quantizer is an inverse adaptive quantizer for producing the reconstructed error signal from the ADPCM signal and the adaptive quantizing-step-size signal.

The invention also extends to an ADPCM encoder comprising an ADPCM decoder as recited above, means for producing an error signal from a signal to be encoded and the predicted signal, and a quantizer for producing the ADPCM signal from the error signal and the adaptive quantizing-step-size signal if the latter signal is produced.

Conveniently the quantizer produces the ADPCM signal with n bits, n being an integer, with 2.sup.n -1 possible ADPCM codes, excluding the all-zeroes code, representing 2.sup.n -1 quantized levels of the error signal.

Thus the invention enables the transmission of all-zero ADPCM code words to be avoided, whereby zero code suppression is effectively provided without disturbing the operation of the ADPCM encoder and decoder. The predetermined non-zero ADPCM code, representing a zero magnitude error signal, can then be mis-interpreted as a positive or negative code, leading to a polarity bias of the predictor function. Such a bias, and consequent non-optimal predictor function, is avoided by inhibiting updating of the predictor coefficients in dependence upon the reconstructed signal and the reconstructed error signal whenever the predetermined non-zero ADPCM code occurs. This is particularly significant where the updating is effected solely on the basis of the polarity of the reconstructed error signal, as is the case with some adaptive predictors.

According to another aspect of this invention there is provided a method of decoding an ADPCM signal produced by quantizing an error signal, zero magnitudes of the error signal being quantized as a predetermined non-zero ADPCM code, comprising the steps of: producing a reconstructed error signal from the ADPCM signal; producing a reconstructed signal from the reconstructed error signal and a predicted signal; producing the predicted signal by adaptive prediction from the reconstructed signal and the reconstructed error signal in dependence upon predictor coefficients which are adapted in dependence upon a leakage function and in dependence upon the reconstructed signal and the reconstructed error signal; and inhibiting the adaptation of the predictor coefficients in dependence upon the reconstructed signal and the reconstructed error signal when the ADPCM signal has the predetermined non-zero ADPCM code. Preferably the ADPCM signal is produced by adaptively quantizing the error signal in dependence upon an adaptive quantizing-step-size signal derived from the ADPCM signal, and the reconstructed error signal is produced from the ADPCM signal in dependence upon the adaptive quantizing-step-size signal.

The invention further extends to a method of encoding an incoming signal to produce an ADPCM signal, comprising the steps of decoding the ADPCM signal by the method recited above; producing the error signal from the incoming signal and the predicted signal; and quantizing the error signal to produce the ADPCM signal with n bits, n being an integer, with 2.sup.n -1 possible ADPCM codes, excluding the all-zeroes code, representing 2.sup.n -1 quantized levels of the error signal.

The invention will be further understood from the following description with reference to the accompanying drawings, in which:

FIG. 1 is a functional block diagram of an ADPCM encoder and decoder in accordance with the invention;

FIG. 2 schematically illustrates the encoder and decoder of FIG. 1 in the form of a block diagram; and

FIG. 3 illustrates ADPCM encoding and decoding characteristics of the encoder and decoder.

Referring to FIG. 1, there is illustrated a functional block diagram of an ADPCM encoder 10 and decoder 12. The encoder 10 converts an 8-bit PCM signal incoming on a bus 14 to a 4-bit ADPCM signal outgoing on a transmission link 16. The decoder 12 is responsive to the latter signal to reproduce an 8-bit PCM signal on a bus 18.

The functional blocks of the encoder 10 comprise an adder 20, an adaptive quantizer (AQ) 22, a quantizing-step-size adaptation circuit 24, an inverse adaptive quantizer (IAQ) 26, an adaptive predictor (AP) 28, and an adder 30. The functional blocks of the decoder 12 comprise elements 32, 34, 36, and 38 which correspond to, and are interconnected in the same manner as, the elements 24, 26, 28, and 30 respectively of the encoder 10.

In operation, an 8-bit PCM signal sample incoming on the bus 14 has subtracted from it (after linearization as described below with reference to FIG. 2) by the adder 20 an adaptively predicted signal P, produced by the AP 28, on the bus 40, to produce an error signal E on a bus 42. The signal E is quantized by the AQ 22, in dependence upon a quantizing-step-size signal D provided on a bus 44 by the adaptation circuit 24, to produce a 4-bit ADPCM signal sample on the transmission link 16.

The 4-bit ADPCM signal is also supplied to the circuit 24 to control the quantizing-step-size adaptation, and to the IAQ 26 which in dependence upon the step-size signal D produces a reconstructed error signal RE on a bus 46. The signal RE is added to the predicted signal P on the bus 40 by the adder 30 to produce a reconstructed PCM signal sample RS on a bus 48. The AP 28 is responsive to the signals RE and RS to update the predicted signal P.

As is known, the AP 28 produces predictor coefficients which are adapted in dependence upon a leakage function and in dependence upon the reconstructed signal RS and the reconstructed error signal RE. For example, each predictor coefficient is adapted by making its value at any sampling time equal to its value at the preceding sampling time multiplied by a constant less than one (the leakage function), modified by a function of the signal samples RE and RS. If the latter function has a zero value, then it can be seen that, because the leakage function constant is less than one, the predictor coefficient will gradually be reduced to zero.

In a similar manner, in the decoder 12 the 4-bit ADPCM signal is supplied to the circuit 32 to control the decoder quantizing-step-size signal D', which is used by the IAQ 34 to produce from the ADPCM signal a reconstructed error signal RE'. This is added by the adder 38 to a predicted signal P' produced by the AP 36 to produce a reconstructed PCM signal sample RS' which constitutes the output of the decoder, and which is used with the signal RE' to update the predicted signal P'.

The above description briefly describes a known form of ADPCM encoder and decoder. The present invention is directed to an improvement of this, described below.

As illustrated in FIG. 1, in the encoder 10 the IAQ 26 also supplies to the AP 28 a signal EZ via a line 50, and in the decoder 12 the IAQ 34 similarly supplies to the AP 36 a signal EZ' via a line 52. The respective IAQ 26 or 34 produces the signal EZ or EZ' with a predetermined value (e.g. logic 1) in response to the ADPCM signal code corresponding to a zero value, as described further below. In response to this value of the signal EZ or EZ', the respective AP 28 or 36 does not adapt its predictor coefficients in dependence upon the signals RE and RS or RE' and RS' respectively, but only in dependence upon the leakage function.

FIG. 2 illustrates a block diagram of an encoder and decoder corresponding to the function diagram of FIG. 1. In FIG. 2, latches 54, 56, 58, and 60 are used to enable multiplexing of signals as described below. FIG. 2 also shows a NAND gate 62, an inverter 64, an AQ ROM (read-only memory) 66 which corresponds to the AQ 22 in FIG. 1, a 16-bit adder 68 which corresponds to the adders 20, 30, and 38 in FIG. 1, a quantizing-step-size adaptation circuit 70 which corresponds to the circuits 24 and 32 in FIG. 1, an IAQ and mu-law to linear PCM conversion ROM 72 which replaces the IAQs 26 and 34 in FIG. 1, an AP 74 which corresponds to the APs 28 and 36 in FIG. 1, and a linear to mu-law PCM conversion ROM 74. Signals EN and AD are supplied to the gate 62 whose output enables the latch 54, the signal AD also being supplied to the ROM 72 and being inverted by the inverter 64 to enable the latch 56.

In operation, the arrangement of FIG. 2 is controlled by the signals EN and AD to operate alternately as a mu-law PCM to ADPCM encoder and decoder. For operation as an encoder, in a first part of the encoding cycle the signal AD is a logic 0 so that the latch 54 is inhibited via the gate 62, the latch 56 is inhibited via the inverter 64, and the ROM 72 is controlled to convert an 8-bit mu-law PCM code word incoming on a bus 78 into a negative (two's complement) 15-bit linear PCM code word on a bus 80. The negative linear PCM code word on the bus 80 is added by the adder 68 to the relevant predicted signal P produced by the AP 74 on the bus 40, to produce a negative error signal E which is latched in the latch 58.

In a second part of the encoding cycle, the signals EN and AD are each a logic 1, so that the latches 54 and 56 are enabled. The negative linear error signal E from the latch 58 is converted by the ROM 76 into an 8-bit mu-law PCM negative error signal code word on a bus 84, which is quantized by the AQ ROM 66 into a 4-bit ADPCM code word on a bus 86, the quantization being dependent on the quantizing-step-size signal D which is supplied on a bus 90 to the AQ ROM 66 and is also latched in the latch 56. The ADPCM code word on the bus 86 constitutes the output of the encoder on a bus 88 corresponding to the transmission link 16 in FIG. 1, and is also latched in the latch 54.

The output of the latch 54 is supplied via a bus 92 to the circuit 70, which adapts the quantizing-step-size signal D accordingly, and to the ROM 72. The signal AD=1 causes the ROM 72 to operate as an inverse adaptive quantizer and mu-law to linear converter, responsive to the quantizing-step-size signal latched in the latch 56 to produce a linear reconstructed error signal RE on the bus 80. The signal RE is added to the linear predicted signal P on the bus 40 by the adder 68 to produce a linear reconstructed signal RS which is latched in the latch 58. This signal RS is converted by the ROM 76 into a mu-law signal which is latched from the bus 84 into the latch 60.

The reconstructed signal RS from the latch 60, and a mu-law version of the reconstructed error signal RE supplied by the IAQ ROM 72 on a bus 94, are applied to the AP 74. The AP 74 adapts its predictor coefficients in dependence upon the leakage function and these signals if the signal EZ, supplied from the ROM 72 to the AP 74 via the line 50, does not have the predetermined value, e.g. logic 1. If the signal EZ has the predetermined value such adaptation of the predictor coefficients by the AP 74 in dependence upon the signals RE and RS is inhibited and the predictor coefficients are changed only by the leakage function included in the characteristics of the AP 74.

For operation as a decoder, the signals EN and AD are a logic 0 and 1 respectively, so that the latch 54 is inhibited and the latch 56 is enabled. A 4-bit ADPCM signal to be decoded is in this case supplied to the ROM 72 via the bus 78, and the consequent reconstructed signal is derived from the ROM 76 via the bus 84 and a bus 96 corresponding to the bus 18 in FIG. 1. Otherwise, the operation of the arrangement is the same as that described above for the second part of the encoding cycle.

FIG. 3 illustrates characteristics of the AQ ROM 66 and the IAQ ROM 72, for a given quantizing-step-size signal D. More particularly, FIG. 3 illustrates the 4-bit ADPCM codes which are produced on the bus 86 by the AQ ROM 66 in response to the error signal E on the bus 84, and the consequent reconstructed error signal RE which is produced by the ROM 72 on the bus 80 from such ADPCM codes on the bus 78 or 92. For example, an error signal E of magnitude A shown in FIG. 3 will be quantized as the 4-bit ADPCM code 0011, which code is converted by the ROM 72 to a reconstructed error signal RE of magnitude B.

The particular ADPCM codes illustrated in FIG. 3 are given by way of example as possible codes for achieving a large number of logic 1s in the ADPCM signal, thereby simplifying clock recovery. Other codes may be used. As illustrated in FIG. 3, there are 15 possible ADPCM codes which are used out of a total possible 2.sup.4 =16 codes, the all-zeroes code 0000 not being used, thereby facilitating clock recovery. In general, for n-bit (n being an integer) ADPCM codes 2.sup.n -1 of the possible codes are used and the all-zeroes code is not used.

As 2.sup.n -1 is an odd number, if all possible codes except the all-zeroes code are used to best advantage the characteristic which results is a so-called mid-tread characteristic as illustrated in FIG. 3, in which small positive and negative error signals E are represented by a single predetermined ADPCM code, in this example the 4-bit code 1110. Apart from this, for convenience all negative error signal codes have an initial 1 bit and all positive error signal codes have an initial 0 bit.

Commonly, the adaptive predictor 74 may use only this initial, or sign, bit of the reconstructed error signal RE for determining the updating of the predictor coefficients in dependence upon the signal RE. With the mid-tread characteristic, however, each zero value of the reconstructed error signal would in this case be interpreted by the AP 74 as a negative reconstructed error signal RE (from the initial 1 bit of the code 1110 used to represent a near-zero error signal E), resulting in a change of the predictor coefficients in dependence upon the signal RE when no such change is in fact desired.

In order to avoid the suboptimal predictor function which would result from such undesired changes, in accordance with this invention the ROM 72 produces the signal EZ with its predetermined value, e.g. the signal EZ=1, whenever the ADPCM code 1110, corresponding to a zero reconstructed error signal RE, occurs. As already described, the signal EZ=1 inhibits the AP 74 from updating the predictor coefficients in dependence upon the reconstructed signal RS and the reconstructed error signal RE, whereby the undesired changes mentioned above are avoided.

Although in FIG. 2 the reconstructed error signal RE is illustrated as being derived from an output of the ROM 72 via a bus 94 for application to the AP 74, it should be appreciated that if only the initial, sign, bit of the reconstructed error signal RE is to be used by the AP then this can instead be derived directly from the input side of the ROM 72; i.e. directly from the buses 78 and 92.

It should be understood that numerous other modifications, variations, and adaptations may be made to the particular embodiment of the invention described above without departing from the scope of the invention, which is defined by the claims. In particular, it is observed that the improved tracking and signalling bit insertion techniques, described in the copending patent applications filed simultaneously herewith and already referred to, can be incorporated herein. In this respect the signal EZ of the former technique can be OR-ed in the ROM 72 with the signal EZ described above, to provide a single, composite signal EZ on the line 50. It is also observed that although reference has been made to mu-law PCM signals being converted into ADPCM signals, the invention is equally applicable to other signals, including A-law and linear PCM signals.