Buffer Circuits for Use With Semiconductor Memory Devices

This invention relates to a buffer circuit.

A buffer circuit which produces two output signals having opposite phases (hereinafter termed opposite output signals) in response to a single input signal is constructed to compare the input signal with a predetermined reference voltage signal for obtaining two opposite output signals and is important as a buffer element between an input circuit and an internal circuit in various electronic circuits. As the capacity of memory devices increases and as their operating speed increases, so an address buffer circuit for use with semiconductor memory devices becomes important. For this reason, in the following description, an address buffer circuit utilized in a semiconductor memory device is taken as a typical example.

An address buffer circuit is used in a semiconductor memory device for sending an address selection designation signal to a decoding circuit in accordance with an address input signal, and it is required in such an address buffer circuit that it accurately determine a designated address and operate at a high sensitivity and high speed, that its power consumption be small, that it includes a signal generating circuit, and that it can be designed readily and reduced in size for miniaturization of the chip.

Various circuits have been proposed which meet these requirements. FIG. 1 shows one example of the most advanced prior art circuit.

The circuit shown in FIG. 1 comprises a pre-circuit 11 essentially constituted by a flip-flop circuit which is made up of enhancement type field effect transistors (E-FET) Q.sub.31 and Q.sub.32 and which compares a single input signal A.sub.I with a predetermined reference voltage signal V.sub.REF to produce two opposite pre-output signals A'.sub.o and A'.sub.o, and a main circuit 12 essentially constituted by another flip-flop circuit made up of E-FETs Q.sub.41 and Q.sub.42 acting as a transfer gate which transfers the pre-output signals A'.sub.o and A'.sub.o according to a clock signal P.sub.11, and E-FETs Q.sub.47 and Q.sub.48 which produce two opposite output signals A.sub.o and A.sub.o when supplied with the pre-output signals A'.sub.o and A'.sub.o. One of the characteristic features of this circuit lies in that depletion type field effect transistors (D-FET) Q.sub.33 Q.sub.34, Q.sub.35 and Q.sub.36 are used in the pre-circuit. The operation of this circuit will be outlined as follows.

The operation of the pre-circuit will first be described. According to a clock signal .phi..sub.11, the input signal A.sub.I giving an address input and the reference voltage signal V.sub.REF are applied to nodes N.sub.13 and N.sub.14 via E-FETs (in the following merely designated as FET except D-FET) Q.sub.37 and Q.sub.38. While latching the applied signals by the clock signal .phi..sub.11, a clock signal .phi..sub.12 rises to raise the potential of these nodes N.sub.13 and N.sub.14 by the action of bootstrap capacitances C.sub.11 and C.sub.12. As a consequence, the conductivity of each of D-FETS Q.sub.35 and Q.sub.36 is caused to vary by the applied input signal A.sub.I and reference voltage signal V.sub.REF. Such a change is detected by the flip-flop circuit constituted by FETs Q.sub.31 and Q.sub.32 by making a clock signal .phi..sub.11 low level which appears at nodes N.sub.11 and N.sub.12 and is then sent out to the main circuit 12 as the pre-output signals A'.sub.o and A'.sub.o via FETs Q.sub.39 and Q.sub.40. If the clock signal .phi..sub.11 is still at a low level even after detection by the flip-flop circuit, the D-FETs Q.sub.33 and Q.sub.34 on the load side would be turned ON, thereby increasing power consumption. Accordingly, a one shot reverse phase signal as shown in FIG. 2 is used as the clock signal .phi..sub.11. Since the clock signal .phi..sub.11 is a one shot reverse phase signal, as the clock signal .phi..sub.11 rises again, the nodes N.sub.11 and N.sub.12 will be precharged through D-FETs Q.sub.33 and Q.sub.34 again, whereby their address determination information at the nodes N.sub.11 and N.sub.12 would be lost, and levels at the nodes N.sub.15 and N.sub.16 would be also lost. Thus, the FETs Q.sub.41 and Q.sub.42 are provided for the purpose of preventing such loss by separating the nodes N.sub.15 and N.sub.16 from the nodes N.sub.11 and N.sub.12 which are kept at high potential levels. The FETs Q.sub.41 and Q.sub.42 act as a transfer gate so that pre-output signals A'.sub.o and A'.sub.o are applied to nodes N.sub.15 and N.sub.16 in the main circuit 12 in accordance with a clock signal P.sub.11 and then detected by the flip-flop circuit comprising FETs Q.sub.47 and Q.sub.48. The detected signals are outputted as output signals A.sub.o and A.sub.o from output terminals 15 and 16. The circuit constituted by FETs Q.sub.43, Q.sub.45 and Q.sub.44 and Q.sub.46 is an output level ensuring circuit which produces an output having the same level as that of a clock signal .phi..sub.13 by bringing the potential levels of nodes N.sub.17 and N.sub.18 up to the levels above the level of the clock signal .phi..sub.13 by self-boost effect caused by gate-source capacitances of FETs Q.sub.45 and Q.sub. 46. The FETs Q.sub.49 and Q.sub.50 are provided for the purpose of preventing a low level floating in which a low level one of the pre-output signals A'.sub.o and A'.sub.o is maintained directly by a high level one of the output signals A.sub.o and A'.sub.o to turn ON one receiving such high level signal of FETs Q.sub.49 and Q.sub.50.

As described above, although this prior art circuit is advantageous in that its main circuit 12 is simple and compact in construction, it still involves the following problems. For example, the output information of the pre-circuit 11 which is transmitted to the nodes N.sub.15 and N.sub.16 is directly controlled by the output signals A.sub.o and A.sub.o through FETs Q.sub.49 and Q.sub.50. When the output signals A.sub.o and A.sub.o float, the outputs at the nodes N.sub.15 and N.sub.16 are lost. Consequently, as shown in FIG. 2, this circuit is inherently sensitive to mutual differences in timing between clock signals .phi..sub.11, P.sub.11 and .phi..sub.13. For example, should the clock signal P.sub.11 becomes a low level before the clock signal .phi..sub.11 becomes sufficiently low level, the main circuit would be disconnected from the pre-circuit before the address information is determined by the main circuit. This requires the clock signal generator to ensure correct timing. Such ensurance can be attained by increasing the time spacing (i.e. lowering frequency) but such expedient prevents high speed operations. Furthermore, as the clock signal .phi..sub.13 is required not only to directly maintain the output signal level, but also to drive a decoder circuit constituting the load of the address buffer circuit, it becomes necessary to provide a high power clock signal generating circuit having a high level of V.sub.DD. Such a circuit is complicated and uses large transistors, thereby preventing miniaturization of the chip.

Other prior art circuits also, require a clock signal that rises to the V.sub.DD source voltage level at the time of detection. In addition, there is the problem of time spacing described above. Accordingly, the requirement for clock signal generating circuit is severe, which makes it complex and difficult to design the circuit and prevents miniaturization of the circuit and high speed operation thereof.

Accordingly, it is an object of this invention to provide an improved buffer circuit in which the requirements for the voltage and time spacing of clock signals necessary for proper operation are not so severe as in the prior art buffer circuit so that the clock signal generating circuit can be designed readily to have a compact size and can operate at a high speed.

According to this invention, there is provided a buffer circuit which produces two output signals of opposite phases in response to an input signal, characterized in that there are provided a pre-circuit producing two pre-output signals in accordance with the input signal and a reference voltage signal; and a main circuit including a transfer gate circuit enabled by the pre-output signals and disabled by the output signals of the buffer circuit, a latch circuit latching the pre-output signals, and a flip-flop circuit connected to receive the pre-output signals latched by the latch circuit for producing the output signals of the buffer circuit.

In the accompanying drawings:

FIG. 1 shows a connection diagram of a prior art buffer circuit;

FIG. 2 shows waveforms of clock signal voltages utilized in the circuit shown in FIG. 1;

FIG. 3 is a connection diagram showing one embodiment of the buffer circuit according to this invention;

FIG. 4 shows waveforms of node potentials and clock signal voltages of the circuit shown in FIG. 3; and

FIG. 5 shows waveforms of the clock signal voltages utilized in the circuit shown in FIG. 3.

A preferred embodiment of the buffer circuit of this invention illustrated in FIG. 3 is constituted by a pre-circuit 1 which produces two opposite pre-signals A'.sub.o and A'.sub.o in response to an address designation input signal A.sub.I impressed upon an input terminal 3 and a reference voltage signal V.sub.REF impressed upon a reference voltage terminal 4, and a main circuit 2 supplied with the pre-output signals A'.sub.o and A'.sub.o for performing an address judgement to produce two output signals A.sub.o and A.sub.o of opposite phases and having predetermined levels.

The pre-circuit 11 has the same construction as that 11 shown in FIG. 1. More particularly, the pre-circuit 1 is constituted by FETs Q.sub.1 and Q.sub.2 which form a flip-flop circuit cross-connected at nodes N.sub.1 and N.sub.2, with their source electrode common junction driven by a clock signal .phi..sub.1, D-FETs Q.sub.3 and Q.sub.4 respectively connected between the FETs Q.sub.1 and Q.sub.2 and a V.sub.DD source terminal with their gate electrodes commonly interconnected to be driven by the clock signal .phi..sub.1, D-FETs Q.sub.5 and Q.sub.6 respectively connected between the nodes N.sub.1 and N.sub.2 and the V.sub.DD source terminal, FETs Q.sub.7 and Q.sub.8 respectively having drain electrodes for forming nodes N.sub.3 and N.sub.4 together with the gate electrodes of the D-FETs Q.sub.5 and Q.sub.6, the gate electrodes of FETs Q.sub.7 and Q.sub.8 being driven by the clock signal .phi..sub.1 and the source electrodes of the FETs Q.sub.7 and Q.sub.8 being connected to the input signal terminal 3 and the reference voltage signal terminal 4, respectively, bootstrap capacitors C.sub.1 and C.sub.2 respectively connected to the nodes N.sub.3 and N.sub.4 to be driven by a clock signal .phi..sub.2, and FETs Q.sub.9 and Q.sub.10 with their drain electrodes connected to the nodes N.sub.1 and N.sub.2, the gate electrodes commonly connected to the gate electrodes of FETs Q.sub.1 and Q.sub. 2 and source electrode acting as output nodes N.sub.5 and N.sub.6 of the pre-output signals A'.sub.o and A'.sub.o.

The main circuit 2 is constituted by FETs Q.sub.11 and Q.sub.12 cross-connected at nodes N.sub.7 and N.sub.8 to form a flip-flop circuit, the nodes N.sub.7 and N.sub.8 forming output terminals 5 and 6 of output signals A.sub.o and A.sub.o respectively; FETs Q.sub.13 and Q.sub.14 with their source electrodes connected to nodes N.sub.7 and N.sub.8 and gate electrodes connected to nodes N.sub.8 and N.sub.7 respectively; FETs Q.sub.15 and Q.sub.16 with their source electrodes connected to the drain electrodes of FETs Q.sub.13 and Q.sub.14 respectively, drain electrodes connected to source electrodes of FETs Q.sub.9 and Q.sub.10 for forming the nodes N.sub.5 and N.sub.6 acting as output and input terminals of the pre-output signals A'.sub.o and A'.sub.o, and the gate electrodes connected to the gate electrodes of FETs Q.sub.14 and Q.sub.13 respectively; FETs Q.sub.17 and Q.sub.18 with their source electrodes connected to the nodes N.sub.7 and N.sub.8 respectively, drain electrodes connected to the V.sub.DD source terminal, and gate electrodes connected to drain electrodes of FETs Q.sub.13 and Q.sub.14 to form nodes N.sub.9 and N.sub.10 ; bootstrap capacitors C.sub.3 and C.sub.4 respectively connected to the nodes N.sub.9 and N.sub.10 and driven by a clock signal .phi..sub.2 ; and FETs Q.sub.19 and Q.sub.20 with their source electrodes connected to the nodes N.sub.7 and N.sub.8, drain electrodes connected to the V.sub.DD source terminal, and gate electrodes connected to be driven by a clock signal P.sub.1. The flip-flop circuit comprised of the FETs Q.sub.11 and Q.sub.12 is connected to receive a clock pulse .phi.3.

The operation of the embodiment shown in FIG. 3 will now be described with reference to the node potentials and clock signal voltages shown in FIG. 4. For the sake of description, it is assumed that the input signal A.sub.I is at a high level.

Firstly, the level of the clock signal P.sub.1 is raised to the level of V.sub.DD, if necessary, higher than V.sub.DD to precharge the output nodes N.sub.7 and N.sub.8 to a sufficiently high level and the levels of the clock signals .phi..sub.1 and .phi..sub.2 are raised to a level slightly lower than that of the V.sub.DD. The input signal A.sub.I at the high level and the reference voltage signal V.sub.REF are applied to respective input terminals 3 and 4. Accordingly, both FETs Q.sub.7 and Q.sub.8 are turned ON to apply the input signal A.sub.I to the node N.sub.3 and the reference voltage signal V.sub.REF to the node N.sub.4. Also the nodes N.sub.1 and N.sub.2 are precharged to the level of source V.sub.DD by the D-FETs Q.sub.3 and Q.sub.4, and the flip-flop circuit constituted by FETs Q.sub.1 and Q.sub.2 is in an inoperative state. On the other hand, in the main circuit, FETs Q.sub.19 and Q.sub.20 are turned ON to precharge the nodes N.sub.7 and N.sub.8 to the level of the source voltage V.sub.DD, with the result that FETs Q.sub.13 and Q.sub.14 are turned ON to precharge the nodes N.sub.9 and N.sub.10 to the level of the source voltage V.sub.DD. Thus, FETs Q.sub.15 and Q.sub.16 acting as a transfer gate are turned OFF since nodes N.sub.5 and N.sub.6 are charged to a high potential through FETs Q.sub.9 and Q.sub.10, whereby the pre-circuit is disconnected from the main circuit.

Then, the level of the clock signal P.sub.1 is lowered (to source potential V.sub.SS or ground potential), the clock signal .phi..sub.2 is raised to a level slightly lower than that of the source voltage V.sub.DD and the clock signal .phi..sub.1 is lowered to a low level. Accordingly, the nodes N.sub.3 and N.sub.4 are raised to high potentials by way of the bootstrap capacitors C.sub.1 and C.sub.2 to make different the capability of D-FETs Q.sub.5 and Q.sub.6, which changes the potentials of the nodes N.sub.1 and N.sub.2. The difference is judged by the flip-flop circuit constituted by FETs Q.sub.1 and Q.sub.2 and the result of judgement appears at the output nodes N.sub.5 and N.sub.6 of the pre-circuit via FETs Q.sub.9 and Q.sub.10 as the pre-output signals A'.sub.o and A'.sub.o. On the other hand, in the main circuit, the potentials of nodes N.sub.9 and N.sub.10 are raised to levels higher than the level of the source voltage V.sub.DD by the clock signal .phi..sub.2 through the medium of the bootstrap capacitors C.sub.3 and C.sub.4.

Under this state, when the pre-output signals A'.sub.o and A.sub.o from the pre-circuit appear at nodes N.sub.5 and N.sub.6, the FET Q.sub.16 on the lower level side (since at this time the input signal A.sub.I is at the high level, signal A'.sub.o is at the low level) acting as a transfer gate is turned ON to lower the potential of the node N.sub.10 to a low level. As a consequence, the capability of FETs Q.sub.17 and Q.sub.18 is greatly varied whereby the potentials of nodes N.sub.7 and N.sub.8 vary correspondingly. In other words, the output signals A'.sub.o and A'.sub.o of the pre-circuit are latched by FETs Q.sub.17 and Q.sub.18. The potential level difference at nodes N.sub.7 and N.sub.8 is amplified and judged by the flip-flop circuit constituted by FETs Q.sub.11 and Q.sub.12 by lowering the level of the clock signal .phi.3 from high to low level to produce output signals A.sub.o and A.sub.o (in this case, A.sub.o is the low level signal) at the output terminals 5 and 6, respectively, and these output signals are positively fedback to the nodes N.sub.9 and N.sub.10 respectively through FETs Q.sub.13 and Q.sub.14. As the output node N.sub.8 becomes the low level, the FET Q.sub.16 automatically turns OFF since the potential of node N.sub.10 is lowered as a result of turning ON of FET Q.sub.14 due to the high potential of node N.sub.7, whereby the pre-circuit and the main circuit are disconnected again. Consequently, even when the potential of the clock signal .phi..sub.1 is increased for the purpose of preventing increase in the power consumption caused by turning ON D-FETs Q.sub.3 and Q.sub.4 after the judgement effected in the pre-circuit 1, the main circuit 2 will not be influenced. FIG. 5 shows only the clock signals among various waveforms shown in FIG. 4 and the clock signals are depicted to correspond to those shown in FIG. 2.

As described above, the circuit of this embodiment requires 4 clock signals P.sub.1, .phi..sub.1, .phi..sub.2 and .phi..sub.3 as shown in FIG. 5 just in the same manner as in the prior art. However, signal P.sub.1 is used to precharge the output nodes N.sub.7 and N.sub.8 to a suitable potential, and may simply be of the same level as that of the source voltage V.sub.DD or more, if necessary. Accordingly, different from the clock signal P.sub.11 necessary for directly driving the transfer gate as in the prior art, the clock signal P.sub.1 is not required to have a high level like V.sub.DD and a strictly defined time spacing (see FIG. 2). The clock signal .phi..sub.1 is a one shot opposite phase signal like the prior art for the purpose of decreasing the power consumption caused by the turning ON of the D-FETs Q.sub.3 and Q.sub.4 in the pre-circuit after the address judgement. The clock signal .phi..sub.2 is used to drive the bootstrap capacitors C.sub.1, C.sub.2, C.sub.3 and C.sub.4 for raising the potentials of nodes N.sub.3, N.sub.4, N.sub.9 and N.sub.10. According to this invention, although the number of the nodes whose potentials are to be increased by 2 as compared to the prior art circuit, the high level is lower than that of the source voltage V.sub.DD, thus causing no problem. The clock signal .phi..sub.3 is used to activate the flip-flop circuit comprising FETs Q.sub.11 and Q.sub.12 for judging the address level and its level is changed from a level slightly lower than that of V.sub.DD to a much lower level, without requiring any special change. For this reason, in the circuit shown in FIG. 3, it is not necessary to use the strictly defined signal .phi..sub.13 (shown in FIG. 2) adapted to directly drive a load, which signal is required to have strict time spacings with respect to other signals as in the prior art circuit, and further required to have a higher level than V.sub.DD sufficient to self-boot the nodes N.sub.17 and N.sub.18 (see FIG. 1) to above V.sub.DD.

Thus, according to the circuit shown in FIG. 3, among various clock signals, the one necessary for the activation during judgement is not required to have strict voltage and time spacing so that it is not necessary to enlarge the time spacing, to use a complicated circuit or large capacity transistors. Thus, the clock signal generating circuit can be readily designed, thus ensuring miniaturization and high speed operation of the memory circuit.

Although, in the foregoing embodiment, the buffer circuit has been described by way of an address buffer circuit for a semiconductor memory device, the invention may also be applied to any circuit of a similar type.

As described above, the buffer circuit of this invention is constituted by a pre-circuit producing two pre-output signals having opposite phases in response to an input signal; and a main circuit comprising a transfer gate circuit enabled by the pre-output signal and disabled by the output of the buffer circuit, a latch circuit for latching the pre-output signals, and a flip-flop circuit supplied with the pre-output signals latched by the latch circuit. As a consequence, different from the prior art circuit, it is not necessary to use any clock signal required to have high levels equal to the level of the source voltage V.sub.DD and strict time spacing during the activation (judging operation) of the circuit, thereby simplifying the design of the clock signal generating circuit, miniaturizing the entire circuit and increasing the operating speed.