US 4,539,494 AGrant
Semiconductor Device for Use in a Sense Amplifier
Issue Date:1985-09-03
•9 Claims
•3 Drawing Sheets
Abstract
A semiconductor device for use in a sense amplifier of a memory circuit includes a first load, a second load, third loads and first and second enhancement-type transistors. The first enhancement-type transistor is connected between the first load and the third loads and receives a data signal. The second enhancement-type transistor is connected between the second load and the third loads and receives a reference voltage. The reference voltage is compensated for by a temperature-compensating circuit so that the reference voltage is changed in accordance with a change in temperature.
Metadata
Assignee
- Fujitsu Limited
Inventor
- Setsuo Kurafuji
Application Information
Application Number:US 4787250
Filing Date:1983-03-25
Priority Date:1982-03-30
Art Unit:254
Classifications
IPC:
H03K 524G01R 19165G11C 706
Field of Search:
307365491;497;362;530;475190;207;208
Patent Drawings (3 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a semiconductor device for use in a sense amplifier of a memory circuit. Particularly, it relates to a differential amplifier for amplifying the difference in potential between a data signal and a reference voltage.
2. Description of the Prior Art
Generally, in a metal-oxide semiconductor (MOS) static memory circuit, a sense amplifier and an output buffer are provided at the output portion thereof. The sense amplifier usually consists of one or more stages of differential amplifiers, including a differential amplifier for amplifying the difference in potential between a data signal and a reference voltage.
The conductance g.sub.m of an MOS transistor decreases as the temperature increases. Therefore, a high level, i.e., an on-output level, of the output buffer, obtained from an output of the differential amplifier, has a negative temperature coefficient. A change in the on-output level of the output buffer creates a serious problem in a circuit such as an emitter-coupled logic (ECL) circuit.
Summary of the Invention
It is an object of the present invention to provide a semiconductor device for use in a sense amplifier in which a reference voltage is changed in accordance with a change in the temperature of the device, thereby stabilizing the on-output level of an output buffer.
The above-mentioned object can be achieved, according to the present invention, by a sense amplifier circuit which includes first, second and third loads, and first and second enhancement-type transistors. The first enhancement-type transistor is connected between the first and the third loads and receives a data signal. The second enhancement-type transistor is connected between the second and the third loads and receives a reference voltage. The reference voltage is compensated for by a temperature-type compensating circuit so that the reference voltage is changed in accordance with a change in temperature.
Brief Description of the Drawings
The present invention will be more clearly understood from the following description made with reference to the accompanying drawings wherein:
FIG. 1 is a graph illustrating an example of the margin between ECL levels;
FIG. 2 is a circuit diagram illustrating an embodiment of the semiconductor device according to the present invention;
FIG. 3 is a circuit diagram illustrating another embodiment of the semiconductor device according to the present invention;
FIG. 4 is a graph illustrating the characteristics of the reference voltage V.sub.REF of FIG. 2 and FIG. 3; and
FIG. 5 is a graph illustrating the characteristics of the on-output V.sub.OH of FIG. 2.
Description of the Preferred Embodiments
As is illustrated in FIG. 1, in an ECL circuit, two levels, i.e., a high level V.sub.OH and a low level V.sub.OL, are used. The low level V.sub.OL increases slightly as the temperature increases. On the other hand, the high level V.sub.OH increases greatly as the temperature increases. The semiconductor device according to the present invention is used for generating signals for an ECL circuit having bi-level signals, as is shown in FIG. 1.
In FIG. 2, which illustrates an embodiment of the present invention, C.sub.OO designates a memory cell, WL.sub.O designates a word line, BL.sub.O and BL.sub.O designate bit lines, Q.sub.LO and Q'.sub.LO designate load transistors, Q.sub.BO and Q'.sub.BO designate column selection transistors selected by a column selection signal Y.sub.O, DB and DB designate data bit or bus lines, SA designates a sense amplifier, and OB designates an output buffer.
V.sub.cc designates a first power supply and its potential and V.sub.ss designates a second power supply and its potential. For an ECL level circuit, V.sub.cc is the ground level and V.sub.ss is -5.2 volts while for a transistor-transistor logic level, V.sub.cc is +5 volts and V.sub.ss is the ground level.
The memory cell C.sub.OO comprises resistors R.sub.1 and R.sub.2, cross-coupled driver transistors Q.sub.1 and Q.sub.2, and transfer transistors Q.sub.3 and Q.sub.4.
The sense amplifier SA comprises a first differential amplifier DA.sub.1, a second differential amplifier DA.sub.2, and a temperature-compensating circuit CP.sub.1. The first differential amplifier DA.sub.1 comprises depletion-type load transistors Q.sub.11 and Q.sub.12 connected to the power supply V.sub.cc, enhancement-type input transistors Q.sub.13 and Q.sub.14 for receiving the data signals of the data bit lines DB and DB, and enhancement-type load transistors Q.sub.15 and Q.sub.16 connected between the input transistors Q.sub.13 and Q.sub.14 and the power supply V.sub.ss. The second differential amplifier DA.sub.2 has the same configuration as the first differential amplifier DA.sub.1. That is, the elements Q.sub.21 through Q.sub.26 of the second differential amplifier DA.sub.2 correspond to the elements Q.sub.11 through Q.sub.16 of the first differential amplifier DA.sub.1. The first differential amplifier DA.sub.1 detects and amplifies the difference in potential between the data bit lines DB and DB, while the second differential amplifier DA.sub.2 detects and amplifies the difference in potential between an output SD of the first differential amplifier DA.sub.1 and a reference voltage V.sub.REF to transmit its outputs D and D to the output buffer OB.
The reference voltage V.sub.REF is changed by the temperature-compensating circuit CP.sub.1, which comprises resistors R.sub.1, R.sub.2 and R.sub.3, and an enhancement-type transistor Q.sub.27.
The circuit of FIG. 2 is operated by making the potential at the word line WL.sub.O high so as to turn on the transfer transistors Q.sub.3 and Q.sub.4 and by simultaneously or subsequently making the column selection signal Y.sub.O high so as to turn on the transistors Q.sub.BO and Q'.sub.BO. In this state, if the transistors Q.sub.1 and Q.sub.2 are in an on state and in an off state, respectively, the potential at the node N.sub.1 is low and the potential at the node N.sub.2 is high, and, accordingly, the potential at the bit line BL.sub.O is low and the potential at the bit line BL.sub.O is high. In addition, the potential at the data bit line DB is low and the potential at the data bit line DB is high. The difference in potential between the data bit lines DB and DB is detected and amplified by the first differential amplifier DA.sub.1.
Next, the difference in potential between the output SD of the first differential amplifier DA.sub.1 and the reference voltage V.sub.REF is detected and amplified by the second differential amplifier DA.sub.2, whose outputs D and D are transmitted to the gates of the transistors Q.sub.31 and Q.sub.32 of the output buffer OB, respectively. Therefore, if the potential of the output D is low and the potential of the output D is high, the potential of the output D.sub.OUT is low. This low potential is referred to as V.sub.OL. Contrary to this, if the potential of the output D is high and the potential of the output D is low, the potential of the output D.sub.OUT is high. This high potential is referred to as V.sub.OH. In this case, the low potential V.sub.OL and the high potential V.sub.OH of the output D.sub.OUT are determined by the ratio of the conductance g.sub.m of the transistor Q.sub.31 to that of the transistor Q.sub.32.
Therefore, even if the high potential of the output D and the low potential of the output D are definite, when the temperature increases, the high potential V.sub.OH of the output D.sub.OUT decreases. This is because the conductance g.sub.m of each of the transistors Q.sub.31 and Q.sub.32 decreases as the temperature increases. Thus, the reduced high potential V.sub.OH creates a disadvantage in an ECL circuit which has the characteristics shown in FIG. 1.
According to the present invention, the above-mentioned disadvantage is eliminated since the reference voltage V.sub.REF is increased by the temperature-compensating circuit CP.sub.1 as the temperature increases.
The temperature-compensating circuit CP.sub.1 will now be explained in more detail. Since the potential at the node N.sub.3 between the resistors R.sub.2 and R.sub.3 is almost constant regardless of the temperature, the gate potential of the transistor Q.sub.27 is also almost constant. In the transistor Q.sub.27, when the temperature increases, the conductance g.sub.m of the transistor Q.sub.27 decreases so as to increase the saturation voltage between the drain and source of the transistor Q.sub.27, i.e., the reference voltage V.sub.REF indicated by the line A in FIG. 4. The line B in FIG. 4 indicates the reference voltage V.sub.REF of the prior art.
Therefore, in the second differential amplifier DA.sub.2, the difference in potential between the output SD and the reference voltage V.sub.REF increases as the temperature increases. As a result, the high potential of the output D becomes high and the low potential of the output D becomes low. Therefore, in the output buffer OB, the transistor Q.sub.31 is fully controlled in the on direction while the transistor Q.sub.32 is fully controlled in the off direction.
Thus, the decrease in the conductance g.sub.m of the transistor Q.sub.31 due to the increase in temperature is compensated for by the increase in the gate potential applied to the transistor Q.sub.31. Accordingly, the high potential V.sub.OH of the output D.sub.OUT never decreases and has a positive temperature coefficient, as is shown by the line E in FIG. 5. The line F in FIG. 5 shows the temperature coefficient of the prior art.
In FIG. 3, which illustrates another embodiment of the present invention, a temperature-compensating circuit CP.sub.2, comprising a resistor R'.sub.1 and a depletion-type transistor Q'.sub.27, is used as the temperature-compensating circuit CP.sub.1 of FIG. 2. This depletion-type transistor Q'.sub.27 is manufactured by the same process as the transistors Q.sub.11, Q.sub.12, Q.sub.21, and Q.sub.22.
A change in the reference voltage V.sub.REF of the temperature-compensating circuit CP.sub.2 due to a change in temperature is made in the same as that of the temperature-compensating circuit CP.sub.1. In addition to temperature compensation, the embodiment of FIG. 3 has an advantage in that fluctuation of the conductance g.sub.m of each of the depletion-type transistors Q.sub.21 and Q.sub.22 is compensated for. That is, if the conductance g.sub.m of each of the transistors Q.sub.21 and Q.sub.22 decreases due to fluctuations in the manufacturing process, the high potential of the output D decreases. As a result, the high potential V.sub.OH of the output D.sub.OUT decreases and the low potential V.sub.OL of the output D.sub.OUT increases. However, in this embodiment, the conductance g.sub.m of the transistor Q'.sub.27 also decreases so as to increase the reference voltage V.sub.REF. As a result, the high potential of the output D becomes high and the low potential of the output D becomes low. Thus, fluctuation of the conductance g.sub.m of the transistors Q.sub.21 and Q.sub.22 due to the manufacturing process is compensated.
Note that the characteristics of a depletion-type transistor are greatly dependent upon the process for ion-implanting impurities in a channel area of an enhancement-type transistor to change the transistor from an enhancement-type transistor to a depletion-type transistor. As was explained above, in the embodiment of FIG. 3, the depletion-type transistor Q'.sub.27, which is manufactured by the same process as the transistors Q.sub.21 and Q.sub.22, enables the fluctuation of the manufacturing process to be compensated.
As explained hereinbefore, according to the present invention, the reference voltage V.sub.REF of the differential amplifier DA.sub.2 increases as the temperature increases. As a result, the difference between the high potential of the output D and the low potential of the output D of the differential amplifier DA.sub.2 can be increased, and, accordingly, when the outputs D and D are used in the output buffer OB, the high potential V.sub.OH of the output D.sub.OUT is never decreased.
Claims
I claim:
1. A semiconductor device for amplifying a difference in potential between a storage state of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; first amplifying means, operatively connected to the memory cell, for sensing the storage state of the memory cell and for generating a data signal with a temperature dependency; second amplifying means for producing an output signal in dependence upon the data signal and the reference voltage, comprising: first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate operatively connected to said first amplifying means to receive the data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; and third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature-compensating circuit, operatively connected to said first and second power supply means and the gate of said second enhancement-type MIS transistor, for generating the reference voltage and providing temperature compensation by changing the reference voltage in accordance with changes in temperature to provide the reference voltage with a temperature dependency which is different from the temperature dependency of the data signal; and output buffer means, operatively connected to said first and second load means, for buffering the output signal to produce a buffered output signal having a level, said temperature compensating circuit compensating for changes in the level of the buffered output signal caused by the changes in temperature.
2. A semiconductor device as set forth in claim 1, wherein each of said first and second load means comprises a depletion-type transistor having a drain operatively connected to said first power supply means and a commonly connected gate and source operatively connected to the drain of said first and second enhancement-type MIS transistors, respectively.
3. A semiconductor device as set forth in claim 1, wherein said output buffer means comprises: a third enhancement-type MIS transistor having a drain operatively connected to said first power supply means, a gate operatively connected to said first load means, and a source for providing the buffered output signal; and a fourth enhancement-type MIS transistor having a drain operatively connected to the source of said third enhancement-type transistor, a gate operatively connected to said second load means, and a source operatively connected to said second power supply means.
4. A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means for providing a load, comprising third and fourth enhancement-type MIS transistors connected in parallel, each having a drain operatively connected to the sources of said first and second enhancement-type MIS transistors, respectively, a gate operatively connected to said first and second load means, respectively, and a source operatively connected to said second power supply means; and a temperature-compensating circuit, operatively connected to said first and second power supply means and the gate of said second enhancement-type MIS transistor, for generating the reference voltage and changing the reference voltage in accordance with a change in temperature.
5. A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature compensating circuit, comprising: a first resistor operatively connected to said first power supply means; a compensating enhancement-type MIS transistor having a drain operatively connected to said first resistor and the gate of said second enhancement-type MIS transistor, a gate, and a source operatively connected to said second power supply means; and second and third resistors, operatively connected to said first and second power supply means and the gate of said compensating enhancement-type MIS transistor, for applying a constant voltage to the gate of said compensating enhancement-type MIS transistor.
6. A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature-compensating circuit, comprising: a resistor operatively connected to said first power supply means; and a depletion-type transistor having a drain operatively connected to said resistor and the gate of said second enhancement-type MIS transistor, and a gate and a source operatively connected to said second power supply means.
7. A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means, operatively connected between said memory cell and said output buffer, for amplifying said data signal, and comprising compensating means for compensating the negative temperature coefficient of said output buffer.
8. A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means for amplifying the data signal, comprising: first differential amplifier means, operatively connected to said memory cell, for amplifying said data signal; second differential amplifier means, operatively connected to said first differential amplifier means and said output buffer, for providing an output data signal and an inverse output data signal from the data signal amplified by said first differential amplifier means; and compensating means for compensating the negative temperature coefficient of said output buffer, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; a first resistor operatively connected to said first power supply means; an enhancement-type MIS transistor, operatively connected to said first resistor, said second differential amplifier means and said second power supply means, having a gate; and second and third resistors, operatively connected to said first and second power supply means, respectively, and operatively connected to each other and to the gate of said enhancement-type MIS transistor, for applying a constant voltage to the gate of said enhancement-type MIS transistor.
9. A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means for amplifying the data signal, comprising: first differential amplifier means, operatively connected to said memory cell, for amplifying said data signal; second differential amplifier means, operatively connected to said first differential amplifier means and said output buffer, for providing an output data signal and an inverse output data signal from said data signal amplified by said first differential amplifier means; and compensating means for compensating the negative temperature coefficient of said output buffer, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; a resistor operatively connected to said first power supply means; and a depletion-type transistor operatively connected to said resistor, said second differential amplifier means and said second power supply means.
Patent Citations (5)
Non-Patent Literature (1)
- De Simone et al., "MOSFET Sense Amplifier with Low-Input Impedance", IBM Tech. Discl. Bull., vol. 14, No. 8, pp. 2290-2291, 1/1972.