Data Transfer Control Device

The present invention relates to a data transfer control device adaptable for transferring display data to a liquid crystal drive circuit for directly driving a liquid crystal display unit of a dynamic drive type.

FIG. 1 shows a prior liquid crystal drive circuit with a duty ratio of 1/4 and with 8-segment outputs. In the drive circuit, a closed loop is formed including four 8-bit shift registers 1.sub.0 to 1.sub.3 connected in a cascade fashion, an inverter 2 for AC-driving a liquid crystal display 6 unit to be described later, and a multiplexer 4. An output signal from a parallel/serial converter circuit 3 for converting parallel data into serial data is transferred to the multiplexer (selector) 4.

The multiplexer 4, controlled by a control signal a supplied from a central processing unit (CPU) (not shown), selects the data from the parallel/serial converter circuit 3 and the inverter 2. The shift register 1.sub.0 is connected at the 8-bit output terminals to a latch/driver circuit 5. The latch/driver circuit 5 converts the parallel data derived from the shift register 1.sub.0 into segment signals SEG.sub.0 to SEG.sub.7 for directly driving a liquid crystal display unit 6. The liquid crystal display unit 6 is connected to the output terminals of the latch/drive circuit 5. The 8-segment liquid crystal display 6 displays four figures at the duty ratio of 1/4 under control of common electrode drive signals COM0 to COM3 generated from a common signal generator 7 to specify a segment to be displayed.

A clock signal generator 8 generates clock signals .phi.T and .phi.L and applies them to the shift register 1.sub.0 and the latch/driver 5. The clock generator 8 is made up of a frequency divider 11 and an AND gate 12, as shown in FIG. 4. Fundamental clock signals .phi.1 and .phi.2 are generated by another clock signal generator (not shown). The clock signal .phi.1 is applied to one of the input terminals of the AND gate 12. The clock signal .phi.2 is applied in an inverted state to the frequency divider 11, and is appplied in a non-inverted state to the shift register 1.sub.0. The signals at different frequencies are applied from the frequency divider 11 to the remaining input terminals of the AND gate 12. The AND gate 12 responds to the clock signal .phi.1 to produce the clock signal .phi.L for transferring to the latch/driver 5. One clock signal .phi.L is produced every time eight pulses of the clock signal .phi.T are produced.

FIG. 5 shows an example of the common signal generator 7 for generating common electrode drive signals COM0 to COM3. The common signal generator 7 includes p-channel MOS transistors TR7 and TR8 and n-channel MOS transistors TR9 and TR10, all of which have the current paths which are connected in series between power source terminals VD and VL. Generator 7 also has p- and n-channel MOS transistors TR11 and TR12 connected in parallel between a node coupled to a resistor R2 and a resistor R3 and a node coupled to the MOS transistor TR8 and the MOS transistor TR9. NAND gate 121 applied with a first common electrode select signal d0 and a blanking signal BLK.

The gates of the MOS transistors TR7 and TR10 are connected through an inverter 122 to a control terminal WCLT. The gates of the MOS transistors TR8 and TR12 are connected together to the output terminal of the NAND gate 121. The gates of the MOS transistors TR9 and TR11 are connected through an inverter 124 to the output terminal of the NAND gate 121 having as inputs a first common electric signal do and a blanking signal BLK.

A 0-th common electrode drive signal COM0 is produced from a node between the MOS transistors TR8 and TR9. The circuit arrangements of the remaining circuit sections 125, 126 and 131 are each substantially the same as that of the circuit section 127. These circuit sections 125, 126 and 131, respectively, produce the first to third common electrode drive signals COM1 to COM3 in response to the output signals from NAND gates 128, 129 and 132 which receive at the first input terminals a blanking signal BLK and at the second input terminals the first to third common electrode select signals d1 to d3.

FIG. 6 shows a time-division control circuit in which four D-type flip-flops 21.sub.0 to 21.sub.3 connected in a cascade fashion make up a ring counter. In the figure, the Q output terminal of the flip-flop 21.sub.0 is connected to a D input terminal of the succeeding stage flip-flop 21.sub.1 of which the Q output terminal is connected to the D input terminal of the succeeding flip-flop 21.sub.2. The Q output terminal of the flip-flop 21.sub.2 is connected to the D input terminal of the flip-flop 21.sub.3. The Q output signals from the flip-flops 21.sub.0 to 21.sub.3 are sent as common electrode select signals d0 to d3. The signals d0 to d2 of these common electrode select signals are supplied through an OR gate 22 and an inverter 25 to the D input terminal of the flip-flop 21.sub.0.

The clock signal .phi.L is applied to the clock terminals CK of the flip-flops 21.sub.0 through 21.sub.3 and a clear signal is applied to the clear terminals CL of the same flip-flop.

The time division control circuit under discussion is further provided with a circuit for generating a PHASE signal and a polarity inverting signal W. An output signal CTL of the OR gate 22 is applied to one of the input terminals of a XNOR gate 24. The output signal from the XNOR gate 24 is produced as the PHASE signal and is also applied to a D-type flip-flop 23. The clear terminal CL and the clock terminal CK of the flip-flop 23 are supplied with the clear signal and the clock signal .phi.L, respectively. The polarity inverting signal W is derived from the Q output terminal of the flip-flop 23 and is applied to the other input terminal of the XNOR gate 24.

FIGS. 7A to 7F show timing diagrams of input signals applied to the time division control circuit and output signals produced from the same circuit. At the timing of the clock signal .phi.L shown in FIG. 7B, the CTL signal shown in FIG. 7D, after being inverted by the inverter 25, is applied to the D input terminals of the flip-flops 21.sub.0 through 21.sub.3, thereby to provide the signals d0 to d3 shown in FIG. 7C. The CTL signal is at a high level so long as the signals d0 to d2 are logic "1". When the signal d3 is logic "1", the signals d2 through d0 are all logic "0". These signals are applied to the OR gate 22, so that the CTL signal as the output signal from the OR gate 22 is at low level, as shown in FIG. 7D. As a result, the CTL signal at a low level is applied to one of the input terminals of the XNOR gate 24 and the polarity inverting signal at low level, after being inverted, is applied to the other input terminals of the XNOR gate 24. Therefore, the XNOR gate 24 produces the PHASE signal at high level.

The output signal from the XNOR gate 24 is further latched in the flip-flop 23. When any one of the common electrode select signals d0 to d2 is at high level, the CTL signal is at high level. Accordingly, the XNOR gate 24 produces a PHASE signal at high level, so that the PHASE signal as shown in FIG. 7E is obtained. As a result, the inverting signal W becomes a signal as shown in FIG. 7F which is the PHASE signal delayed a fixed time. The common electrode select signals d0 through d3 are applied to the common electrode drive signal generator circuit of FIG. 5, thereby forming the common electrode drive signals COM0 to COM3 as shown in FIGS. 7G through 7J.

FIG. 2 shows another example of a prior art liquid crystal drive circuit. In this example four shift registers 1.sub.0 to 1.sub.3 are connected in a cascade fashion. Multiplexers 4.sub.0 through 4.sub.3 are provided so as to write data of 4 bits from the CPU to the shift registers 1.sub.0 to 1.sub.3. One-bit signals are applied to each of the input terminals of these multiplexers 4.sub.0 through 4.sub.3. The output signals from the shift register 1.sub.3 are applied to the other input terminal of the multiplexer 4.sub.0 ; the output signal from the shift register 1.sub.2 to the other input terminal of the multiplexer 4.sub.1 ; the output signal from the shift register 1.sub.1 to the other input terminal of the multiplexer 4.sub.2 through the inverter 2; the output signal from the shift register 1.sub.0 to the other input terminal of the multiplexer 4.sub.3.

The shift register 1.sub.0 is connected through the latch/driver circuit 5 to the liquid crystal display unit 6. The fundamental clock signal .phi.T is applied to the shift registers 1.sub.0 through 1.sub.3 and the clock signal .phi.L is supplied to the latch/driver circuit 5. The common electrode drive signals COM0 to COM3 are applied from the common electrode drive signal generator 7 to the liquid crystal display 6. A control signal al for selecting the data from the CPU or the data from the shift registers 1.sub.0 through 1.sub.3 is applied to the multiplexers 4.sub.0 to 4.sub.3.

FIG. 8 is a block diagram illustrating an interconnection of the liquid crystal drive circuit shown in FIG. 2 with a microcomputer (CPU) 31 for supplying display data to the liquid crystal drive circuit. In the figure, the common electrode drive signal generator 32 transfers a display data transfer ready signal l shown in FIG. 10G to the CPU 31 and a transfer data inverting control signal K to the multiplexer 33. Further, the circuit 32 transfers the common electrode drive signals COM0 to COM3 to the liquid crystal (LC) display 6, through transfer lines 35.

FIG. 9A illustrates a figure including eight segments a to h of a digit used in the display unit 6. FIG. 9B shows a format of a segment specifying buffer containing fields for specifying the data representing the segments of the figure shown in FIG. 9A. Since the present examples use a 4-bit microprocessor, two stages of 4-bit segment specifying buffer are used for specifying the 8-segment data. As shown, bit 0 corresponds to the common electrode drive signal COM0; bit 1 to the drive signal COM1; bit 2 to the drive signal COM2; bit 3 to the drive signal COM3.

As shown in FIGS. 10A to 10J, when the common electrode select signals d0 to d2 are at low level and the select signal d3 is at high level, the data transfer ready signal l shown in FIG. 10G is at high level. As a result, the data transfer signal as shown in FIG. 10I is produced. The CPU 31 acknowledges the reception of the transfer ready signal l, and at the time of the high level of the signal d3, transfers the data corresponding to the signal COM0 to the shift register 1.sub.0, the data corresponding to the signal COM1 to the shift register 1.sub.2, the data corresponding to the signal COM2 to the shift register 1.sub.2, and the data corresponding to the signal COM3 to the shift register 1.sub.1. Thus, in the prior liquid crystal drive circuit, a fixed timing relationship is established between the common electrode drive signals COM0 to COM3 and the transfer data. This fixed timing relationship frequently hinders correct LC display operation. In other words, there is poor flexibility in setting up the transfer timing of the display data. Therefore, when the frame frequency shown in FIG. 10A is 100 Hz, the CPU must wait a maximum of 10 ms till data transfer is permitted.

Accordingly, an object of the present invention relates to a data transfer control device with improved flexibility in setting up a transfer timing of data and an improved transfer efficiency of data.

In a data transfer control device according to the present invention, a selector for selecting a transfer port of the display data is provided in display data transfer lines connecting to the multiplexers. With the provision of the selector, the data transfer is allowed at a desired timing. Therefore, the data transfer processing is relatively independent of the program, thereby improving data transfer efficiency.

Other objects and features of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIGS. 1 and 2 are block diagrams of prior art liquid crystal drive circuits;

FIGS. 3A through 3C include timing diagrams illustrating sequential operations of the liquid crystal drive circuits of FIGS. 1 and 2, in which FIG. 3A shows a waveform of a fundamental timing signal .phi.1, FIG. 3B a waveform of a clock signal .phi.L for display latch, and FIG. 3C a waveform of a clock signal .phi.T for shifting shift registers;

FIG. 4 is a schematic block diagram of a circuit for generating the clock signals .phi.L and .phi.T shown in FIGS. 3B and 3C;

FIG. 5 is a circuit diagram of a common electrode drive signal generator circuit used in the circuit shown in FIGS. 1 and 2;

FIG. 6 is a circuit diagram of a time division control circuit necessary for the liquid crystal drive circuits shown in FIGS. 1 and 2;

FIGS. 7A through 7J include timing diagrams illustrating a set of waveforms of signals formed by a time division control circuit shown in FIG. 6, in which FIG. 7A shows a waveform of a clock signal .phi.T for shifting shift registers, FIG. 7B a waveform of clock signal .phi.L for a display latch, FIG. 7C waveform of common electrode select signals d0 to d3 produced from the time division control circuit shown in FIG. 6, FIG. D a waveform of a CTL signal produced from the same circuit, FIG. 7E a waveform of a polarity inverting preparatory signal PHASE, FIG. 7F a waveform of a polarity inverting signal W, and FIGS. 7G to 7J waveforms of common electrode drive signals COM0 to COM3;

FIG. 8 is a block diagram of a prior circuit arrangement for driving the liquid crystal drive circuit shown in FIG. 2 by a microcomputer;

FIG. 9A illustrates a figure made up of eight segments a to h located at a digit space of the liquid crystal display;

FIG. 9B shows a format of a segment specifying buffer for specifying the data representing segments of the figure;

FIGS. 10A through 10J include timing charts illustrating a transfer state of display data in which FIGS. 10A to 10D illustrate common electrode select signals d0 to d3, FIG. 10E a waveform of a polarity inverting signal, FIG. 10F a waveform of a COM0 signal, FIG. 10G a waveform of a transfer ready signal 1, FIG. 10 a waveform of a transfer data inversion control signal K, FIG. 10I a waveform of a transfer data signal from a CPU, and FIG. 10J, a waveform of a display data signal;

FIG. 11 shows the interrelation of common output signals and shift registers 1.sub.0 to 1.sub.3 in the FIG. 8 circuit;

FIG. 12 shows a circuit diagram of an embodiment of a data transfer device according to the present invention;

FIGS. 13A to 13I show waveforms of signals used in the FIG. 12 circuit, in which FIG. 13A shows a polarity inverting signal, FIGS. 13B to 13E waveforms of common electrode select signals d0 to d3, and FIGS. 13F to 13H waveforms of common electrode drive signals COM0 to COM3; and

FIGS. 14A through 14F are timing charts illustrating a transfer state of display data, in which FIGS. 14A to 14D shows waveforms of segment electrode select signals, FIG. 14E a waveform of a transfer data signal from a CPU, and FIG. 14F a waveform of a display data signal.

FIG. 12 shows an embodiment of a data transfer control device according to the present invention. In the figure, like numerals are used to indicate like portions in FIG. 2. In the present embodiment, a selector 42 for selecting a transfer destination of the data transferred to the shift registers 1.sub.0 to 1.sub.3 is provided in the display data transfer path from the data bus 41 of the CPU to the multiplexers 4.sub.0 to 4.sub.3. The selector 42 is made up of groups of gates 47.sub.0 to 47.sub.3, 48.sub.0 to 48.sub.3, 49.sub.0 to 49.sub.3, and 50.sub.0 to 50.sub.3. A display data signal is applied to the gates 50.sub.0, 49.sub.0, and 48.sub.0. The inverted signal D.sub.0 from an inverter 43 coupled at the input with the signal D.sub.0 is supplied to the gate 47.sub.0. A signal D1 is applied to the gates 49.sub.1 to 48.sub.1 and its inverted signal D.sub.1 derived from an inverter 44 is applied to the gates 50.sub.1 and 47.sub.1. A D.sub.2 signal is applied to the gate 48.sub.2 and its inverted signal D.sub.2 from an inverter 45 is applied to the gates 50.sub.2, 49.sub.2 and 47.sub.2. An inverted signal D.sub.3 from an inverter 46 is applied to the gates 50.sub.3, 49.sub.3, 48.sub.3 and 47.sub.3. The gates 47.sub.0 (D.sub.0), 48.sub.3 (D.sub.3), 49.sub.2 (D.sub.2) and 50.sub.1 (D.sub.1), the gates 47.sub.1 (D.sub.1), 48.sub.0 (D.sub.0), 49.sub.3 (D.sub.3) and 50.sub.2 (D.sub.2), the gates 47.sub.2 (D.sub.2), 48.sub.1 (D.sub.1) and 49.sub.0 (D.sub.0), 50.sub.3 (D.sub.3) and the gates 47.sub.3 (D.sub.3), 48.sub.2 (D.sub.2), 49.sub.1 (D.sub.1) and 50.sub.0 (D.sub.0) constitute first to fourth gate groups, respectively.

As shown, a common electrode select signal d0 is applied to the 2nd gate group; a common electrode select signal d1 to the 3rd gate group; a common electrode select signal d2 to the 4th gate group; and ANDed signal of these signals d0 to d2 (passed through a three-negative input AND gate 51) is applied to the first gate group. The multiplexer 4.sub.0 is made up of three AND gates 52.sub.0 to 52.sub.2 and an OR gate 56.sub.0 connected at the input to these three AND gates. The remaining multiplexers 4.sub.1 to 4.sub.3 have each a similar circuit arrangement to that of the multiplexer 4.sub.0. The output signals from these multiplexers 4.sub.0 to 4.sub.3 are applied to the shift registers 1.sub.0 to 1.sub.3, respectively.

An output signal from a shift register 1.sub.0 is applied through an inverter 2 to one of the input terminals of the AND gate 53.sub.2 ; an output signal from the shift register 1.sub.1 to one of the input terminals of the AND gate 54.sub.2 ; an output signal from the shift register 1.sub.2 to one of the input terminals of the AND gate 55.sub.2 ; an output signal from the shift register 1.sub.3 to one of the input terminals of the AND gate 52.sub.2. The data signals from the 1st to 4th gate groups are respectively applied to first input terminals of the AND gates 52.sub.1, 53.sub.1, 54.sub.1 and 55.sub.1, and through inverters 61.sub.0 to 61.sub.3 to first input terminals of the AND gates 52.sub.0 to 55.sub.0.

A display/transfer signal m is applied to the second input terminals of the AND gates 52.sub.2 to 55.sub.2, through an inverter 57. An output signal from a two-negative input AND gate 60 is applied to the second input terminal of the AND gates 52.sub.1 to 55.sub.1. An output signal from a two-negative input AND gate 59 is applied to the AND gates 52.sub.0 to 55.sub.0. The display/transfer signal m is applied through the inverter 57 to the first input terminals of AND gates 59 and 60.

When the display/transfer signal m is logic "0", a data display is going on, while when it is logic "1", a data transfer is going on. The polarity inverting preparatory signal PHASE is directly applied to the second input terminal of the AND gate 60, and applied through an inverter 58 to the second input terminal of the AND gate 58. With such a circuit arrangement, when the signal m is logic "1" and the signal PHASE is logic "0", if the data is transferred at the timing of the signal d3, the gates of the first gate group are enabled to allow the data D.sub.0 to go to the shift register 1.sub.0, the data D.sub.3 to go to the shift register 1.sub.1, the data D.sub.2 to go to the shift register 1.sub.2, and the data D.sub.1 to go to the shift register 1.sub.3.

At the other timings d0 to d2, the data are transferred to the shift registers 1.sub.0 to 1.sub.3 in a similar process. When the signal m is logic "1" and the signal PHASE is logic "1", if the data is transferred at the timing of the signal d3, the related logics operate to allow the data D0 to go to the shift register 1.sub.0, the data D3 to go to the shift register 1.sub.1, the data D2 to go to the shift register 1.sub.2, and the data D1 to go to the shift register 1.sub.3.

Relationships between the registers and the data loaded into them in such operations are tabulated in FIG. 13. When the signal m is logic "0", the AND gates 52.sub.2 to 55.sub.2 in the multiplexers 4.sub.0 to 4.sub.3 are enabled and the remaining AND gates of the multiplexers are disabled through the AND gates 59 and 60. The result is the formation of a closed loop of shift registers 1.sub.0 to 1.sub.3. When the output signal from the AND gate 60 is logic "1", the gates 52.sub.1 to 55.sub.1 are enabled to allow the inverted signal WI1 to WI4 to go to the shift registers 1.sub.0 to 1.sub.3. When the output signal from the AND gate 59 is logic "1", the AND gates 52.sub.0 to 55.sub.0 pass the signals WI1 to WI4 to the shift registers 1.sub.3 to 1.sub.0 through inverters 61.sub.0 to 61.sub.3. The AND gates 59 and 60 are provided for loading signals with the opposite polarity to that of common electrode drive signals COM0 to COM3 into the shift registers 1.sub.0 to 1.sub.3. The subsequent data inversion is made by the inverters in the shift register loop. As seen from FIG. 13, the display data regularly changes with the change of the signals d0 to d3. Accordingly, the signals d0 to d3 are applied to the selector 42 and the data corresponding to those signals are loaded into the shift registers 1.sub.0 to 1.sub.3.