US 4,536,860 AGrant
Random Access Memory Device
Issue Date:1985-08-20
•16 Claims
•8 Drawing Sheets
Abstract
The random access memory device of the present invention provides the memory cell array arranged in the form of a matrix. The plurality of memory cells have cross-connected flip-flop circuits. Word driver transistors are provided corresponding to a plurality of word lines, wherein the collector is connected to a high power supply voltage while the emitter is connected to the word line. Moreover, the base of the word driver transistor is connected respectively in common to a selected word line level switching circuit via diodes. The selected word line level switching circuit supplies a current during the write operation to the common connecting point of diodes and forms a current switch together with the diodes. Thus, the voltage of a selected word line is lower than that during the read operation. The present invention provides a random access memory device which has a simplified structure, consumes less current and assures a high speed read operation.
Metadata
Assignee
- Fujitsu Limited
Inventors
- Kazuhiro Toyoda
- Haruo Shimada
Application Information
Application Number:US 568952&
Filing Date:1984-01-06
Priority Date:1980-04-01
Art Unit:233
Classifications
IPC:
G11C 700
Field of Search:
365154;155;190;226;227;189
Patent Drawings (8 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to a random access memory comprising a plurality of memory cells each of which has a flip-flop circuit where a pair of transistors are cross-connected, particularly to a memory cell driver circuit.
2. Description of the Prior Art
A random access memory device, wherein a plurality of memory cells comprising a flip-flop circuit cross-connecting a pair of bipolar transistors as the basic structure are arranged in the form of a matrix is generally known as a high speed RAM (Random Access Memory). In such a memory cell array having the memory cells in the form of a matrix, a level difference exists between the potentials of a selected word line and a non-selected word line. This level difference has so far been selected from the point of view of acquiring a margin at the time of data writing to the memory cells and therefore this value is excessive for data reading. This situation is explained by referring to FIG. 1 to FIG. 3.
FIG. 1 outlines a memory cell array where the memory cells Moo . . . Mno . . . Mom . . . Mnm are arranged in the form of (n+1).times.(m+1) matrix. Each memory cell has, for example in the case of Moo, a flip-flop circuit where the collector and base of a pair of bipolar transistors Qc1, Qc2 are cross-connected. In FIG. 1, Wo . . . Wn are word lines, H0 . . . Hn are hold lines, Bo . . . Bm, Bo . . . Bm are bit lines. The word lines W0 . . . Wn are selected by the word drivers WD0 . . . WDn, while the bit line pairs (B0,B0) . . . (Bm,Bm) are selected by the bit drivers BD0 . . . BDm. The bit drivers BD0 . . . BDm form the current switch circuits in combination with the constant current source I.sub.BS. A current is applied to only a single pair of bit lines as selected by the Y selection signal V.sub.Y0 . . . V.sub.Ym. Only a pair of bit lines is selected. It is also possible to apply a current to all lines. The word drivers WD0 . . . WDn selected by the X selection signals V.sub.X0 . . . V.sub.Xn make only one word line a "H" (High) level and maintain the remaining word lines at a "L" (Low) level. SA is the sense amplifier which forms the detecting system for the contents stored in the memory cell in combination with the transistors (Q.sub.S10,Q.sub.S20) . . . (Q.sub.S1m,Q.sub.S2m) of the the bit line pairs (B.sub.0, B.sub.0) . . . (B.sub.m, B.sub.m). WA is a write amplifier which generates an output V.sub.D .noteq.V.sub.D in accordance with an input Din when the write signal WE is "L", namely during writing, while an output V.sub.D =V.sub.D when the write signal WE is "H", namely during reading.
Explained below with reference to FIG. 2 is the memory array operation with a pair of bit lines B.sub.0, B.sub.0 selected and the word line W.sub.s selected (the selected line is given the subscript s, while the non-selected one is given the subscript N).
FIG. 2 shows a part of FIG. 1, while FIG. 3 shows the potentials of FIG. 2. Namely, when the X selection signal V.sub.xs is "H", the potential V.sub.ws of the word line W.sub.s of selected memory cell M.sub.s0 is kept high by the word driver WD.sub.s. At this time, since the other X selection signal V.sub.XN is a "L", the potential V.sub.WN of the remaining word lines W.sub.N is kept low by means of the word driver WD.sub.N.
The read operation and write operation for the memory cell M.sub.s0 under such condition will be explained by referring to FIG. 3.
The memory cell M.sub.s0 (similar to M.sub.N0) is the emitter detection type cell consisting of two load resistances R.sub.L, Schottky barrier diodes SBD and multi-emitter transistors. The transistors Q.sub.H1 to Q.sub.H4 connected to the hold lines H.sub.s, H.sub.N of the multi-emitter transistors, are the memory holding transistors, while the transistors Q.sub.c1 to Q.sub.c4 connected to the bit lines B.sub.1, B.sub.1, are the driver transistors.
When the transistor Q.sub.H1 of memory cell M.sub.s0 is ON, Q.sub.H2 is OFF, and before selection, the relation V.sub.BS >V.sub.CS is exists between the base voltage V.sub.BS of the transistor Q.sub.c1 and collector voltage V.sub.CS at the time Q.sub.c1 is selected. Here, a voltage difference (V.sub.BS -V.sub.CS) is considered as V.sub.BCS. Namely, the base voltage V.sub.BS is obtained by subtracting a value of voltage drop (this is very small) expressed as the subtraction of the product of the load resistance R.sub.L of Q.sub.c2 and a base current of Q.sub.c1 from the word line voltage V.sub.WS, while the collector voltage V.sub.CS is obtained by subtracting a voltage drop in the forward direction (V.sub.BE) of SBD from V.sub.cc because the the collector current of Q.sub.c1 is sufficiently high and therefore the diode SBD is ON. Thus, as shown in FIG. 3, V.sub.CS is kept low.
The read operation under this condition will be explained below. First, the write amplifier generates output V.sub.D, V.sub.D in accordance with the relation, V.sub.CS <V.sub.D =V.sub.D <V.sub.BS. Since the transistors Q.sub.c1 and Q.sub.s1, Q.sub.c2 and Q.sub.s2 respectively form the current switch, the transistor Q.sub.c1 is ON, while Q.sub.s1 is OFF and the current I.sub.B of bit line B.sub.1 is supplied from the transistor Q.sub.c1. Simultaneously, since V.sub.CS <V.sub.D, the transistor Q.sub.s2 is ON, while Q.sub.c2 is OFF. Thus the current I.sub.B of the bit line B.sub.1 is supplied from the transistor Q.sub.s2. For this reason, the currents viewed from the sense amplifier SA are as follow. I.sub.D =0, I.sub.D =I.sub.B. The information of memory cell M.sub.S0 can be read using the difference between these currents.
Next, the write operation will be explained with the condition of memory cell M.sub.S0 inverted by the write operation. For this purpose, first of all, it is necessary to lower the V.sub.D below collector voltage V.sub.CS by about 200 mV or more, in order to turn Q.sub.c1 to OFF from ON. When V.sub.D is lowered and it becomes equal to V.sub.CS (V.sub.D =V.sub.CS), the current I.sub.B of the bit line B.sub.1 flows equally from both transistors Q.sub.c2 and Q.sub.s2, and moreover when V.sub.D is further lowered (V.sub.D <V.sub.CS), the current I.sub.b flows from the transistor Q.sub.c2 and thereby the transistor Q.sub.c2 is ON, while Q.sub.s2 is OFF. As a result, V.sub.BS is low and the flip-flop is inverted (not indicated in FIG. 3). When V.sub.BS <V.sub.D, even if the V.sub.D remains at a potential equal to that in read operation, the transistor Q.sub.s1 is ON, while transistor Q.sub.c1 is OFF. In such a conventional memory, a level of V.sub.D is boosted generally as indicated in FIG. 3 in order to realize the speed-up of the write operation. Therefore, turning the transistors OFF is performed more quickly.
The problems of the abovementioned write and read operations will be explained. At the time of the write operation, the potential V.sub.WN of the non-selected word line W.sub.N must be such that V.sub.WN <V.sub.D <V.sub.CS. Namely, when the transistor Q.sub.H4 of the non-selected memory cell M.sub.N0 is in the ON state during the write operation, the base voltage V.sub.BN is almost equal to V.sub.WN. When the relation V.sub.WN >V.sub.D is established with V.sub.D lowered for the write operation, the transistor Q.sub.c4 turns ON and the current I.sub.B of the bit line B.sub.1 is supplied from said transistor Q.sub.c4. However, the transistor Q.sub.c2 cannot turns ON sufficiently or it requires excessive long period until it turns ON. In order to avoid such disadvantage, the relation V.sub.CS >V.sub.D >V.sub.WN .apprxeq.V.sub.BN is necessary.
On the other hand, during the read operation, the potential V.sub.WN of the non-selected word line must be lower than V.sub.WS by a constant value, but is not required to be as low as that in the write operation. Namely, it is sufficient if it is a little lower than V.sub.D =V.sub.D. In other words, if V.sub.WN =V.sub.BN =V.sub.D =V.sub.D during the read operation, the current I.sub.B of the bit line B.sub.1 is supplied from both the transistor Q.sub.s2 and Q.sub.c4. Thereby, a difference of currents (I.sub.D -I.sub.D) at the sense amplifier SA is reduced to a half, and thus it becomes difficult to read out the content of the cell M.sub.S0. Such a disadvantage can be avoided by lowering the potential V.sub.WN of the non-selected word line WN than the value V.sub.D =V.sub.D.
However, since the word line potential of the non-selected cell or the word line potential of the selected cell is conventionally constant anytime during the read and write operations, a difference in voltages between the selected word line voltages V.sub.WS and non-selected word line voltage V.sub.WN during read operation has been excessively high. This means that the selected word line voltage rises drastically during the change over to selection from the non-selection condition, namely in the transient condition to the read operation. Since it is necessary to charge the stray capacitance of the word lines to raise the word line voltage, a longer period is required for raising the word line voltage. Moreover, such problem has brought about the disadvantage that the read operation speed is lowered.
Such disadvantage can be eliminated by changing the voltage level difference between the selected word line and non-selected word line for the read and write operations. Moreover, the same effect can be obtained by changing the single selected word line level for the read and write operations.
This example of changing the selected word line level will be explained by referring to the schematic diagram of FIG. 4. The circuit shown in FIG. 4 illustrates the decoders DEC.sub.0 to DEC.sub.n and word drivers WD.sub.0 to WD.sub.n. In regard to the decoders DEC.sub.0 to DEC.sub.n, only a part is shown. In the decoders DEC.sub.0 to DEC.sub.n, the transistors (T.sub.10, T.sub.20, T.sub.30) to (T.sub.1n, T.sub.2n, T.sub.3n) respectively form the current switches for I.sub.xw, while the transistors (T.sub.40, T.sub.50) to (T.sub.4n, T.sub.5n) respectively form the current for I.sub.x. Only one of the decoder signals S.sub.0 to S.sub.n is a low (L) level and the transistors (T.sub.10, T.sub.50) are OFF, if S.sub.0 is the L level. Thus, one of the selection signal voltages V.sub.X0 to V.sub.Xn becomes a high, H, level. Thereby, one of the word lines WL.sub.0 to WL.sub.n becomes H level and is selected. At this time, all of the remaining signals among S.sub.0 to S.sub.n are at a H level, turning ON the relevant transistors (T.sub.10, T.sub.50) and resultingly all of the remaining selection signal voltages V.sub.X0 to V.sub.Xn are a L level. Thus, the relevant word line is a L level.
The level of a word line WL.sub.0 to WL.sub.n when selected is higher than that at the time of non-selection. But the select level at the time of the write operation is higher than that at the time of the read operation as shown in FIG. 5. In other words, the write control signal WE is a H during the read operation or a L during the write operation. During the read operation, at the current switches T.sub.10, T.sub.20, T.sub.30 (FIG. 4) which select the word line, for example, WL.sub.0, the transistor T.sub.20 is ON. At the current switch comprising the transistors T.sub.40, T.sub.50, the transistor T.sub.40 is ON and a current of the current source I.sub.x flows through the transistor T.sub.40. On the other hand, when the transistor T.sub.20 is ON, the current I.sub.XW flows through the load resistance R.sub.X. Therefore, the selection signal voltage V.sub.X0 is lowered to (V.sub.CC -R.sub.X I.sub.XW) as indicated in FIG. 5. This voltage is higher than the level {V.sub.CC -R.sub.X (I.sub.X +I.sub.XW)} of the non-selection condition, but is lower than the level V.sub.CC in the selecting condition.
Meanwhile, since S.sub.0 =L, WE=L during the write operation, the transistors T.sub.30, T.sub.40 are ON, while T.sub.10, T.sub.20, T.sub.50 are OFF. Therefore, the currents I.sub.x, I.sub.XW do not flow into the resistor R.sub.X. Thereby, the selection signal voltage V.sub.X0 becomes the highest power supply voltage V.sub.CC. At the time of non selection, S.sub.0 is a H level (similar to the other non-selection word), the transistors T.sub.10, T.sub.50 are ON and the currents I.sub.X, I.sub.XW flow through the resistance R.sub.X. As a result, the selection signal voltage V.sub.X0 is the lowest level shown in FIG. 5.
By the aforementioned operation, the potential of the word line during of the write operation can be made larger than that during the read operation. However, the circuit shown in FIG. 4 requires the current sources I.sub.X, I.sub.XW for each of the decoders DEC.sub.0 to DEC.sub.n which are provided to the word drivers WD.sub.0 to WD.sub.n. Therefore there is a disadvantage in that power consumption is large. Furthermore, the multi-emitter type transistors are used and many elements are also used in each of the decoders DEC.sub.0 to DEC.sub.n, so that, the structure is complicated.
Summary of the Invention
It is an object of the present invention to provide a RAM device wherein the potential of the word line is changed respectively for the write and read operations, thereby ensuring a high speed read operation and an accurate write operation.
It is another object of the present invention to provide a memory array driver circuit where the non-selected word line voltage is kept at a constant value for read and write operations and the selected word line voltage during the write operation is higher than that during the read operation.
It a further object of the present invention to provide the driver circuit having a small number of elements, having a simple circuit structure and consuming less power consumption.
The present invention relates to a random access memory device comprising;
a memory cell array arranged in the form of matrix, a plurality of memory cells having the flip-flop circuit where with cross-connected transistors;
a plurality of word lines connected to said memory cells;
word drivers which are provided respectively corresponding to the word lines and make the selected word line voltage higher than the non-selected word line voltage by means of a selection signal which is an input signal, and word decoders which are provided respectively corresponding to the word drivers and supply the selection signal, which is higher than that supplied to the non-selected word drivers, to the selected word drivers;
a selected word line level switching circuit which makes the selection signal of the selected word drivers in the read operation, the switching circuit lower than that in the write operation is provided in common with the input terminal of the word driver via the switching portion of the drivers and whereby the potential of the selected word lines in the read operation is lower than that in the write operation.
Brief Description of the Drawings
FIG. 1 is a schematic diagram of a static type RAM;
FIG. 2 is a schematic diagram indicating in detail a part of the cell array of the RAM of FIG. 1
FIG. 3 is a graph of the relation of voltages at terminals in the circuit of FIG. 2;
FIG. 4 is a schematic diagram of an example of a conventional memory cell array drive circuit;
FIG. 5 is a graph of the operating voltage waveforms at terminals of the circuit in FIG. 4;
FIG. 6 is a schematic diagram of the present invention;
FIG. 7 is a graph of the operating voltage waveforms of terminals of circuit in FIG. 6;
FIG. 8 is a schematic diagram indicating the 1st embodiment of the present invention;
FIGS. 9A-9C are schematic diagrams of embodiments of change-over circuits of the present invention;
FIG. 10 is a schematic diagram of the 2nd embodiment of the present invention;
FIG. 11 is a schematic diagram of the 3rd embodiment of the present invention;
FIG. 12 is a schematic diagram of the 4th embodiment of the present invention; and
FIG. 13 is a schematic diagram of the 5th embodiment of the present invention.
Description of the Referred Embodiment
FIG. 6 is a schematic diagram for explaining the concept of the present invention. The operation of this circuit is explained by referring to the operating voltage waveforms of FIG. 7. The portions of FIG. 6 corresponding to those of FIG. 2 mentioned above are given the same reference symbol. The conditions of the information held by the selected memory cell M.sub.S0 and non-selected memory cell M.sub.N0 are the same as that of FIG. 2.
According to FIG. 6, the word drivers WD.sub.S to WD.sub.N corresponding to the word lines W.sub.S to W.sub.N are connected such that the collector is connected to a high voltage power supply V.sub.cc, while the emitter is connected to the word lines W.sub.S to W.sub.N and the base is the input terminal. To the base, the selection signals V.sub.XS to V.sub.XN are supplied from the decoder (not illustrated). Therefore, a high voltage selection signal V.sub.XS is supplied to the base of the selected word driver WD.sub.S and the word line W.sub.S has a high voltage V.sub.WS. To the base of other non-selected word drivers WD.sub.N, a low voltage selection signal V.sub.XN is supplied and thereby the word lines W.sub.N are kept at a low voltage V.sub.WN.
Moreover, according to FIG. 6, the selection word line level switching circuit SLS is provided in common to the input terminal of the word drivers WD.sub.S to WD.sub.N via the switching parts SW.sub.S to SW.sub.N, respectively. The selected word line level switching circuit SLS controls a current I.sub.XW from the input terminal of the selected word driver WD.sub.S in the read operation in accordance with the write control signal WE. Namely, the current I.sub.XW flows along the route, Power supply V.sub.CC, through the Load resistance R.sub.X, through the Switching part SW.sub.S, through the Switching circuit SLS. Particularly, the switching parts SW.sub.S to SW.sub.N are rectifying element, so that the current I.sub.XW is applied from only the selected word driver WD.sub.S with the highest input (base) voltage of the word drivers WD.sub.S to WD.sub.N. When a current I.sub.XW flows during the read operation, the selection signal V.sub.XS is lower than that during the write operation by the amount of R.sub.X I.sub.XW. In other words, an amplitude .DELTA.R of the potentials of the selected and non-selected word line during the read operation is smaller than .DELTA.W during the write operation by R.sub.X I.sub.XW. Therefore, the amplitude .DELTA.R during the read operation is set to the minimum value, the switching time of the selected word line in the read operation becomes short as compared with the conventional time as indicated by .DELTA.t of FIG. 7. This means the shortening of the access time of the RAM is shortened.
The structure shown in FIG. 6 is the simplest and consumes less power because first, the voltage level of only one selected word line among plurality of word lines is changed, and second, the common current source I.sub.XW is provided and thereby the current I.sub.XW is supplied to only the one selected word line.
FIG. 8 is a schematic diagram of the 1st embodiment of the present invention being adapted to a logical decoder.
The decoder DEC.sub.S generates signals A.sub.0 to A.sub.m and the inverted signals A.sub.0 to A.sub.m from the address input A.sub.0 to A.sub.m with the address inverters AI.sub.0 to AI.sub.m are of the current switch structure. The desired m-bit pair among 2m bits in total of A.sub.0 to A.sub.m, A.sub.0 to A.sub.m can be combined up to n+1 (n+1=2.sup.m+1) from (A.sub.0, A.sub.1, . . . , A.sub.m) to (A.sub.0, A.sub.1, . . . A.sub.m). Thus, the n+1 decoders DEC.sub.0 to DEC.sub.n are provided, and address signal groups AG.sub.0 to AG.sub.n are provided to the decoders DEC.sub.0 DEC.sub.n respectively. The decoder DEC.sub.0 includes the NOR gate composed of the transistors T.sub.01 to T.sub.0m receiving the inputs of A.sub.0 to A.sub.m, load resistance R.sub.X, and transistor T.sub.OR which forms the current switch together with the NOR gate and the constant current source I.sub.x. The selection signal voltage V.sub.X0 obtained from the decoder DEC.sub.0 is applied to the input terminal (base) of the word driver WD.sub.0. The other word drivers and decoders are also structured in the same way. Operations are performed as well known. When all of A.sub.0 to A.sub.m signals are a L level, the transistors T.sub.01 to T.sub.0m are OFF. As a result, V.sub.X becomes equal to V.sub.CC and the word line W.sub.0 is the selection level. On the contrary, when any one of A.sub.0 to A.sub.m is H, the current I.sub.X flows into the load resistance R.sub.X, V.sub.X becomes equal to V.sub.CC -R.sub.X I.sub.X and the word line W.sub.0 is the non-selection level.
In this embodiment, the diodes D.sub.0 to D.sub.n are used as the rectifying element of the switching part (SWs of FIG. 6) in order to change the potential of the word lines in the read and write operations, and moreover a single selected word line level switching circuit SLS consisting of the transistors T.sub.1 and T.sub.2, and the constant current source I.sub.XW are provided in common to each decoder. The first and second transistors T.sub.1, T.sub.2 are emitter-connected and the common emitter side is connected to the current source I.sub.XW. The reference voltage V.sub.R is applied to the base of the 2nd transistor T.sub.2 and its collector is connected to an adequate voltage (V.sub.CC, for example). On the other hand, the write control signal WE is applied to the base of the first transistor and its collector to the cathode of diodes D.sub.0 to D.sub.n. The anodes of diodes D.sub.0 to D.sub.n are connected to the point V.sub.X of the word drivers WD.sub.0 to WD.sub.n respectively (in FIG. 8, V.sub.X is indicated as V.sub.XS while selected, V.sub.X as V.sub.XN while not selected).
The operation of decoders and word drivers thus structured is explained below.
When the word line W.sub.0 (FIG. 8) is selected, all signals A.sub.0 to A.sub.m of the address signal group AG.sub.0 are a L level, while at least any one bit of the each other address signal group (represented by AG.sub.n) is a H level. Therefore, at the decoder DEC.sub.n and word driver WD.sub.n, at least one of transistors T.sub.n1 to T.sub.nm is ON and the current I.sub.X flows through the load resistance R.sub.X. Thereby, the potential of the selection signal V.sub.XN, is equal to (V.sub.CC -R.sub.X I.sub.X). As a result, the non-selected word line W.sub.n is kept at the lowest non-selection level. On the other hand, at the decoder DEC.sub.0 and word driver WD.sub.0, all of the transistors T.sub.01 to T.sub.0m are OFF. Therefore, the level of V.sub.X0 is determined by the factor other than I.sub.X. Namely, since the write control signal WE is a H during the read operation, the transistor T.sub.1 is ON. Resultingly, the current I.sub.XW flows on along the route, V.sub.CC .fwdarw.R.sub.X .fwdarw.V.sub.X0 .fwdarw.D.sub.0 .fwdarw.T.sub.1, and V.sub.XS is equal to (V.sub.CC -R.sub.X I.sub.XW) (intermediate value). Since the rectifying elements, diodes D.sub.0 to D.sub.n form the current switch, the I.sub.XW flows from the highest point of the V.sub.X0 to V.sub.XN. Therefore, when I.sub.X >I.sub.XW, V.sub.XS is larger than V.sub.XN (V.sub.XS >V.sub.XN). Thus, the I.sub.XW flows only through the load resistance R.sub.X. While in the write operation mode (W), WE=L. Therefore, the transistor T.sub.1 is OFF and the current I.sub.XW flows through transistor T.sub.2. Namely, the current I.sub.XW does not flow through any load resistance R.sub.X. For this reason, neither I.sub.X nor I.sub.XW flow through the word driver WD.sub.0 and resultingly V.sub.XS becomes equal to V.sub.CC (maximum value).
Variation of the potential of the word lines thus obtained shows the characteristic similar to the conventional one shown in FIG. 5. But this embodiment forms the current switch with the rectifying, diodes D.sub.0 to D.sub.n and uses in common for all word drivers, the selected word line level switching circuit SLS comprising the current source I.sub.XW and transistors T.sub.1, T.sub.2, thus drastically simplifying the circuit structure as compared with the conventional structure shown in FIG. 4 and providing high density integration. Moreover, this embodiment does not use the multi-emitter type transistor and therefore has simplified the circuit pattern and uses less current, thus consuming less power.
In the embodiment of FIG. 8, the diodes D.sub.0 to D.sub.n are used as the rectifying element of the switching parts (SWs of FIG. 6), the diodes D.sub.0 to D.sub.n are used. However, any rectifying element can be used. For example, the Schottky barrier diode SBD as shown in FIG. 9A, transistor TD where the base and collector are terminated as shown in FIG. 9B or the rectifying circuit consisting of the resistances R.sub.1, R.sub.2 and transistor TD' can also be used.
FIG. 10 is a schematic diagram of the 2nd embodiment of the present invention. The present invention is adapted to a logical decoder of a type different from FIG. 8.
The operation of this logical type decoder is as follow. First, eight 2-bit combinations A.sub.0 A.sub.1, A.sub.0 A.sub.1, . . . A.sub.2 A.sub.3 are generated by combining the non-inverted and inverted outputs of the address inverters AI.sub.0 to AI.sub.3. A.sub.0 A.sub.1 is a L level when both A.sub.0 and A.sub.1 are L, but is a H level when either is H. This is also true for A.sub.0 A.sub.1 to A.sub.2 A.sub.3. The desired two pairs of these are used as the input of the decoders DEC.sub.0 to DEC.sub.15. The decoder DEC.sub.0 (similar to the other decoders) is composed of the transistors T.sub.01, T.sub.02 which are controlled by the inputs A.sub.0 A.sub.1, A.sub.2 A.sub.3, load resistance R.sub.X, transistors T.sub.05, T.sub.06 forming the current switch and the current source I.sub.X. The word driver WD.sub.0 is composed of the transistor T.sub.W0. Operation is the same as FIG. 8. When both A.sub.0 A.sub.1 and A.sub.2 A.sub.3 are a L level, transistors T.sub.01, T.sub.02 are OFF, the transistor T.sub.06 also is OFF, resulting in V.sub.X =V.sub.CC. Thus, the word line W.sub.0 rises to the selection level. Meanwhile, when at least one of A.sub.0 A.sub.1, A.sub.2 A.sub.3 is H level, the transistor T.sub.06 is ON, resulting in V.sub.X =V.sub.CC -R.sub.X I.sub.X. Thus, the word line W.sub.0 is in the non-selection level.
As in the case of FIG. 8, in this embodiment, the diodes D.sub.0 to D.sub.15, functioning as the switching parts SWs of FIG. 6, are provided at the input terminals V.sub.X0 to V.sub.X15 (here the selection signal is applied) of the transistors T.sub.W0 to T.sub.W15 of the word drivers WD.sub.0 to WD.sub.15. These diodes are also connected in common to a single selected word line level switching circuit SLS. The operation is the same as FIG. 8 and therefore explanation is omitted here.
FIG. 11 is the third embodiment of the present invention employing a general diode matrix type decoder. This decoder has the current switches CS.sub.0 to CS.sub.m of which one transistor receives the address signals A.sub.0, A.sub.1 . . . , while the other transistor receives the reference voltage V.sub.R. Thereby, the signals A.sub.0 to A.sub.n and inverted A.sub.0 to A.sub.m are obtained. Thereafter, the desired m+1 signals among the 2(m+1) signals A.sub.0 to A.sub.m are selected and connected to the m+1 emitters of the multi-emitter transistor of diode matrixes DM.sub.0 to DM.sub.n of the decoders DEC.sub.0 to DEC.sub.n. In the selected diode matrix among the diode matricies DM.sub.0 to DM.sub.n, all emitters are at the H level and the multiemitter transistor is OFF. Thereby, the selected input terminal V.sub.X0 to V.sub.Xn of the word drivers WD.sub.0 to WD.sub.n is any H level and the relevant word line W.sub.0 to W.sub.n is set to the high potential selection level. If any transistor of DM.sub.1 to DM.sub.n is ON, a voltage drop across resistance R.sub.X occurs and the selection signal V.sub.X0 to V.sub.Xn becomes a L level. As a result, corresponding word line is set to the low potential non-selection level.
In this embodiment, the diodes D.sub.0 to D.sub.n are provided as the switching parts SWs of FIG. 6 to the input terminal (to which the selection signals V.sub.X0 to V.sub.Xn are applied) of the driver transistors T.sub.W0 to T.sub.Wn of the word drivers WD.sub.0 to WD.sub.n as in the case of FIG. 8. These diodes are also connected in common to the one selected word line level switching circuit SLS. The operation is the same as that of FIG. 8 and therefore explanation is omitted here.
In above embodiment, the selected word line level switching circuit SLS comprises the current switch consisting of the transistors T.sub.1, T.sub.2 and the constant current source I.sub.XW, but this circuit can also be attained by the other circuit.
FIG. 12 shows the fourth embodiment of the present invention adapted to the logical decoder as in the case of FIG. 8. This circuit provides the selected word line level switching circuit SLS consisting of the switching part composed of the diodes D.sub.0 to D.sup.1, transistors T.sub.3, T.sub.4, T.sub.5 and resistors R.sub.1, R.sub.2 and R.sub.3. Respective elements are connected as indicated in the figure. The collector of transistor T.sub.3 and resistor R.sub.2 are connected to adequate voltage (V.sub.CC, for example), while the diode D', emitter of transistor T.sub.4 and resistor R.sub.3 are connected to a low voltage. The base of transistor T.sub.3 is connected to the write control signal WE.
In such structure, since the write control signal WE is a H level during the read operation (R), the transistor T.sub.3 is ON and the transistor T.sub.5 also becomes ON. Thereby, a current flows through the route, V.sub.CC .fwdarw.R.sub.X .fwdarw.V.sub.XS .fwdarw.D.sub.0 .fwdarw.T.sub.5 .fwdarw.R.sub.3, setting V.sub.XS to an inter-mediate value. On the other hand, in the write operation (W), the signal WE is a L level and therefore the transistors T.sub.3, T.sub.5 are OFF. Thus signal does not flow through any of the diodes D.sub.0 . . . D.sub.n, thus setting V.sub.XS to V.sub.CC (maximum value). Of course, this embodiment can be adopted to the decoder of diode matrix type.
FIG. 13 is the fifth embodiment of the present invention, adapted to the logical decoder. In this embodiment, the switching parts, diodes D.sub.0 to D.sub.n and the selected word line level switching circuit SLS consisting of the transistor T.sub.6 and constant current source I.sub.XW are provided. Connections are as indicated in the figure. The base of transistor T.sub.6 is connected to the inverted level of the write control signal WE, namely WE. During the read operation (R), WE is a L level and the transistor T.sub.6 turns OFF and thereby the current I.sub.XW flows from the highest voltage of the selection signal voltages V.sub.X0 to V.sub.XN. Meanwhile, during the write operation (W), WE becomes sufficient H level and the current I.sub.XW flows into the transistor T.sub.6 in the ON state. Of course, this embodiment can also be adopted to the diode matrix type decoder.
As explained previously, the present invention comprises a circuit which changes the potential of the word line for the write and read operations, particularly the driver circuit of the memory cell array with a simple circuit structure, which makes realizing a high speed read and on accurate write operation by making the selected word line potential higher during the write operation than that during the read operation, while the potential of the non-selected word line is kept at a constant value during the read and write operations. Therefore, the reduction in number of elements makes possible the higher integration density or simplification of the circuit pattern and moreover reduction in the current source brings about less power consumption. This is the outstanding advantage of the present invention.
Claims
What is claimed is:
1. A random access memory device, operatively connected to receive first and second power supply voltages from first and second power supply lines, respectively, for performing read and write operations, said device comprising: a plurality of memory cells arranged in a matrix form, each cell comprising a cross-connection transistor flip-flop circuit; a plurality of word lines each having a selected potential and a non-selected potential, said word lines respectively connected to corresponding ones of said memory cells; word drivers, each having selected and non-selected states, respectively operatively connected to said plurality of word lines, each having an input terminal for receiving selection signals, said word drivers providing said selected potential higher than said non-selected potential in accordance with the selection signals; word decoders, each having an output terminal respectively connected to an input terminal at a corresponding one of said word drivers, for supplying the selection signals to said word drivers, each of said word decoders including resistor means, operatively connected between the first power supply line and a respective output terminal, for generating the selection signals, having a higher or lower potential in accordance with said selected and non-selected states of said word drivers, respectively; and a selected word line level switching circuit, operatively connected to receive a read and write operation signal, and operatively connected to said plurality of word drivers, said selected word line level switching circuit comprising: a current source; and switching means, each of said switching means operatively connected to the input terminal of respective word drivers, and operatively connected to said current source, for selectively connecting said current source to said resistor means of only one of said selected word decoders during the read operation, and for making the selected potential of the selected word line during the read operation lower than the selected potential of the selected word line during the write operation.
2. A random access memory device as set forth in claim 1, wherein each of said word drivers comprise: a driver transistor having a collector operatively connected to receive the first power supply voltage, having an emitter connected to a corresponding one of said word lines and having a base corresponding to the input terminal for receiving a corresponding one of the selection signals.
3. A random access memory device as set forth in claim 2, wherein said current source of said selected word line level switching circuit has first and second current levels, the first current flows in said resistor means provided between the base of said driver transistor and the first power supply voltage in accordance with said selected word drivers in said selected state and said read operation, and the second current which is larger than the first current flows through said resistor means in accordance with said corresponding word drivers in said non-selected state.
4. A random access memory device as set forth in claim 1, wherein each of said switching means comprises a diode, having an anode connected to a corresponding one of said word drivers and having a cathode operatively connected in common to said current source.
5. A random access memory device as set forth in claim 1, wherein each of said switching means comprises a Schottky barrier diode, having an anode connected to a corresponding one of said word drivers and having a cathode operatively connected in common to said current source.
6. A random access memory device as set forth in claim 1, wherein each of said switching means comprises a transistor having a base, having a collector connected to said base and to a corresponding one of said word drivers, and having an emitter connected in common to said current source.
7. A random access memory device as set forth in claim 1, wherein each of said switching means comprises a transistor having a base, having a collector and having an emitter and which has at least two resistors operatively connected between said collector and said base and between said base and said emitter, respectively, said collectors of said respective transistors being connected to corresponding ones of said word drivers, and said emitters of each said transistor being operatively connected in common to said current source.
8. A random access memory device as set forth in claim 1, wherein said device is operatively connected to receive a reference voltage and a control signal, and wherein said selected word line level switching circuit further comprises: first and second transistors each having a base, having a collector, and having an emitter connected in common to said current source, and said current source operatively connected between said emitter and the second power supply voltage, said collector of said first transistor is connected to receive the first power supply voltage, said base of said first transistor is operatively connected to receive the reference voltage, and said collector of said second transistor is operatively connected in common to each of said rectifying circuits, said base of said second transistor is operatively connected to receive the control signal, the control signal having a voltage higher than the reference voltage in response to the read operation and a voltage lower than the reference voltage in response to the write operation.
9. A random access memory device operatively connected to receive select signals, first and second power supply voltages from first and second power supply lines, respectively, and a control signal, for performing read and write operations, comprising: a plurality of memory cells, each comprising a cross-connected transistor flip-flop circuit arranged in a matrix form; a plurality of word lines, each having a selected potential and a non-selected potential, said word lines respectively, operatively connected to said memory cells; word line driver means, respectively, operatively connected to said word lines and to said memory cells and having input terminals operatively connected to receive the select signals, for providing said selected potential and said non-selected potential of said word lines, said selected potential being higher than sad non-selective potential, and said word line driver means having a selected state and a non-selected state; word decoder means having output terminals respectively, operatively connected to said input terminals of word line driver means, for providing the select signals to said word line driver means, each of said word decoder means including resistor means operatively connected between the first power supply line and respective output terminals, for generating the select signals, the select signals having a higher or lower potential in accordance with said selected and non-selected states of said word line driver means, respectively; and selected word line level switching means, operatively connected to receive read or write operation signals and operatively connected to said word line driver means, for varying said higher potential of the select signals between first and second levels in accordance with the read operation and the write operation signals, said selected word line level switching means comprising: a current source; and switching means, operatively connected to said current source, and each respectively, operatively connected to the input terminals of said word line driver means, for selectively connecting said current source to said resistor means of only one of said selected word decoder means during the read operation, and for making the selected potential of said selected word line during the read operation lower than the selected potential of said selected word line during the write operation.
10. A random access memory device as set forth in claim 9, wherein each of said word line driver means comprises: a driver transistor having a collector operatively connected to receive the first power supply voltage, an emitter operatively connected to a corresponding one of said word lines, and a base operatively connected to receive a corresponding one of the select signals.
11. A random access memory device as set forth in claim 9, wherein said switching means comprises a diode having an anode operatively connected to said base of said driver transistor, and a cathode operatively connected to said current source.
12. A random access memory device as set forth in claim 9, wherein said switching means comprises a Schottky barrier diode having anode operatively connected to said base of said driver transistor, and a cathode operatively connected to said current source.
13. A random access memory device as set forth in claim 9, wherein said switching means comprises a transistor having a base, having a collector operatively connected to said base and to said base of said driver transistor, and having an emitter operatively connected to said current source.
14. A random access memory device as set forth in claim 9, wherein said switching means comprises: a transistor having a base, having a collector operatively connected to said base, and having an emitter operatively connected to said current source; a first resistor operatively connected between said collector and said base of said transistor; and a second resistor operatively connected between said base and said emitter of said transistor.
15. A random access memory device as set forth in claim 9, operatively connected to receive a reference voltage, wherein said selected word line level switching means further comprises first and second transistors each having a base, having a collector and having an emitter, said emitter of each of said first and second transistors operatively connected to said current source, said collector of said first transistor operatively connected to receive the first power supply voltage, said base of said first transistor operatively connected to receive the reference voltage, said collector of said second transistor operatively connected to said rectifying circuit and said base of said second transistor operatively connected to receive the control signal, wherein the control signal has a voltage higher than the reference voltage in response to the read operation and a voltage lower than the reference voltage in response to the write operation.
16. A random access memory device as set forth in claim 9, wherein said selected word line level switching means further comprises: a first transistor having a base operatively connected to receive the control signal, having a collector operatively connected to receive the first power supply voltage and having an emitter; a first resistor having a first terminal operatively connected to said emitter of said first transistor, and having a second terminal; a second transistor having a collector operatively connected to said second terminal of said first resistor, having an emitter operatively connected to receive the second power supply voltage and having a base; a second resistor having a first terminal operatively connected to receive the first power supply voltage and having a second terminal operatively connected to said base of said second transistor; a rectifying circuit having a first terminal operatively connected to said base of said second transistor and having a second terminal operatively connected to receive the second power supply voltage; a third transistor having a base operatively connected to said second terminal of said first resistor and said collector of said second transistor, having a collector operatively connected to said switching means, and having an emitter; and a third resistor having a first terminal operatively connected to said emitter of said third transistor and having a second terminal operatively connected to receive the second power supply voltage.