Direct A.C. To A.C. Converter Controlled by a Data Processor

This invention relates to a direct a.c. supply converter, that is a converter in which an alternating current power supply input is converted into an alternating current power supply output having different characteristics from the input supply without passing through an intermediate direct current stage.

A direct a.c. power converter is described and claimed in U.S. patent application Ser. No. 390,000 (issued Aug. 28, 1984 as U.S. Pat. No. 4,468,725) assigned to the assignee of the present application and incorporated herein by reference. That converter uses a matrix of bi-directional switches having contiguous width-modulated conduction periods to connect the phases of a poly-phase a.c. input supply to output conductors to synthesize the output supply. The switches are operated in a cycle of much higher frequency than the supply frequencies in such a way that each output conductor is connected to only one of the input conductors at a time. A potential difficulty in the operation of this converter is that the generation of the control signals for the switches involves calculations dependent on the phases of the supplies which means that alteration of the characteristics of the output supply may be complicated.

An object of the present invention is to provide an improved a.c. supply converter in which the above difficulty is largely overcome.

According to the present invention there is provided an a.c. supply converter having input conductors for a balanced polyphase a.c. input supply system, output conductors for an a.c. output supply system, a plurality of bidirectional switches which individually connect each input conductor to each output conductor, and a control system connected to operate the switches by a repeating sequence of abutting width modulated pulses, there being the same number of pulses in the sequence as there are phases in the input supply, in such a way that each phase of the input supply is connected in turn to each phase of the output supply and that at any instant one and only one of the switches connected to each of the output conductors is closed, wherein the control system includes a data processor means programmed to produce a sequence of values representing the widths of the modulated pulses, pulse generator means responsive to the values to produce the width modulated pulses and apply them to the switches, and means connected to the input conductors to derive therefrom signals indicative of the phase of the a.c. input supply, which signals are applied to the data processor means to influence the sequence of values generated. For example, the phase indicative signals may be applied to the data processor means as a time reference for matching the timing of the sequence of the pulses generated to the input supply.

The signals indicative of the phase of the a.c. input supply may be derived in response to the voltage of the supply crossing a particular level, such as zero, and may be applied to an interrupt input of the data processor means to initiate a program for synchronizing the operation of the data processor means with the time of the crossing. The synchronizing program may be a software phase locked loop.

The pulse generator means may include means for monitoring the conductive states of the bidirectional switches and a circuit for interlocking the operation of the switches so that the turning on of a switch coincides with the turning off of the preceding switch. In the case of an overload on the output circuit the bidirectional switches may be unable to be fully turned on and the pulse generators may have an overload detection circuit which compares the period of time taken for each switch to turn on fully with a preset value and if that time is exceeded turns off all the switches.

A default logic circuit may be provided for feeding equal values to the pulse width modulators should the data processor means suffer a hardware or software failure preventing the correct operation of the pulse width modulators. When this happens the output voltage is zero.

Although a converter according to the invention is generally useful for providing an output a.c. supply of selected voltage, frequency, relative phase or number of phases from an at least 3-phase input supply, it is particularly applicable to the speed control of an induction motor.

The control system described uses a data processor working on-line to provide values representing the pulse widths which are utilised as they are generated to control the pulse width modulators. In an alternative arrangement the data processor may be arranged to calculate the values in advance for a whole cycle, which values are then stored and used as required, the computer updating the values whenever a change is required.

In order that the invention may be fully understood and readily carried into effect an embodiment will now be described with reference to the accompanying drawings, of which:

FIG. 1 is a block diagram of the embodiment of the invention;

FIG. 2 is a circuit of the microcomputer circuit of FIG. 1;

FIGS. 3 and 4 together show a circuit diagram of each pulse width modulator of FIG. 2;

FIGS. 5(a), 5(b) and 6 are flow diagrams of the microcomputer program;

FIG. 7 shows the memory map of the microcomputer;

FIG. 8 shows details of the input data file; and

FIG. 9 shows examples of the waveforms applied to the switches.

Reference will also be made to Table 1 which shows the program of the microcomputer in detail. The program is written in the assembly code of the microprocessor type TMS 9995 which is the microprocessor used in the embodiment of the invention to be described. The reader is referred to the data manual for this device to enable him to follow the operations performed by the program and to determine the operation codes for the program.

The embodiment of the invention as shown in FIG. 1 is for converting a 3-phase input supply into a 3-phase output supply, the converter controlling the phase amplitude and frequency of the output supply. The input supply is applied via conductors 1 to nine switches S1 to S9 in groups of three as shown and the output supply appears on conductors 2. The operation of the switches is performed in accordance with the principles described in U.S. Pat. No. 4,468,725 by a microcomputer circuit 3. Input values indicative of the phase, amplitude and frequency required of the output supply are applied via an input unit 4 to the microcomputer circuit 3. In order that the microcomputer circuit 3 can perform its calculation on the basis of the phase and frequency of the input supply, one predetermined phase of this supply is applied to the circuit 3 via a conductor 5. The microcomputer circuit 3 will be described later with reference to FIGS. 2, 3 and 4 and its program with reference to FIGS. 5, 6, 7 and 8. The switches S1 to S9 may for example take any of the transistorized forms described and illustrated in FIGS. 12, 16, 17, 18 or 19 of U.S. Pat. No. 4,468,725.

The microcomputer circuit includes a microprocessor of type TMS 9995 manufactured by Texas Instruments, and the reader is directed to the data manual for this device to improve his understanding of the operation of the circuit to be described. The microprocessor carries the reference 10 and has its eight parallel data terminals connected to the 8-bit data bus 11. The device 10 has sixteen address connections of which ten are connected to an address bus 12. The remaining address terminals are not used in this application. The device 10 has a built in oscillator to which a 12 MHz crystal 13 is connected, which oscillator provides the pulses for the operation of the device 10. A programmable read only memory (PROM) 14 is connected to the data bus 11 and the address bus 12 and provides not only the program for the operation of the device 10 but also a look-up table of cosines, the values of which are used in the calculations performed by the device 10. The input data is applied to the circuit via a buffer store 15, which is connected to both data and address buses 11 and 12. A memory map logic circuit 16 is connected to the address bus and to the PROM 14 and the buffer store 15 to provide chip select signals for those components in accordance with the allocation of memories used in the circuit. Three pulse width modulators 17, 18 and 19 are connected to the data bus 11 to receive values representing the widths of pulses to be applied to the switches S1 to S9 to produce the required output supply in accordance with the principles described in U.S. Pat. No. 4,468,725. The modulator 17 has outputs connected to switches S1, S2 and S3, the modulator 18 has outputs connected to switches S4, S5 and S6, the modulator 19 has outputs connected to switches S7, S8 and S9. The addressing of the modulators 17, 18 and 19 is effected by a decoder circuit 20 connected to the address bus 12, which decoder has outputs respectively for the modulators 17, 18 and 19 which are applied to those modulators via a default logic circuit 21 which operates as described below to override the control of the modulators 17, 18 and 19 by the device 10 in the event of a breakdown which could lead to damage of the switches S1 to S9 or of the devices driven by the output of the converter. The default logic unit 21 is connected to the data bus 11 and receives timing pulses from a time bus 22, which also supplies the timing pulses for the pulse width modulators 17, 18 and 19. The time bus 22 is driven by a crystal oscillator 23 controlled by 2 MHz crystal 24. A ready logic circuit 25 is connected to the device 10, the memory logic 16 and the time bus 22 to derive an indication of when the circuit timing is synchronised and provide an indication of this state to the device 10.

Since the calculations to be performed by the device 10 depend on the phase and frequency of the input supply, a sample of the input supply derived from one of the conductors 1 (FIG. 1) via a conductor 5 is applied to an integrator 26, the output of which is connected to a comparator 27 and thence to a monostable multivibrator 28. The integrator 26 not only provides a 90.degree. phase shift so that zero crossings detected by the comparator 27 coincide with input voltage peaks which is desirable because of the use of cosines in the calculations, but also confers a measure of noise immunity to the circuit. The multivibrator 28 applies interrupt pulses to the device 10 via a conductor 29 to operate a software phase locked loop included in the program of the device 10.

Before describing the calculations performed by the program, the functions of the various parts of the microcomputer circuit shown in FIG. 2 will be discussed. The device 10 reads input data from the buffer store 15, which data represents the voltage, frequency and phase required of the output supply. For a given output supply the phase of the switching signals will clearly depend on the phase of the input supply and it is for this reason that the operation of the device 10 is synchronised with a phase of the incoming supply. Similarly, the output voltage of the converter will depend on the input voltage and the representations of the output voltage takes the form of the relationship of the output voltage to the input voltage. The frequency control data represents the actual output frequency, but, as will be evident from a consideration of the calculations to be described, the device 10 requires an indication of the input supply frequency in order to calculate the pulse widths. This input supply information is derived from the input supply by means of the software phase locked loop.

The PROM 14 operates in a conventional manner to provide the program information for the device 10 and the program makes use of the internal registers provided. If another type of microprocessor is employed, then it may be necessary to provide some random access memory to enable the program to be performed. The program of the device 10 causes it to address the buffer store 15 when input data is required and to address the pulse width modulators 17, 18 and 19 via the decoder 20 when output values have been calculated.

The pulse width modulators 17, 18 and 19 are of the same construction and each consists of the circuitry shown in detail in FIGS. 3 and 4. The data bus 11 is connected to two 8-bit latches 50 and 51 which are selected alternately by decoding of the address data on the bus 12 (FIG. 2). The values stored in the latches 50 and 51 are transferred to a counter 52 formed of two chips, and pulses of a constant frequency are applied via a conductor 53 to the counter 52 to cause it to count down to zero, an operation which takes a period of time depending on the value transferred into the counter from one of the latches. The end of this period is indicated by a pulse on conductor 54 which is applied to latches 55 and 56, the outputs of which are combined logically to effect the application of the width modulated pulse output of the latches in turn to the three switches to which the particular modulator is connected. The modulator in addition to including the circuitry for producing the width modulated pulses also includes a programmable timing counter 57, the purpose of which is to detect an overload of the switches. This circuit receives state signals from the three switches via conductors 58, 59 and 60, which are directed via gates 61 and 62 to the counter 57. When a switch is driven a pulse is transmitted via a gate 63 and the gate 62 which starts the counter 57 and if the state indication from the switch does not indicate that the switch has changed state within a predetermined time set by a number applied to the counter 57 via conductors 64, then this is assumed to be due to the overloading of the switches, for example, due to a short-circuit, and the circuit produces a trip output to block further conduction of the switches.

The state inputs from the switches are also used to ensure that there is no overlap in the conduction apparatus of the switches by holding off the application of a turning on signal to one switch until the preceding switch is turned off. This function is achieved by the gates 75 to 80.

In the pulse width modulators only two data latches 50 and 51 are required because the on time of the three switches connected to each modulator always adds up to a constant interval with the result that only two on times need be specified in each cycle of control of the switches. The period of this cycle of control is determined by signals applied to the modulator from the time base 22 and is typically between 50 and 200 .mu.s. The operation of the modulator is such that the first switch on-time is stored in the latch 50, the second switch on-time in the latch 51 and the third switch on-time occupies the remainder of the period before the next pulse from the time base 22 via a conductor 81. During the respective switch off times the latches 50 and 51 receive the next input values for the next cycle. The maximum duration of the on-time of any switch is two-thirds of the total cycle period, and this means that at least one-third of the cycle period is available for updating each latch. If the values are not loaded into the latches 50 and 51 during this time, the default logic 21 is arranged to override the control of the modulators by the microprocessor 10 and automatically loads the latches 50 and 51 with values representing one-third of the cycle period which has the effect of making the output voltage of the converter equal to zero. This default logic serves to protect the load whilst the converter is coming into synchronism and, in the event of failure of the microprocessor or a crash of its program. The synchronisation of the program of the processor to the loading times for the loads is achieved by the use of the READY signal provided by the ready logic 25. If the microprocessor 10 completes the calculation routine before this time occurs and is ready to perform a memory write to the pulse width modulator, the ready logic 25 applies a signal to the device 10 which causes it to enter an extended wait state until the ready logic 25 output indicates that the time for loading the value has come. The use of the ready logic in this way has the effect that after a few cycles the timing becomes stabilised, so that the processor enters a wait state on each cycle halting program execution until the calculated values can be loaded into the latches. Immediately after the loading has been effected, the processor 10 resumes the calculations for the next switch interval. The transfer of data requires much less time than is provided by the one-third of the cycle period, so that, if necessary, the transfer can be delayed allowing for interruption of the calculation, for example, to perform the phase locking with the input supply.

As shown in FIG. 2, the default logic 21 transmits the address signals for the pulse width modulators 17, 18 and 19 from the decoder 20. The logic 21 includes six latches respectively connected to the six address lines and are set when the corresponding sets of latches in the pulse width modulators are addressed. A gate is provided in the default logic to produce an output if at the end of a cycle all of the latches have not been set. Any failure to address one of the sets of latches in the pulse width modulators will be detected by this arrangement and is used to initiate the fail-safe override to avoid damage to the switches or the load device.

Turning now to the program to be performed by the microprocessor, consideration will first be given to the calculations to be performed in generating the values representing the required pulse widths. From the above-mentioned U.S. Pat. No. 4,468,725, the theory for the operation of a 3-phase to 3-phase converter can be described in the following terms.

Given a set of input sinusoidal voltages at input frequency: ##EQU1## and a set of output sinusoidal currents at output frequency: ##EQU2## determine a control law for the switches S.sub.11,S.sub.12, . . . , S.sub.33 so that the low frequency parts of the synthetized output voltages V.sub.o1, V.sub.o2, V.sub.o3, and input currents I.sub.i1, I.sub.i2, I.sub.i3 are sinusoidal with the prescribed output frequency, input frequency, phase and amplitude respectively.

Let now the desired input currents and output voltages be: ##EQU3##

According to the existence theorem, the output voltage and input current high frequency synthesis are possible, in this case, only if:

Furthermore, it is required that: ##EQU4## Within these limitations, a solution of the system of equations is the following generalized transformer low frequency modulation matrix m(t): ##EQU5## where:

with:

In the particular embodiment, the input data is as follows:

Output frequency: 12-bit word, say 0 to 1000 Hz=f.sub.o

Output amplitude: 8-bit word, range 0 to 0.5=q

Input-Output phase transfer: 5-bit word (4 bits+sign), range -1 to +1=.phi..sub.*

Output Phase Set (optional, not in this implementation): 8 bit-word, range 0 to 2.pi./3=.phi..sub.o

The input voltage frequency and phase must be obtained from the supply. This is achieved by taking zero crossings in the comparator 27 which causes pulses to be produced by the multivibrator 28 applied as interrupts via conductor 29 to the microprocessor 10.

Input voltage=V.sub.i ; Output voltage=V.sub.o ; so that

Input frequency=f.sub.i and Output frequency=f.sub.o and .omega..sub.i =2.pi.f.sub.i ; .omega..sub.o =2.pi.f.sub.o.

The input data file is shown in FIG. 8 and indicated in FIG. 7. Each memory location indicated is of 1 byte, that is to say 8 bits. The values stored represent .phi..sub.o, the output phase set value, q and a frequency control value occupying 2 bytes. The value stored in these bytes has 14 significant bits and is a twos complement value in the range 2001 to 1FFF (-8191 to +8191). This value defines the output value frequency as ##EQU6## where f.sub.s is the switch rate.

Apart from the input data file, the memory map shown in FIG. 7 indicates that 256 bytes are provided for storing the program, another 256 bytes store the cosine look-up table and a further 256 bytes are provided by the internal RAM of the microprocessor, which locations are used in the performance of the calculations. In addition, the memory map includes six bytes forming an output data file and two bytes forming an event counter.

Flow diagrams of the calculations performed by the microprocessor are shown in FIGS. 5 and 6. The flow diagram A of FIG. 5 indicates the main loop of the program which periodically cause the calculation subroutine which is shown in the flow diagram of FIG. 6. The flow diagram B of FIG. 5 illustrates the program used to ascertain the microprocessor operation is synchronised and the values being calculated can be used to control the pulse width modulators.

The details of the program itself in the assembly language of the TMS 9995 microprocessor are given in Table 1 which is annotated to indicate the particular functions being performed by the operations.

FIG. 9 shows an example of typical width modulated pulses which would be produced by the microcomputer circuit for operating the switches S1 to S9 of the converter. The cycle time T.sub.c is 192 .mu.s, resulting from the use of 2 MHz as the time base frequency, 8 bits to specify each switch pulse duration and the fact that the maximum duration for a switch pulse is 2/3 of the cycle time. The maximum duration for a switch pulse is 2.sup.8 =256 times 0.5 .mu.s=128 .mu.s from which the cycle time T.sub.c =192 .mu.s follows. ##SPC1##

Although the invention has been described with reference to a specific embodiment it will be appreciated that many other embodiments are possible. For example, the input supply may have more than three phases and the output supply may be d.c. or a.c. of any number of phases. Moreover, the various clock and switching frequencies may be modified to suit other embodiments and applications.