Programmable Delay for Digitizer Circuits

A digitizer circuit is used to digitize an electrical waveform by performing a transformation from an analog to a digital format in order that storage in memory and subsequent data manipulation may be facilitated by the use of digital circuitry. It is known in the prior art, as exemplified by the Hewlett-Packard Model 1150A waveform analyzer, to perform such digitization by sampling a waveform a fixed number of times over a sample window or user-defined width. A disadvantage of such a prior art digitizer is the inability to depict the location on the waveform of the sample window prior to digitization.

The present invention is directed to a digitizer circuit which digitizes a waveform displayed upon a cathode ray tube (CRT) by sampling the output of the CRT vertical amplifier. The user specifies the sample location by specifying the offset between the CRT trigger signal and the first sample, the width of the sample window, and the number of samples to be taken. From these user-specified parameters of microprocessor is used to determine and implement the necessary delay between the CRT trigger signal and each sample taken by a sample-and-hold circuit.

An advantage of the present invention is the high degree of flexibility the user is permitted in defining an arbitrary portion of the displayed waveform as the sample window. Another advantage is the ability to depict the sample window as an intensified portion of the displayed waveform, thereby allowing the user to view the sample window in relation to the entire displayed waveform prior to digitization.

FIG. 1 is a block diagram of a preferred embodiment of the present invention.

FIG. 2 is a block diagram of the intensifier of FIG. 1.

Referring now to FIG. 1 there is shown a block diagram of a preferred embodiment of the present invention. Prior to commencing the digitization process the user enters the user-specified paramters (number of samples desired (N.sub.D), sample window width (W.sub.D), and offset between the trigger signal and the first sample (O.sub.D) into an input 2 of a microprocessor 1 in a conventional manner such as through a panel mounted keyboard or through panel mounted switches. Microprocessor 1 is programmed and interfaced in a conventional manner and may comprise any of a number of commercially available microprocessor chips such as the Intel 8085A.

During operation of the CRT display, whether or not digitization is performed, an input waveform 3 is received at an input node 5 and is amplified by a vertical amplifier 7 before being applied to a CRT 9 to cause vertical deflection of the CRT beam. Input waveform 3 is also used to cause a trigger generator 11 to generate a trigger signal when waveform 3 exceeds a predetermined threshold level. The trigger signal causes a ramp generator 13 to initiate generation of a ramp signal which is amplified by a horizontal amplifier 15 and is used to sweep the beam across the screen of CRT 9. A display circuit 17 used in the present invention operates in a conventional manner and may utilize the same components as those used in commercially available oscilloscopes such as the Hewlett-Packard 1740A.

When a waveform displayed upon the screen of CRT 9 is to be digitized one sample of the waveform is taken during each horizontal sweep of the beam across the screen of CRT 9. Microprocessor 1 is used to determine the time delay (T.sub.D) required between generation of the trigger signal by trigger generator 11 and the time at which the next sample is to be taken. Microprocessor 1 receives the user-specified parameters (N.sub.D, W.sub.D, O.sub.D) at input 2 and receives a sample pulse, described below, at input 3, each time a sample is taken, thereby causing a counter internal to microprocessor 1 to record the total number of samples already taken (S.sub.T). Microprocessor 1 computes T.sub.D as defined by the relation wherein T.sub.D =((S.sub.T W.sub.D)/(N.sub.D -1))+O.sub.D. Microprocessor 1 computes T.sub.D .times.F (F being the oscillation frequency of an oscillator 23) and loads the BCD representation thereof into a counter 19. Counter 19 comprises an 8-digit BCD down-counter having a clock input 21 at which a sinusoidal signal is received from oscillator 23 for causing counter 19 to decrement its count by one for each cycle. It is well within the level of ordinary skill in the art to construct counter 19 from any of a number of commercially available TTL counters such as by cascading, in a conventional manner, 8 Texas Instruments 74LS168A counters. To provide a sampling resolution on the displayed waveform of 100 nanoseconds, oscillator 23 is arranged to oscillate at a frequency (F) of 10 MHz with oscillation starting upon receipt of a trigger pulse from trigger generator 11. Thus, the count within counter 19 will be 0 after T.sub.D .times.F decrements which corresponds to a time delay of T.sub.D after generation of a trigger pulse by trigger generator 11.

A zero detector 24 detects the zero state of counter 19 and generates a sample pulse in response thereto. Zero detector 24 may be implemented by connecting the outputs of all of the flip-flops of counter 19 to a standard TTL NOR gate which generates a logic "1" output when the zero state is achieved. The sample pulse is received at input 3 of microprocessor 1 causing S.sub.T to be incremented as described hereinabove. The sample pulse also causes a sample and hold circuit 25 to sample the output of vertical amplifier 7. For operations involving bandwidths of less than 200 KHz sample and hold circuit 25 may comprise a commercially available device such as the Harris HA-2425. For higher speed operations, sample and hold circuit 25 may comprise a high speed circuit such as that employed in the Hewlett-Packard Model 1810A sampler which provides a bandwidth of approximately 1 GHz.

An A/D converter 27 converts the sampled data resident in sample and hold circuit 25 into a representative 10-bit digital word. A/D converter 27 may comprise any of a number of commercially available circuits which are 10 bits wide and have conversion times of less than 10 microseconds.

The digital representation of the sampled data is stored in a conventional manner in sequential memory locations within a memory 29 which may comprise, for example, a random access memory such as the Intel 2142. In order to later reconstruct the sampled waveform from the stored data it is necessary to also store the time interval between samples (T.sub.I) in memory 29. Microprocessor 1 computes T.sub.I as T.sub.I =(W.sub.D)/(N.sub.D -1) and loads the digital representation of T.sub.I into memory 29. From memory 29 the sampled data may be sent through a data buss in a conventional manner to other devices such as plotters or calculators for further data manipulation. The data may also be used to display the digitized waveform upon the screen of CRT 9 with or without simultaneous display of the real-time waveform by using display circuitry such as that employed in the Hewlett-Packard Model 1350S Computer Graphics Display System.

An important feature of the present invention is the ability to depict at any time that portion of the displayed waveform which is to be digitized as a visually distinct portion of the entire displayed waveform. This feature is implemented by arranging microprocessor 1 to cause an intensifier 31 to write the sample window portion of the displayed waveform at a higher level of intensity than the remainder of the waveform in order to render it visually distinct.

Referring now to FIG. 2, there is shown a diagram of the operation of intensifier 31. It is well known in the prior art to use a positive-going unblanking pulse 55 to bias the grid 59 of CRT 9 above cutoff only while the CRT screen is being swept so as to eliminate any retrace illumination. In order to intensify the sample window portion of the trace, microprocessor 1 operates to trigger an intensity generator 51 into the "on" state with a positive impulse at time O.sub.D (after a trigger pulse is received from trigger generator 11) and into the "off" state with a negative impulse at time O.sub.D +W.sub.D so that intensity generator 51 generates an intensity pulse 53 having a leading edge at time O.sub.D and a trailing edge at time O.sub.D +W.sub.D. Intensity generator 51 may comprise, for example, a pulse generator having a design similar to the unblank generator commonly employed in commercially available oscilloscopes such as the Hewlett-Packard Model 1740A.

Intensity pulse 53 is superimposed onto an unblank pulse 55 to create a grid pulse 57 which is applied to grid 59 of CRT 9. Thus, no trace is present when the grid pulse 57 goes to O (retrace). When the grid pulse 57 comprises only unblank pulse 55 the grid voltage exceeds cutoff and a trace is visible. When grid pulse 57 comprises the superposition of intensity pulse 53 onto unblank pulse 55 the grid voltage is increased, in turn causing the beam current to increase. This increase in beam current appears as an intensified portion of the displayed trace.