Suppression of Edge Effects Arising in CCD Imager Field Registers

The present invention concerns CCD imagers that use field registers and output registers and, more particularly, ones in which edge effects arising in the field register(s) are eliminated from the imager output signal.

In CCD imagers that use separate image and output registers, the output register typically comprises a charge transfer channel the stages of which during selected intervals in time are loaded in parallel from the outputs of charge transfer channels parallelly arranged in a field register. In different types of CCD imagers in which the present invention can find application, this field register may be the image register in which photo-detection takes place, or it may be a field storage register interposed between an image register and the output register. The charge packets loaded parallelly into the output register stages are supplied serially from its output.

The lifetime of charge carriers in the semiconductor substrate on which the imager is formed is relatively long compared to the time for charge integration in the image register, transfer of charge from the image register to the output register and parallel-to-series conversion in the output register. Charge carriers generated in the bulk, rather than in the depletion regions induced by applying voltages to the image register gate electrodes, may diffuse from that portion of the image register across which one charge transfer channel extends to an adjacent charge transfer channel, where they are collected into a depleted region. As between two adjacent charge transfer channels in the image register, this process leads to some loss of spatial resolution in the portions of the image they accumulate charge packets descriptive of. This loss of resolution is in the direction perpendicular to the charge transfer channels. But this process does not affect the total amount of charge collected in the channels.

As between each of the charge transfer channels at the sides of the image register and what lies beside them outside the image register, however, there is substantial probability of the charge collected by that charge transfer channel being appreciably affected, thereby to generate undesirable edge effects. If the sides of the image register are bounded by drain structures--e.g., anti-blooming drains--some charge carriers will pass into the drains and never be collected, reducing from its proper amount the charge collected by the imager. If the sides of a field register (whether image register or field storage register) are bulk substrate, extra charge carriers, generated in that portion of the bulk owing to dark-current-generating effects or to photoemissive response to stray light, will migrate to the charge transfer channels in the sides of the field register and increase from its proper amount the charge collected by the imager.

The CCD imager field registers could have extra charge transfer channels added to each side of them to avoid edge effects in the channels they adjoin, and the charge packets spoiled by edge effects and clocked through these extra channels could be discarded.

It is preferable, in accordance with the invention, to discard the charge packets from the outputs of these extra channels through drains, rather than admitting them into the imager output register. This, to avoid the complexity of having to selectively blank output signals from the imager output register. In an improved CCD imager constructed in accordance with an aspect of the present invention then, the output register is operated so as to admit input charge packets into respective ones of its stages only if they originate in respective ones of the charge transfer channels of the image register exclusive of the side charge transfer channels on each side of the register. This implements the method of suppressing edge effects provided by discarding charge packets from the side charge transfer channels of the image register, rather than admitting them into the imager output register and then blanking the response to these charge packets in the imager output signal, which method is an aspect of the present invention.

In the drawing:

FIG. 1 is a functional diagram of an electro-optical signal processor modified so as to embody the invention;

FIG. 2 is a plan view schematic of a CCD imager constructed in accordance with the invention for use in an electro-optical processor of the sort shown in FIG. 1;

FIG. 3 is a functional diagram of a television camera modified to embody the invention; and

FIG. 4 is a plan view schematic of a CCD imager of the field transfer type constructed in accordance with the invention for use in a television camera of the sort shown in FIG. 3.

The general type of electro-optical signal processor shown in FIG. 1 is described in the article "Incoherent Optical Signal Processing Using Charge-Coupled Devices (CCD's)" by K. Bromley et al. in SPIE Vol. 118--Optical Signal & Image Processing (IOCC 1977) pp. 118-123. This processor comprises a light-emitting diode (LED) 5 providing a regularly flashing light source of modulated intensity for illuminating a light mask 7, which is in contact with an image register 11 of a charge-coupled device (CCD) imager 10. (The mask, shown exploded from the surface of image register, is conveniently made by evaporating a thin layer of chromium on the imager 10 surface, followed by selective etching.) The image register 11 is a field register. It comprises a plurality, M+2>3, of parallelled charge transfer channels consecutively ordinally numbered left to right 0.sup.th through (M+1).sup.st, represented by the columns on the surface of imager 10 facing the viewer. Each channel contains a like number of image integrating sites or pixels. The squares arrayed in row and in column on the CCD surface facing the viewer each represent an image integrating site. The imager 10 departs from usual construction in that in accordance with the invention charge packets integrated in the 0.sup.th and (M+1).sup.st charge transfer channels at the left and right sides of image register are periodically clocked forward to drains connected to a drain voltage V.sub.DD supply. The charge packets integrated on the other, first through M.sup.th, charge transfer channels of image register 11 are periodically clocked forward to respective stages of an output register 12 which performs a parallel-to-series conversion to supply successive samples of an output analog sampled-data sequence g.sub.m.

The input signal temporally modulating the intensity of light from LED 5 is an analog sampled-data sequence

flashed at a sampling rate of r.sub.1 samples per second, n.sub.o being used to designate an arbitrary time origin and n assuming successive integral values at each successive sampling time. Mask 7 contains an M by K array of apertures with respective optical transmittance values h.sub.m,k in registration with respective pixels of the first through M.sup.th charge transfer channels of register 11. The mask 7 aperture patterns over the first and M.sup.th channels adjacent to the 0.sup.th and (M+1).sup.st side channels are essentially repeated (possibly enlarged somewhat) over the side channels, so the side channels tend to integrate charge packets equal to these integrated in the channels adjacent to them. The light falling on the m,k.sup.th element of the CCD will integrate to provide an analog charge packet of amplitude

The vertical shift rate in the imager 10 at which charge packets are clocked upward from one charge integration site to the next is made to equal r.sub.1. So a running sum of the products of the time-varying intensity of LED 5 radiance and the space-varying transmittance of mask 7 apertures in each charge transfer channel is clocked out each cycle of r.sub.1 sampling rate to a respective one of the stages of output register 12. As a row of charge samples is clocked upward in image register 11 from the bottom row (k=n=1) to the top row (k=n=K) the accumulated charge in a column takes on the following value: ##EQU1## This is equivalent to matrix vector multiplication of the following form for given n.sub.o :

The important part of the FIG. 1 processor insofar as the present invention is concerned is that integration errors in the first and M.sup.th columns are reduced by virtue of the operation of the adjoining 0.sup.th and (M+1).sup.st columns. There is a discarding of their clocked-upward outputs to drain supply, rather than their clocked-upward outputs being entered into output register 12. This avoids the complexity of discarding these samples by selectively blanking output register 12 output signal.

FIG. 2 shows a plan-view schematic of the front surface of a CCD imager for use in a processor like that shown in FIG. 1. The columns of pixel locations are consecutively ordinally numbered 0.sup.th through (M+1).sup.st at the top of the figure, and the rows of pixel locations are consecutively ordinally numbered 1.sup.st through K.sup.th at the left side of the figure. The FIG. 2 imager uses two-phase clocking of its buried-channel image register 11 and output register 12, which are constructed with a two-level polysilicon gate architecture. The FIG. 2 imager is designed to be front-surface-illuminated to facilitate the chromium light mask 7, stripped away in FIG. 2 to reveal the underlying CCD structure, being evaporated to an opaque-to-light 500 .ANG. or so thickness on the front surface and then being photo-etched to provide the apertures in registration over image-integrating pixel sites. A metal-oxide-semiconductor field effect transistor MOSFET) 13 provides source-follower output response to potential on a floating diffusion 14 at the output end of output register 12. Floating diffusion 14 is periodically clamped to a direct drain potential V.sub.DR applied to a drain diffusion 15, using properly timed .phi..sub.R1 and .phi..sub.R2 reset pulses applied to successive ones of the intervening pair of reset gates. At the input end of output register 12 a direct source voltage V.sub.s is applied to a source region 16 and bias charges (e.g., "fat zero" charges) can be admitted by applying properly-phased V.sub.IN and V.sub.G pulses to the gates at the beginning of output register 12.

The generation of the two-phase clock signals and the pulses to control the CCD imager operation is per conventional design, so the timing generator for generating these conventional operating voltages is not shown. The conventional feature used in implementing two-phase operation, ion implanted barriers under the trailing edges of the gate electrode structures for the direction of charge transfer, is not shown in FIG. 2 for purposes of clarity. The image or I register 11 has .phi..sub.1I clocking phase applied at two direct bias levels as .phi..sub.1I-T and .phi..sub.1I-S to odd-numbered transfer gates and to odd-number storage gates, respectively, ordinally numbering the gate pairs first through K.sup.th from top of FIG. 2 down. The second clocking phase .phi..sub.2I is applied at two direct bias levels as .phi..sub.2I-T and .phi..sub.2I-S to even-numbered transfer gates and to even-numbered storage gates respectively in image register 11. These clock phases have r.sub.1 repetition rate. Four successive gate electrode structures are associated with each image integrating site or pixel, so one will note the FIG. 2 imager structure is foreshortened in the vertical direction to three pixels per column as compared to the five pixels per column of FIG. 1 imager 10. This foreshortening does not affect the operation insofar as the invention is concerned and is made so the schematic will fit within the confines of a standard sheet without overly reducing the size of important features. Electro-optical signal processors which are practically advantageous for implementing matrix multiplications will, of course, normally have a number M of actively used columns and a number K of pixel rows both much larger than the five shown for each in FIG. 1.

In performing matrix multiplication only the K.sup.th terms of the running sums generated at the outputs of the 1.sup.st through M.sup.th of the imager columns are of interest, and the (K-1) earlier items are discarded. If one clocks all the running sum terms through the output register 12 its clock rate r.sub.2 must equal or exceed M times the clock rate r.sub.1 advancing charge samples through imager register 11, as noted in the description of the FIG. 1 processor 10. Arranging to dump all charge packets in the running sum of each imager column, previous to the K.sup.th, will allow the output register clock rate to be reduced by a factor of K. The reduced output register clock rate r.sub.2 '.gtoreq.(Mr.sub.1)/K.

The FIG. 2 imager has structure for dumping the (K-1) earlier terms in the running sums. The .phi..sub.1I -clock-phase transfer electrode in the K.sup.th row is followed by a first-polysilicon-layer storage electrode 17 that receives a V.sub.GDS pulse in synchronism with .phi.1I-S only when the K.sup.th term charge packets are transfered to wells thereunder, allowing those packets to be clocked forward to side-load the output register 12. When these K.sup.th term charge packets are being clocked forward normally, no V.sub.BG pulse is applied to a second-polysilicon-layer electrode 18 for dumping the charge packets into drain sites 19 at the sides of the charge transfer channels under the storage gate electrode 17. At previous times, when the charge packets descriptive of terms of the running sums previous to the K.sup.th are clocked to wells induced under storage gate electrode 17, no V.sub.GDS pulse is applied to 17 as will permit charge to be clocked forward. Instead V.sub.BG pulse is applied to gate electrode structure 18 overlying storage gate electrode 17 to provide a conductive path through field-effect-transistor action between the charge transfer channels as virtual sources and drain regions 19 connected in common to a direct drain voltage V.sub.GD.

The side-loaded output register 12 is clocked at r.sub.2 ' rate in .phi..sub.10 and .phi..sub.20 phases. The .phi..sub.10 phase is applied at two direct bias levels as .phi..sub.10-S and .phi..sub.10-T to alternate ones of the storage gates and to alternate ones of the transfer gates, respectively, of output register 12. The .phi..sub.20 phase is applied at two direct bias levels as .phi..sub.20-S and .phi..sub.20-T to the remaining storage gates and to the remaining transfer gates, respectively, in register 12. The K.sup.th terms of the running sums of the first through M.sup.th columns are supplied seriatim at r.sub.2 ' clock rate to floating diffusion 14 and voltages proportional to the charge under floating diffusion 14 are provided at the source of source-follower transistor 13.

The details of FIG. 2 imager construction set forth above are incidental to the invention in which extra charge transfer channels are placed alongside the field register used for imaging. The 0.sup.th channel at the left side and the (M+1).sup.st channel at the right side of this image register 11 do not have outputs to stages in the output register 12, in accordance with the invention, but instead terminate in drain regions 20 and 21, respectively, each returned to V.sub.DR drain potential. The charge packets spoiled by edge effects are dumped into drains 20 and 21, and there is no need to selectively blank responses to these charge packets in the output from floating diffusion 14 or from source-follower 13.

FIG. 3 is a schematic of a CCD black-and-white television camera in which the invention is used. A conventional camera lens and iris assembly is used to project an image onto the A or image register 31 of a CCD imager 30 of the field transfer type. The image is preferably projected so that it overscans the first through M.sup.th columns of the A register 31 and that the edge portions of it fall on the 0.sup.th and (M+1).sup.st columns of A register 31. Image integration takes place over a field scan interval during which time the clocking to the A register 31 is halted. Charge packets sampling the previous integrated image and subsequently transfered to the field store or B register 32 are, during the current image integration time, clocked forward in the B register 31 one row at a time during line retrace intervals. The charge packets sampling image that are clocked out of the 1.sup.st through M.sup.th columns of the B register 32 are side-loaded into the output or C register used for parallel-to-series conversion. The charge packets sampling edge portions of the image, anomalous due to edge effects, are drained off to V.sub.DD drain voltage supply in accordance with the invention. During line trace the C register is clocked at pixel scan rate to provide a line of video samples to processing amplifier 35, which inserts synchronizing pulses to generate camera output signal. Processing amplifier 35 responds to the same timing generator (not shown) as is used to time the clocking signals applied to A register 31, B register 32 and C register 33 of imager 30.

Image integration takes place only in the A register 31. A mask 34, shown in cut-away to reveal the connections of registers 31, 32 and 33 is used to shield B register 32 and C register 33 from light. The mask 34 which can be evaporated directly on the CCD imager surface and photo-etched to final dimensions, may overlap the last few rows of the A register, to avoid light creeping past the mask into B register 32. (This is not shown).

Between image integration times, coincidental with field retrace, both the A register 31 and B register 32 are clocked to transfer the charge packets sampling the image field, which have been integrated in A register 31, from that register to B register 32. In FIG. 3 the charge packets clocked out of the 0.sup.th and (M+1).sup.st columns of A register 31 are forwarded to corresponding columns in B register 32, which terminate in drains 20 and 21. This is advantageous in that charge carriers thermally generated in the bulk underlying the B register 32 exchange in like numbers from below each of the 0.sup.th and 1.sup.st or M.sup.th and (M+1).sup.st columns to below the other, before collection in the charge transfer channel wells, thus avoiding an edge effect that can become noticable at higher camera temperatures.

However, the preponderant portion of charge packets in the B register 32 are forwarded from A register 31 and thus are already collected in depletion regions from which they cannot escape back into the bulk. So, one may alternatively terminate the 0.sup.th and (M+1).sup.st columns of the A register in drains, rather than forwarding their outputs to corresponding columns in the B register. And then in a further variant one may then dispense with the 0.sup.th and (M+1).sup.st columns in the B register 32. Or in a still further variant one may retain the 0.sup.th and (M+1).sup.st columns in the B register and use one or the other or both of them for integrating dark current to implement schemes for reducing field shading attributable to dark currents.

Color television cameras using the invention are, of course, possible. A color pattern filter may be interposed between the camera lens and iris assembly 25 and A register 31 to modify the FIG. 3 camera for color operation; this is the so-called "single-chip" color camera approach. A better color television camera can be constructed using a color-separating beam-splitter following the camera lens and iris assembly 31 and projecting the separated colors into the A registers of CCD imager 30 and of further CCD imagers of like type. The separated colors may, for example, be the additive primaries, so the imagers supply R,G,B (red, green, blue) video output signals to be matrixed in the processing amplifier. Or, as a further example, the separated colors may be the additive complementary colors cyan, magenta and yellow.

FIG. 4 shows a plan view schematic of the front surface of a back-surface-illuminated field transfer type of CCD imager suitable for use in a television camera of the sort shown in FIG. 3. The A register 31 and B register 32 are each shown as comprising seven columns and three rows, this foreshortening in each direction being done to accomodate drafting limitations. Typically between 300 and 500 columns and between 200 and 600 rows are actually used in these registers, with the C register 33 being lengthened to suit. FIG. 4 is also simplified not to show certain standard construction features of a CCD imager for television camera use--e.g., the anti-blooming drain structures--this also being an accomodation to drafting limitations. The columns of the A register 31 and B register 32 (separated by channel stops indicated by dashed line) are consecutively ordinally numbered 0.sup.th through (M+1).sup.st at top of figure; and the rows of each register are consecutively ordinally numbered first through K.sup.th. Three-level polysilicon gate electrode structures are used, and the A, B, and C register are all three-phase-clocked. Channels for charge transfer are shown by stippling and channel stops are left unstippled. The imager is designed for interlaced field operation, with the gate electrodes in the A register 31 receiving the first-phase .phi..sub.A1 of the three-phase A-register clocking being twice as long as those receiving the second phase .phi..sub.A2 and third-phase .phi..sub.A3 of the A register clocking. This provides perfect interlace and no field flicker, charge collection being under the .phi..sub.A1 gate electrodes during a set of alternate fields and being under the .phi..sub.A2 and .phi..sub.A3 gate electrodes during the intervening set of alternate fields. Imagers using a different number of phases in A-and-B-register clocking and in C-register clocking may, of course, be used in the invention. Source-follower output from an MOS transistor 36 with gate supplied from a floating diffusion 37 is shown, though other known methods of extracting signal from the C register 33 may be used instead.

The features of the FIG. 4 CCD imager of primary interest to the invention are, firstly, the drain 38 terminating the 0.sup.th column charge transfer channel after the B register 32 and, secondly, the drain 39 terminating the (M+1).sup.st column charge transfer channel after the B register 32.