High Frequency Differential Amplifier With Adjustable Damping Factor

The present invention relates to differential amplifiers in general, and in particular to a differential amplifier with active transient response correction.

In high-frequency amplifiers, it is generally desirable to have a means by which the transient response of an individual stage can be varied, primarily to compensate for variations in the active devices which occur during the manufacturing process. Typically, transient-response adjustments (also known as high-frequency compensation or signal peaking) are made by varying the values of reactive passive elements such as capacitors or inductors in the signal path. The conventional transient-response adjustment method is found to be lacking in several respects. First, reactive components (or the tools used to adjust them) often introduce parasitic reactances into the circuit which compromise performance. Second, with the advent of micro-miniaturization of amplifiers in the form of integrated circuits, the sensitive circuit nodes which require adjustment are often inaccessible. Third, reactive passive elements are often expensive, and the costs are cumulative where several amplifier stages are required. Finally, the conventional methods for transient-response adjustments do not lend themselves to automatic or programmable control, or to cases in which functional control of transient response is desirable, e.g., such as with temperature or signal strength.

In accordance with the present invention, a high-frequency differential amplifier comprising an emitter-coupled pair of transistors has a buffer stage connected to each side of the differential amplifier in such a way that each buffer stage provides an input path as well as a feedback path for the respective sides. Each buffer stage comprises an emitter-coupled pair of transistors in which the standing currents are equally balanced (although this is not critical), and the base-emitter junction of the transistor on each respective side of the differential amplifier is coupled across the collector-to-base junction of one of the transistors of the emitter-coupled pairs of the respective buffer stage. In operation, an input signal is transmitted across the bases of the buffer stage emitter-coupled pairs of transistors and appears at the emitters of the differential amplifier transistors. Because the transconductance (gm) is proportional to the collector current (I.sub.c) of a transistor, the transconductance may be varied by varying the standing current therethrough. Exploiting this phenomena, the standing current for each of the emitter-coupled pairs of transistors is provided by a variable current source. And because the frequency response of transistor is related to gm (and the damping factor related to 1/gm), the bandwidth and step response of the emitter-coupled pair may be adjusted by varying the current through the devices. Furthermore, this adjustment may be made with little, if any, affect on the gain and dynamic range of the differential amplifier, so that those parameters remain nearly constant.

Among many useful applications for the differential amplifier of the present invention is its use as an error amplifier in a cascode feed-forward amplifier, which is known in the industry as the "cascomp" amplifier as taught by Patrick A. Quinn in U.S. Pat. No. 4,146,844. Here, the apparent damping factor of the cascomp amplifier amplifier circuit may be adjusted by varying a single DC bias control which varies simultaneously a pair of current sources for the two respective buffer stages for the error amplifier.

It is therefore one object of the present invention to provide a high frequency differential amplifier with adjustable bandwidth and step response while gain and dynamic range remain nearly constant.

It is another object of the present invention to provide a differential amplifier having a pair of buffer input stages in which the damping factor of the step response may be adjusted by varying a DC bias current.

It is an additional object of the present invention to provide a buffered error amplifier for a cascomp amplifier circuit such that the apparent damping factor of the step response of the cascomp circuit can be adjusted by application thereto of an external control DC voltage.

Other objects, features, and advantages of the present invention will become apparent to those having ordingary skill in the art upon a reading of the following detailed description when taken in conjunction with the accompanying drawings.

FIG. 1 shows a buffered differential amplifier having adjustable damping factor of the step response in accordance with the present invention; and

FIG. 2 shows a practical embodiment of the present invention in a cascomp amplifier circuit.

Referring to FIG. 1 of the drawings, there is shown a differential amplifier comprising transistors Q1 and Q2, the emitters of which are coupled together by a signal-current-developing resistor 10. The emitter of transistor Q1 is coupled to a suitable negative supply voltage -V.sub.EE via a constant current sink 12, which produces a standing current I.sub.E for transistor Q1. Likewise, the emitter of transistor Q2 is coupled to the supply voltage -V.sub.EE via a constant current sink 14, which produces a standing current I.sub.E for transistor Q2. The collectors of Q1 and Q2 are shown connected to a suitable positive supply voltage +V.sub.cc, and since a signal current I.sub.s is developed across resistor 10 having a value R.sub.E, the collector current of transistor Q1 is I.sub.E +I.sub.s and the collector current of transistor Q2 is I.sub.E -I.sub.s. This is based on the assumption, of course, that transistors Q1 and Q2 have high beta characteristics so that base current is negligible and nearly all of the emitter current I.sub.E is conducted as collector current as well. As a practical matter, however, there will be a finite amount of base current in these devices, but for an understanding of the present invention, the ideal case is presented for simplicity.

A buffer stage on the Q1 side (left-hand side) of the differential amplifier comprises transistors Q3 and Q4, the emitters of which are connected together and coupled to the negative supply -V.sub.EE via a current sink 16. The base of transistor Q3 is connected to an input terminal 18, while the base of transistor Q4 is connected to the emitter of differential amplifier transistor Q1. Note also that the base of transistor Q1 is connected to the collector of transistor Q4. A double-collector current-mirror transistor Q5 has the base and one collector thereof connected to the collector of transistor Q3, while the other collector thereof is connected to the collector of transistor Q4 and to the base of transistor Q1. The emitter of transistor Q5 is coupled to a suitable bias voltage V.sub.pp. The purpose of current-mirror transistor Q5 is to split the current I.sub.T produced by current sink 16 equally between transistors Q3 and Q4, although a current imbalance will not destroy operation of the buffer stage. It should be pointed out that there are many ways in which the load rquirements of transistors Q3 and Q4 may be achieved; the current mirror technique is appropriate for this design.

A substantially idential buffer stage on the Q2 side (right-hand side) of the differential amplifier comprises emitter-coupled transistors Q6 and Q7, current sink 20, input terminal 22, and double-collector current-mirror transistor Q8. Here again, the current-mirror transistor Q8 splits the current I.sub.T produced by current sink 20 equally between transistors Q6 and Q7.

In operation, input signals +V.sub.IN /2 and -V.sub.IN /2 applied to input terminals 18 and 22, respectively, are transmitted to the bases of transistors Q4 and Q6, respectively, and hence the signal V.sub.IN is developed across resistor 10 to produce the signal current I.sub.s. The signals + and -V.sub.IN /2 are replicated at the bases of Q4 and Q6, respectively, due to the wqual standing currents in transistors Q3-Q4 and Q6-Q7, the negative feedback action of transistors Q1 and Q2 emitters on transistors Q4 and Q6 bases, respectively, and the high open loop voltage gain from the base of transistor Q3 to the base of transistor Q1, and from the base of transistor Q7 to the base of transistor Q2. Accordingly, again assuming the gigh beta factors of transistors Q1 and Q2, the value of signal current I.sub.s is equal to V.sub.IN /R.sub.E.

The transconductance (gm) of the transistor is gm.apprxeq.I.sub.c /V.sub.T, where I.sub.c is the collector current and V.sub.T is the well-known voltage equivalent of temperature whereby V.sub.T =kT/q, k being the Boltzmann constant in joules per degree Kelvin, T being the temperature in degrees Kelvin, and q being the magnitude of charge on an electron. While not derived mathematically here because it is shown in many textbooks, frequency response of the transistor is proportional to the transconductance gm. The open loop voltage gain of the feedback triple Q1-Q3-Q4 is proportional to the gm of Q3 and Q4. Therefore, the colosed-loop frequency response changes as the gm is varied. Furthermore, since this adjustment is made in the buffer stage transistors, little, if any, affect is made on the gain and dynamic range of the differential amplifier (transistors Q1 and Q2), so that these parameters remain nearly constant. To this end, current sinks 16 and 20 are shown to be variable current sources, adjustment of which adjusts the bandwidth and step response of transistors Q3-Q4 and transistors Q6-Q7 for optimum performance. It should be pointed out that current sinks 16 and 20 could be adjusted separately; however, if transistors Q3, Q4, Q6 and Q7 are substantially identical, such as may be attained by integrated circuit processes, current sinks 16 and 20 may be adjusted by a single current-source control 27 as shown. There are many ways in which this current-source control may be implemented, such as an adjustable DC bias control or even programmable DC voltages provided by computer control.

FIG. 2 shows a practical implementation of the high-frequency differential amplifier of the present invention in a cascode feed-forward (cascomp) amplifier wherein reference numerals of FIG. 1 are retained. The cascomp amplifier comprises main-channel differential amplifier transistors Q10 and Q11, the emitters of which are coupled together through a signal-current developing resistor 30. Current sinks 32 and 34 provide main-channel standing current I.sub.M. Input signals are applied between input terminals 36 and 38, and resistors 40 and 42 are suitable bias resistors. The cascode feature is provided by common-base amplifier transistors Q12 and Q13, the emitters of which are connected respectively to the collectors of transistors Q10 and Q11. Resistors 50 and 52 having a value R.sub.C are connected between the bases of transistors Q12 and Q13 to produce an error signal which results in correcting alpha-induced error. The collectors of transistors Q12 and Q13 are connected via suitable load resistors 54 and 56, respectively, to the positive voltage supply. Output terminals 60 and 62 are connected respectively to the collectors of transistors Q12 and Q13. The error amplifier is connected such that the inputs are connected across the collectors of transistors Q10 and Q11 and the outputs are cross-coupled to the collectors of transistors Q12 and Q13. Cascomp amplifiers of this type are fully described in U.S. Pat. No. 4,146,844 to Patrick A. Quinn and U.S. Pat. No. 4,322,688 to Kenneth G. Schlotzhauer et al.

Current sinks 16 and 20 are herein shown as transistors Q14 and Q15, the bases of which are connected together and to the base of a diode-connected (collector to base) trnsistor Q16. A variabele resistor 70 such as a potentiometer is connected between the collector of transistor 16 and supply voltage +V.sub.cc to adjust the DC bias of transistors Q14 and Q16, and hence to adjust the currents I.sub.T for transistors Q3, Q4, Q6 and Q7, which are assumed to be substantially identical. Also shown indirectly connected by a dashed line to the bases of transistors Q14 and Q15 is a programmable DC bias control circuit 80, which may be a suitable computer-controlled device for providing DC bias voltages for adjustment of the currents I.sub.T produced by current-sink transistors Q14 and Q15. This to indicate that as an alternative to bias control potentiometer 70, the bias control voltages may be programmed or provided under computer control.

It should be noted that for best performance, the error amplifier should be an ideal transconductance amplifier. The configuration provided here approaches that ideal in that the feedback provided by the emitter-to-base connections of transistors Q1 and Q2 yields high linearity and low thermal distortion, while the buffering action of transistors Q3-Q4 and Q6-Q7 requires low input bias current so that the beta loading of transistors Q12 and Q13 is low and error cancellation improves.

In practice, the error signal appearing at the emitters of transistors Q12 and Q13 is peaked at high frequencies by resistors 50 and 52 and parasitic inductance in the bases of transistors Q12 and Q13. Therefore, the error signal at high frequencies is larger than necessary to correct for gm and alpha losses. By varying the buffer stage currents I.sub.T, the bandwidth of the error amplifier may be adjusted to pass the desired amount of high frequency correction to the output. This results in an apparent variation in the damping factor of the transient response of the cascomp amplifier circuit.

While I have shown and described a preferred embodiment of my invention, it will be apparent to those skilled in the art that many changes may be made without departing from my invention in its broader aspects. The appended claims therefore cover all such changes and modifications as fall therewithin.