Data Searching Apparatus

The present invention relates to a data searching apparatus, and more particularly to a data searching apparatus for searching a record which meets a certain condition from records transferred to a data processing unit.

In a prior art method for searching a record based on the result of field-by-field comparison of records transferred from an external storage unit, such as a magnetic tape unit or a magnetic disc unit, to a data processing unit, the data read from the storage unit is stored in a buffer area of the main storage unit in the data processing unit through a channel and the records are fetched one at a time to an area of the main storage unit referred to by a program and the results are logically operated on by the program. In such a prior art method, however, the search speed is influenced by the instruction execution time of the processor which processes the program and a high speed processor is required to attain a high search speed. Such a high speed processor is usually expensive and hence has a low cost-performance.

In order to improve the search speed, a method has been proposed in which a data searching facility is imparted to a storage control unit. In this method, when field data is transferred from the storage unit to the storage control unit, the storage control unit compares the field data one field at a time with predetermined data and sets the results in latches. The latched data is logically operated on by a microprogram before the next data is transferred to check whether or not the respective records meet the search condition and a record which meets the search condition is processed.

In this method, however, in order for the microprogram processing to be executed within the time gap between the records, it is necessary to stop the transfer of the next record from the storage unit to the storage control unit or to set a gap passing time to be longer than the execution time of the microprogram. As a result, when a plurality of records are sequentially processed, the processing performance is lowered in proportion to the execution time of the microprogram. In addition, because of the presence of the gaps, the blocking of the records is not attained.

In order to allow the field-by-field comparison of the blocked records and the logical operation based on the comparison results without a time delay, a hardware execution without microprogram has been proposed. In this method, however, since undesired field data is also stored in the buffer memory in storing a compare-equal data, the utilization efficiency of the buffer memory is low and wasteful transfer time from the storage control unit to the channel is included because not only the desired fields but also other fields in the same record are stored in the buffer memory when the record meets the search condition.

It is an object of the present invention to provide a data searching apparatus which can utilize a buffer memory efficiently and reduce the data transfer time.

In order to achieve the above object, in accordance with a feature of the present invention, the results of field-by-field comparison of records from a storage unit with reference data are logically operated on and only a desired field in a compare-equal record is stored in a buffer memory.

FIG. 1 shows a schematic block diagram of a system including a data searching apparatus of the present invention.

FIG. 2 shows a configuration of one embodiment of the data searching apparatus of the present invention.

FIG. 3 shows a configuration of a latch circuit shown in FIG. 2.

FIG. 4 shows a configuration of a logical operation circuit 33 shown in FIG. 2.

FIG. 5 shows a configuration of a control unit shown in FIG. 2.

FIG. 6 shows a configuration of a major portion of another embodiment of the data searching apparatus of the present invention.

FIG. 7 shows an overall configuration of other embodiment of the data searching apparatus of the present invention.

FIG. 8 shows a configuration of a control unit shown in FIG. 7.

FIG. 1 shows a schematic block diagram of the data searching apparatus of the present invention.

When field data forming a record is transferred from a storage unit 1 to a storage control unit 2, the storage control unit 2 compares the field data, one field at a time, with predetermined data and logically operates on the results to check whether or not the record meets a search condition, and if it meets the search condition, the storage control unit 2 stores a desired field of the record in a buffer memory. It then reads out the content of the buffer memory and transfers it to a data processing unit 4 through a channel 3.

FIGS. 2, 3 and 4 show embodiments of the data searching apparatus of the present invention.

FIG. 2 shows a block diagram of one embodiment of the storage control unit 2 shown in FIG. 1, FIG. 3 shows a circuit diagram of the latch circuit 32 shown in FIG. 2, FIG. 4 shows a circuit diagram of the logical operation circuit 33 shown in FIG. 2, and FIG. 5 shows a circuit diagram of the control unit 34 shown in FIG. 2. It is now assumed that each of the records R1, R2, . . . stored in the storage unit 1 has four fields F.sub.1, F.sub.2, F.sub.3 and F.sub.4 indicating name, sex, payroll and age, respectively, and that the fields required by the data processing unit 4 (called selection fields) are fields F.sub.1 (name) and F.sub.4 (age). It is further assumed that the following search condition (query) is set: "Indicate names and ages of employees whose sex is male, whose payroll is no less than 150,000 and whose age is no older than 30." The lengths and the attributes of the fields F.sub.1 -F.sub.4 are set in field length buffers 22 of a field length buffer unit 21. The lengths l.sub.1 -l.sub.4 are set in field length areas 24 of the respective field length buffers 22 for the fields F.sub.1 -F.sub.4, "1"s are set in selection field flag areas 25 of the field length buffers 22 for the fields F.sub.1 and F.sub.4, "1"s are set in compare field flag areas 27 of the field length buffers 22 for the fields F.sub.2, F.sub.3 and F.sub.4, and "1" is set in a last field flag area 26 of the field length buffer 22 for the field F.sub.4. Compare data V.sub.1 -V.sub.3 is set in compare data buffers 29 of a compare data buffer unit 28 in the order of the compare fields F.sub.2, F.sub.3 and F.sub.4. In the present example, V.sub.1 ="male", V.sub.2 =" 150,000" and V.sub.3 ="30 years old". Compare conditions C.sub.1 are set in a compare condition register 30 in the order of the compare fields F.sub.2, F.sub.3 and F.sub.4. In the present example, C.sub.1 ="=", C.sub.2 =".gtoreq." and C.sub.3 =".ltoreq.". A compare circuit 31 compares the data for each of the fields F.sub.2, F.sub.3 and F.sub.4 and signals on a line 36 indicating the compare results are set in a latch circuit 32. As shown in FIG. 3, the latch circuit 32 comprises latches 49-1-49-4 one for each of the fields F.sub.1 -F.sub.4 (L.sub.1 -L.sub.4 indicating the contents of the latches), a decoder 47 responsive to a signal on a line 44B for controlling the storing of the compare result on the line 36 to the selected one of the latches 49-1-49-4, and four AND gates 48-1-48-4. Signals on output lines 37 of the latches 49-1-49-4 of the latch circuit 32 are supplied to a logical operation circuit 33 where they are checked by a circuit to determine whether or not they meet the predetermined condition.

FIG. 4 shows the configuration of the logical operation circuit 33. It comprises a latch circuit 11 (having a content M.sub.ij corresponding to the content L.sub.j of the latch circuit 32) which is set and reset by a microprogram or other means, OR circuits 12 and 13, an AND circuit 14 and a latch circuit 15 for storing a result X, and it carries out the following logical operation:

The search condition (query) described above is expressed by a logical expression of

The logical operation circuit 33 is conditioned from a control unit 34 through a line 43 such that it produces a signal "1" on a line 38 when the signals on the output lines 37 of the latch circuit 32 meet the above logical expression.

After the initialization set forth above, data transfer from the storage unit 1 is started. In the field length buffer unit 21, the information relating to the field F.sub.1 is set into the field length register 23 from the field length buffer 22. The field length area 24, the selection field flag area 25, the last field flag area 26 and the compare field flag area 27 of the register 23 are sent to the control unit 34 through lines 42, 41, 40 and 39, respectively. The field length area 24 and the compare field flag area 27 are also supplied to the compare circuit 31 and the latch circuit 32, respectively, through the lines 42 and 39. As shown in FIG. 5, the control unit 34 sets the field length area supplied from the line 42 into a field length counter 50. When the data transfer from the storage unit 1 is started, the counter 50 is counted down in synchronism with a data transfer clock CLK generated by a clock generator (not shown). On the other hand, the data read from the storage unit 1 is supplied to the compare circuit 31 through a line 61 and also to a buffer memory 35 through a line 62.

Processing for the field F.sub.1

Since the field F.sub.1 is a selection field, the selection field flag 25 on the line 41 is "1". The control unit 34 sends the clock CLK to an address counter 52 through an AND gate 51 to increment the address counter 52, which initially stores a start address of an area in the buffer memory 35 in which the field F.sub.1 is to be stored. The buffer memory 35 sequentially stores the data of the field F.sub.1 supplied from the line 62 in an area specified by a signal on an output line 45 of the address counter 52.

On the other hand, since the field F.sub.1 is not the compare field and hence the compare field flag 27 on the line 39 is "0", the control unit 34 does not activate the compare data buffer 28. Accordingly, the signal on the output line 36 of the compare circuit 31 is not significant. Since the compare field flag 27 on the line 39 is "0", the latch circuit 32 does not latch the output on the output line 36 to any latch. Accordingly, the outputs on the lines 37 of the latch circuit 32 do not change and all lines 37 have "0" outputs. As a result, the output of the logical operation circuit 33 indicates non-equal. When the readout of the data of the field F.sub.1 is completed, the output of the counter 50 assumes "0". When the decoder 53 detects this condition, it produces a "1" output. Since the last field flag 26 on the line 40 supplied to the AND gates 54 and 55 is "0", the outputs of the AND gates 54 and 55 remain "0" and the contents of the address counter 52 and the register 60 do not change. Since the compare field flag 27 from the line 39 is "0", the output of the AND gate 57 is "0" and a signal on an output line 44A of the counter 59 remains at the initial count "0". When the output of the decoder 53 changes to "1", the counter 58 is incremented from the initial count "0" to count 1. The "1" output of the decoder 53 is sent to the field length buffer unit 21 through the line 46 so that the field length information relating to the next field F.sub.2 is set into the register 23. The field length l.sub.2 is set into the counter 50. Thus, the processing for the field F.sub.1 is completed.

Processing of the field F.sub.2

The field F.sub.2 is not a selection field. Since the selection field flag 25 on the line 41 is "0", the output of the AND gate 51 is "0". Accordingly, the control unit 34 does not increment the address counter 52 and does not write the data of the field F.sub.2 from the line 62 into the buffer memory 35.

On the other hand, since the field F.sub.2 is a compare field, the control unit 34 responds to the "1" compare field flag 27 on the line 39 to activate the compare data buffer unit 28, which responds to the "0" signal supplied from the counter 59 of the control unit 34 through the line 44A to supply the first compare data V.sub.1 and the compare condition C.sub.1 to the compare circuit 31. When the data having a length equal to the field length l.sub.2 designated by the signal on the line 42 is supplied to the compare circuit 31 from the storage unit 1, the compare circuit 31 compares the data of the field F.sub.2 so far supplied with the compare data V.sub.1 and the compare condition C.sub.1 supplied from the buffer unit 28 and produces a result on the line 36. This output is sent to the latch circuit 32, which stores the output in the latch 49-2 which corresponds to the count 1 of the counter 58 of the control unit 34 supplied through the line 44B. Since the content of the counter 50 becomes 0 when the field F.sub.2 is compared, the "1" output of the decoder 53 of the control unit 34 causes the count of the counter 59 to be incremented from 0 to 1 and the count of the counter 58 to be incremented from 1 to 2. The signal on the output line 46 of the decoder 53 causes the field length information relating to the next field F.sub.3 to be set into the field length register 23. Thus, the processing for the field F.sub.2 is completed.

Processing for the field F.sub.3

Since the field F.sub.3 is not a selection field, the data of this field is not written into the buffer memory 35. Since this field is a compare field, the data is compared with the compare data V.sub.2 and the compare condition C.sub.2 and the result is stored in the latch 49-3 of the latch circuit 32, in the same manner described for the field F.sub.2. When the processing is completed, the field length data relating to the field F.sub.4 is stored in the field length register 23.

Processing for the field F.sub.4

Since this field is a selection field, the address counter 52 is incremented in synchronism with the clock CLK as was done for the field F.sub.1 and the data of this field is stored in the area of the buffer memory 35 next to the area in which the data of the field F.sub.1 was stored.

On the other hand, since this field is also a compare field, the compare operation is carried out as was done for the fields F.sub.2 and F.sub.3 and the result is stored in the latch 49-4 of the latch circuit 32. When the readout of the data of the field F.sub.4 is completed, the decoder 53 of the control unit 34 assumes "1". The control unit 34 operates in a different manner depending on whether the signal on the output line 38 of the logical operation circuit 33 is "1" or "0".

When the signal on the output line 38, the output of the decoder 53, and the last field flag 26 are all "1", the output of the AND gate 55 is "1". This "1" output causes the address register 60 to read in the output of the address counter 52. The content of the address counter 52 does not change. Accordingly, the data of the next record R2 is stored at the next address to the count of the address counter 52. The address register 60 is used to store the data of the next record R3 in the buffer memory 35 when no compare-equal is detected for the record R2. As a result, the data of the fields F.sub.1 and F.sub.4 in the buffer memory 35 is retained.

When the signal on the output line 38 is "1", the output of the AND gate 54 is "0" because the inversion of the signal on the output line 38 of the logical operation circuit 33 by an inverter 56 is applied to the AND gate 54. In response to the output of the AND gate 54, the content of the address register 60, that is, the initial value used to store the data of the field F.sub.1 to the buffer memory 35 is set into the address counter 52. Accordingly, in the course of the search for the record R1, the result of the search for the next record R2 is stored in the area of the buffer memory 35 in which the data of the fields F.sub.1 and F.sub.4 were stored. As a result, the data for the record R1 stored in the buffer memory 35 is erased.

Similarly, the search and store operations for the next records R2, R3, . . . are carried out and only the selection fields of the compare-equal records are stored in the buffer memory 35.

The construction described above offers the following advantages. Since the records are searched in synchronism with the record transfer rate and only the necessary fields of the records are stored in the buffer memory 35, the buffer memory 35 can be efficiently used, the number of times of overflow of the buffer memory is reduced, the amount of data transferred to the central processing unit is reduced, the load to the central processing unit is reduced and hence the processing time is reduced.

In the embodiment described above, the compare operation only for the respective fields of a record and the compare data thereof is carried out and the compare operation for the fields between records cannot be carried out, and hence it is insufficient for the purpose of a complete data search. For example, when a series of annual records include fields for budget, travel expense and outside service fee and when it is desired to search a year the recent five years in which the outside service fee is lowest, an interfield comparison is necessary.

In another embodiment of the present invention, in order to meet the above requirement, the result of comparison of the field data with the compare data and the result of comparison between the fields can be logically operated on without time delay and only the necessary fields for the search of the record are stored in the buffer memory.

The embodiment for performing the above operation is now explained with reference to FIGS. 6, 7 and 8.

FIG. 6 shows a logical sequence chart of a search condition coincidence circuit of the data searching apparatus in accordance with the present embodiment. FIG. 7 shows a block diagram of the data searching apparatus, and FIG. 8 shows a major portion of FIG. 7.

Referring to FIG. 6, data F.sub.1 -F.sub.8 forming records R1 and R2 is supplied from the storage unit 1 to a compare circuit 140 and compared with the content of compare data 141 by conditions stored in a compare condition register 139, and if the conditions are met, "1"s are set in latchs 114-1-114-3 (having contents L.sub.1 -L.sub.3) of a compare result latch circuit 116, and if the conditions are not met, "0"s are set therein. They are logically operated on with preset contents of logical operation latches 117, 119 and 121 by logical operation circuits 133-136 to search the records. The setting of the latches 114-1-114-3 is carried out by opening AND gates 113-1-113-3 by a decoder 115.

The above function is identical to that of the search method in the first embodiment.

The field data F.sub.1 -F.sub.8 from the storage unit 1 is set into registers 146 and 147 by an output of a decoder 123 and the fields are compared with each other by conditions stored in registers 142 and 143 in compare circuits 144 and 145, and if the conditions are met, "1"s are set to latches 112-1-112-4 of a compare result latch circuit 126, and if the conditions are not met, "0"s are set therein. Setting of the data into the latches 112-1-112-4 is carried out by opening AND gates 111-1-111-4 by outputs of decoders 123-125. They are logically operated on with preset contents of logical operation latches 127, 129 and 131 by logical operation circuits 133-136 to search the records.

The above function is newly added in the present embodiment.

In FIG. 6, the content of the latch 114 is represented by L.sub.j, the contents of the latches 117, 119 and 121 are represented by M.sub.ij, the content of the latch 112 is represented by L.sub.j ' and the contents of the latches 127, 129 and 131 are represented by M'.sub.ij. Thus, the circuit of FIG. 6 carries out the following operations: ##EQU1##

In the expression (2) above, any plurality of L.sub.i and L'.sub.i selected from the compare results L.sub.1, L.sub.2, L.sub.3, . . . L.sub.n, L'.sub.1, L'.sub.2, . . . L'.sub.m are logically ANDed. It represents that any numbers are selected from the compare result latch circuits 116 and 126. By placing the expressions (1) and (1') into the expression (2), we get ##EQU2##

When X.sub.1 represents the output of the AND circuit 133, X.sub.1 is represented by the following expression when numbers L.sub.1, L.sub.2, L'.sub.1 are selected.

In order to determine X.sub.1, M.sub.11, M.sub.12, M'.sub.11 of the logical operation latches 117 and 127 are set to "1" and M.sub.13, M'.sub.12, M'.sub.13, M'.sub.14 are set to "0", and the contents of the compare result latches 116 and 126 and the invested outputs of the corresponding logical operation latches 117 and 127 are logically ORed by the OR circuits 118 and 128. The operation is represented by the following expression: ##EQU3##

By carrying out a logical OR operation for the terms X.sub.i of the logical AND in accordance with the following logical expression, any logical operation expression can be prepared.

When the logical operation expression includes an unnecessary logical AND term, it can be deleted in the following manner. Let us assume that the logical AND term X.sub.3 (output of the AND circuit 135) is to be deleted to perform the following operation.

In this case, the contents M.sub.31, M.sub.32, M.sub.33, M'.sub.31, M'.sub.32, M'.sub.33 and M'.sub.34 of the logical operation latches 121 and 131 are set to "1". Thus,

This is a sufficient condition for X.sub.1 and X.sub.2 to be met. Thus, under any conditions for X.sub.1 and X.sub.2, it is not possible that X.sub.1 and X.sub.2 are not met and X.sub.3 is met. Whenever X.sub.3 is met, X.sub.1 and X.sub.2 are always met.

In this manner, any logical operation term X.sub.i can be deleted.

Let us now assume that the following logical expression is to be carried out:

In this case, the contents M.sub.11, M.sub.12, M.sub.13, M'.sub.11, M'.sub.12, M'.sub.13, M'.sub.14 of the logical operation latches 117 and 127 are set to "1", "0", "1", "0", "0", "0", "0", respectively, so that X.sub.i of the AND circuit 133 assumes L.sub.1 .LAMBDA.L.sub.3, the contents M.sub.21, M.sub.22, M.sub.23, M'.sub.21, M'.sub.22, M'.sub.23, M'.sub.24 of the logical operation latches 119 and 129 are set to "1", "1", "0", "1", "0", "1", "0", respectively so that X.sub.2 of the AND circuit 134 assumes L.sub.1 .LAMBDA.L.sub.2 .LAMBDA.L'.sub.1 .LAMBDA.L'.sub.3, and the contents M.sub.31, M.sub.32, M.sub.33, M'.sub.31, M'.sub.32, M'.sub.33, M'.sub.34 of the logical operation latches 121 and 131 are set to "1", "1", "1", "1", "1", "1", "1", respectively, so that X.sub.3 of the AND circuit 135 is not "1" unless all of the contents of the compare result latches 116 and 126 are "1" because all inputs to the OR circuits 122 and 132 from the logical operation latches 121 and 131 are "0". It is thus seen that the signal on the output line 137 of the OR circuit 136 is the logical OR of the AND circuits 133, 134 and 135 and hence it is equal to the expression (9) above.

L.sub.j represents the latched content of a compare condition for a field. By adding a circuit for setting second compare conditions to the same field to latch L.sub.m+1, L.sub.m+2, . . . L.sub.2m and combining the contents M.sub.ij (i=1, 2, . . . 2m, j=1, 2, . . . n) of the logical operation latches with L.sub.j ', more complex search conditions can be set.

The deletion of the unnecessary fields from the record, that is, the storing of only the necessary field into the buffer memory and the setting of the field data of the record to the registers 146 and 147 to compare the fields with each other are now explained.

FIG. 7 shows a block diagram of the data searching apparatus in accordance with one embodiment of the present invention, and FIG. 8 shows a block diagram of a major portion of FIG. 7.

As shown in FIG. 7, the storage control unit 2 comprises a compare data unit 185, a logical operation circuit 183, compare circuits 140, 144 and 145, interfield compare register unit 180, a latch circuit 182 (all of which are shown in FIG. 6), a control unit 184, a buffer memory 188 and a buffer unit 172. FIG. 8 shows a field information register 187 of the buffer unit 172 shown in FIG. 7, a portion of the control unit 184 and the interfield compare register unit 180.

The storing of the necessary fields into the buffer memory 188 is first explained.

An information on one field from the buffer unit 172 which retains the field information of the record is set into the field information register 187 when it is triggered by a signal FLC=0 on a signal line 178 indicating the completion of the processing of the immediately preceding field.

The field information register 187 has a function of a field length counter and responds to an information on a signal line 201 indicating that the field is necessary to store field data FD or a signal line 170 transferred from the storage unit 1 while incrementing the address of the buffer memory 188 by a count FL on a signal line 196 indicating the field length. In actuality, the field count FLC is decremented in synchronism with a clock and the field data is stored in the buffer memory 188 until the field count FLC reaches zero.

In this manner, the necessary fields are stored in the buffer memory 188 and the search condition for one record is terminated and the buffer memory address is updated based on the search result. If the record meets the search condition, the current address of the buffer memory is backed up in another register by a record coincidence signal as a trigger, and when the record does not meet the search condition, the content of the address back-up register is set into the buffer memory address counter as the buffer memory address in order to cancel the data so far stored in the buffer memory 188.

The storing of the record into the buffer memory 188 is now explained in detail with reference to FIG. 8.

If a compare field flag on a line 201 is "1", it is applied to an AND gate 215. The field length on a line 196 is decremented by the field length counter 221 and a decoder 222 checks to see if the content thereof is zero (FLC=0). If the content of the counter 221 is not zero, the output of the AND gate 215 is "0" and the content of the counter 216 remains at the initial value "0". The counter 216 is initialized by a signal INT from a control circuit 223. A signal on an output line 177 of the counter 216 controls the registers 139 and 141 of the buffer unit 185 and the decoder 115. The necessary compare data and compare conditions are supplied to the compare circuit 140 from the registers 141 and 139, respectively, to compare them with the transferred data, and the results are set in the corresponding latches of the latch circuit 116.

When the content of the counter 221 reaches zero (FLC=0) and the decoder 222 produces a "1" output, the output of the AND gate 215 assumes "1" which causes the counter 216 to be incremented to 1. The "1" output of the decoder 221 is sent to the register 187 through the line 178 so that the next field is set into the register 187.

If the selection field flag on the line 200 is "1" at that time, the output of the AND gate 217 assumes "1" which causes the buffer address counter 224 to be incremented, through the line 190A, and the data transferred from the line 170 is stored at the address of the buffer memory 226 specified by the counter 224. When FLC=0, the next field is stored in the register 187. When the last field is processed and the FLC reaches zero, the last field flag on the line 199 is set to "1" and the output of the decoder 222 assumes "1" so that the AND gate 218 is opened. The "1" output of the AND gate 218 is supplied to the AND gate 219 and the control circuit 223 and also applied to the signal lines 160, 177, 178, 179 and 181 to initialize the units in preparation for the next record processing.

The signal on the output line 137 of the logical operation circuit 183 is applied to the AND gate 219, and when the "1" signal indicating the condition met is supplied, the output signal of the AND gate 219 assumes "1" and the decoder 220 produces a signal SUCC on a line 190B. The signal SUCC is applied to the buffer address counter 224 to set the content of the buffer address counter 224 into the back-up buffer address register 225 through the line 227.

When the output of the AND gate 219 is "0", the decoder 220 produces a signal FAIL, which is applied to the back-up buffer address register 225 through the line 190C so that the content of the register 225 is set into the buffer address counter 224 through the line 228.

Thus, when the coincidence condition is met, the buffer address memory is stored at an immediately following address to the address at which the immediately succeeding coincidence data is stored.

In this manner, the necessary fields of the record are stored in the buffer memory 188 and only the field of the coincidence record is retained.

The interfield compare operation is now explained.

Based on a restrict field on a signal line 198 from the field information register (field length counter) 187, the control unit 184 identifies the fields to be compared with each other by the field decoder 205 to determine a first field signal 208 and a second field signal 218. Based on the first field signal 208, the registers (restrict registers) 146-1-146-2, 147-1-147-2 for storing the current field are determined, and the field data is stored through the AND gate 212. Based on the second field signal 218, the field selector 206 selects a second field number to be compared with the first field. When the second field is transferred from the storage unit 1, the field selector 206 produces a trigger signal T for supplying the data from the registers 146-2 and 147-2 to the corresponding comparators 144 and 145. Thus, the data in the registers 146-1, 146-2, 147-1 and 147-2 are compared with the transferred data.

A specific example is now explained.

It is assumed that each of the records comprises eight fields: F.sub.1 (unit number), F.sub.2 (investigation number), F.sub.3 (budget for present session), F.sub.4 (travel expense in present session), F.sub.5 (outside service fee in present session), F.sub.6 (budget for previous session), F.sub.7 (travel expense in previous session) and F.sub.8 (outside service fee in previous session), and the following search (query) is executed.

"Indicate investigation numbers and their budgets for the present session whose unit number is 305, whose investigation numbers are no lower than 570, whose budgets for the present session are less than those for the previous session and whose outside service fees are less than 500,000 or whose travel expenses are no less than those in the previous session."

This query can be represented by the following logical expression: ##STR1##

Prior to the start of the search, the following initializing step is executed by a microprogram or other means.

The compare condition is set into the compare condition register 139 of the control unit 2, the compare data is set in the compare data buffer 141, the compare conditions are set in the restriction compare condition registers 142 and 143 for comparing the fields, the field attritute, such as field length, compare field flag, selection field flag, last field flag and restriction register designation, is set in the field length buffer 186, and the logical operation latches of the logical operation circuit 183 are set in accordance with the logical expression (10) above. The flags 191-195 are set to the field length buffer 186, as shown in FIG. 7. The flag "1" in the first restriction register designation tag flag 194 and the second restriction register designation tag flag 195 indicates a first part in the restriction, and the flag "1" indicates a second part. Usually, the tag flag can include only one flag "1" and a plurality of flag "1'". In the logical operation circuit 183, the logical operation latches shown in FIG. 6 are set in the following way: ##EQU4##

After the above initializing step, the data transfer from the storage unit 1 is started. In the field length buffer unit 172, the information relating to the field F.sub.1 is set from the field length buffer 186 to the field length counter 87.

The information relating to the field F.sub.1, that is, the field length, the compare field flag 191, the selection field flag 192, the last field flag 193, the first restriction designation tag flag 194 and the second restriction designation tag flag 195 are sent to the control unit 184 through the lines 196, 201, 200, 199, 198 and 197, respectively. When the data transfer from the storage unit 1 is started, the field length counter 187 is decremented in synchronism with the transfer clock CLK.

On the other hand, the data read from the storage unit 1 is transferred to the compare circuits 140, 144 and 145 and the restriction registers 146 and 147 through the line 171 and to the buffer memory 188 through the line 170.

Processing for the field F.sub.1

Based on the content of the query, the selection fields are F.sub.2 (investigation number) and F.sub.3 (budget for the present session), and the compare field is F.sub.1. Accordingly, the control unit 184 responds to the "1" compare field flag 191 on the line 201 to activate the compare data buffer unit 185 through the line 177. The buffer unit 185 supplies the first compare data V.sub.1 and compare condition C.sub.1 to the compare circuit 140.

The other data of the field F.sub.1 are all "0" as is seen by referring to the column of the field length l.sub.1 of the buffer unit 185. Therefore, the units for those data are not activated.

Processing for the field F.sub.2

After the processing for the field F.sub.1, the field length data of the field F.sub.2 is set to the register 187. Since the field F.sub.2 is the compare field and the selection field, both the compare field flag 191 and the selection field flag 192 are "1". The subsequent processing is same as that of the prior art and hence it is not discussed here.

Processing for the field F.sub.3

After the processing for the field F.sub.2, the field length data of the field F.sub.3 is set into the register 187. Since the field F.sub.3 is the selection field and the restriction register designation field, the selection field flag 192 and the first restriction register tag flag 194 are "1". The processing for the selection field is same as that of the prior art and hence it is not explained here. The processing for the restriction designation is explained below.

A portion (relating to the restriction) of the data set in the field length counter 187 is sent to the restriction field decoder 205 of the control unit 184 through the line 198 shown in FIG. 8. Since the field F.sub.3 relates to the restriction and is the first part thereof, it is supplied to the counter 204 through the line 208. The counter 204 has an initial content of zero and is incremented by the input from the line 108. The output from the counter 204 is supplied to the register address decoder 123 through the line 210 to specify the restriction first field registers 146-1, 146-2, 147-1 and 147-2 in which the field F.sub.3 is to be stored. If the decoder 123 decodes the register address 1, the output of the decoder 123 on the line 211 is supplied to the restriction first field register 146-1 to trigger it. As a result, the field content FD of the field F.sub.3 is stored in the restriction first field register 146-1 through the line 171. The storing into the register 146-1 is carried out while decrementing the field length data of the field F.sub.3 in synchronism with the clock CLK.

After the above setting operation, when the second part of the field for restricting the field F.sub.3 appears, the data from the register 146 and the data from the restriction compare condition register 142 are supplied to the compare circuit 144. On the other hand, the output of the decoder 205 is supplied to the restriction compare condition registers 229 and 230 and the outputs of the registers 142 and 143 are stored in the registers 229 and 230 at that timing, and the contents of the registers 229 and 230 are decoded by the compare number decoders 124 and 125 and the decoded results are supplied to the latch circuit 126. The compare result is set in the latch 112-1 of the compare result latch circuit 126.

Processing for the field F.sub.4

After the processing for the field F.sub.3, the field length data of the field F.sub.4 is set in the register 187. Since the field F.sub.4 is the restriction register designation field, the second restriction register tag flag 195 is "1". The subsequent processing is same as that for the field F.sub.3 and hence it is not explained here. The field data of the field F.sub.4 is stored in the restriction register 147. When the second part field of the field F.sub.4 appears, the data in the restriction compare condition register 143 is supplied to the compare circuit 145. The compare result is set in the latch 112-3 of the compare result latch circuit 126.

Processing for the field F.sub.5

After the processing for the field F.sub.4, the field length data of the field F.sub.5 is set in the register 187. Since the field F.sub.5 is the compare field, the compare field flag 191 is "1". This processing is same as that for the field F.sub.1 and hence it is not explained here.

Processing for the field F.sub.6

After the processing for the field F.sub.5, the field length data for the field F.sub.6 is set in the register 187. Since the field F.sub.6 has the "1'" restriction register tag flag 194, it is the second part of the data in the restriction register address 1. Like the fields F.sub.3 and F.sub.4, a portion of the data in the field length counter 187 is supplied to the restriction field decoder 205 of the control unit 184 through the line 198 shown in FIG. 8. Since the field F.sub.6 relates to the restriction (F.sub.3 >F.sub.6) and the second part thereof, the output of the field decoder 205 is supplied to the field selector 206 through the line 207 to determine the first part of this field. The restriction register 146-1 is specified by the output of the selector 206, and the data in the register 146-1 and the compare condition in the restriction compare condition register 142 are supplied to the compare circuit 144 together with the field data FD from the line 171 at the timing of the output of the selector 206. The data in the restriction register 146-1 and the data in the restriction compare condition register 142 are supplied to the compare circuit 144 in synchronism with the transfer of the field F.sub.6. The compare result is set in the latch of the compare result latch circuit 126.

Processing for the field F.sub.7

After the processing for the field F.sub.6, the field length data of the field F.sub.7 is set into the register 187. Since the field F.sub.7 has the "1'" restriction register tag flag 195, it is the second part of the data of the restriction register address 2. The subsequent processing is same as that for the field F.sub.6 and hence it is not explained here.

Processing for the field F.sub.8

After the processing for the field F.sub.7, the field length data of the field F.sub.8 is set into the register 187. Since the field F.sub.3 has the "1" last field flag 193, the subsequent processing is same as that described above. Since the content of the buffer memory address counter of the control unit 184 does not change, the data in the next record are stored at the next address to the content of the address counter.

As described hereinabove, according to the embodiments of the present invention, the compare results of the fields of the record read from the storage unit with the compare data as well as the compare results of the fields with each other are logically operated on by the hardware. Accordingly, even if the records are blocked with small interrecord gaps, the record can be searched for a more complex search condition than that of the prior art. In addition, since only the necessary fields of the record are stored in the buffer memory, the buffer memory can be efficiently utilized and the amount of transfer to the data processing unit can be reduced and the processing time can be reduced.