QAM Encoder

This invention relates to an encoder for modems using QAM and PSK type modulation, and more particularly to an encoder without multipliers.

Modems using QAM and PSK type modulation have become standard in the data communications field. Briefly, such modems transmit and receive multi-valued modulated symbols which are distinguishable by phase and radial amplitude. Such symbols may be represented as points on a complex eye diagram. In the past the symbols have been generated by respectively feeding the X- and Y- coordinates of the points representing the symbols into two transversal digital filters. The outputs of the filters were used to modulate, respectively, a sine and cosine wave of the desired frequency. The two waves were then combined to produce the desired symbol. Such systems may be inaccurate because the transversal digital filters contain a plurality of multipliers which can degrade the transmitted symbols. Furthermore, the system is difficult and costly to implement with digital circuits.

An object of this invention is to provide an encoder which does not use multipliers, thus eliminating a possible source of signal degradation.

Another object is to provide an encoder which can be readily implemented from digital circuits and/or microprocessors at a minimum cost. Other objects and advantages of the invention shall be described in relation to the description of the preferred embodiment.

In the standard encoder referred to above each X- and Y- coordinate value is multiplied and summed a given number of times yielding a discrete number of values N. In the present invention, intermediate values are stored in memory units in a tabular form and then retrieved, based on the input data (i.e. the bits that are to be encoded). These intermediate values are used to derive the same discrete values N. Accordingly the invention comprises a plurality of time-delay units which propagate the input data, memory means for storing the intermediate values and a master summer.

Addressing means are used to retrieve the intermediate values in the memory based on the delayed input bits and a carrier frequency sub address means. The intermediate values from the memory are fed to the summer to produce the desired output signal.

FIG. 1 shows a 4800 B/S 8-phase, 9 point eye diagram (the center point or ninth being the zero output state);

FIG. 2 shows a standard prior art digital QAM/PSK modulation system;

FIG. 3 shows the relative values of the filter coefficients for the system of FIG. 2; and

FIG. 4 shows the components of the preferred embodiment of the present invention.

The present description is by way of example for a communication system of 4800 B/S, 1600 symbols/sec, and 9600 ouput sample rate. A standard eye diagram for such a system is shown in FIG. 1. Typically such an eye diagram defines nine points; eight of them being disposed on a circle and the ninth at the origin. This ninth point is expressed as 1XXX and it is used to introduce a silent period on the output of the transmitter modem. The other eight points may be expressed as complex numbers with an X, (real component) and a Y, (imaginary component).

A standard prior art system for transmitting the points of FIG. 1 is shown in FIG. 2. It comprises an X-axis address means 10 and a Y-axis address means 20. The outputs of each of these address means which occur at 1600 symbols/sec are fed respectively into transversal digital filters 30 and 40 which operate at 9600 b/s. Each one of these filters comprises a plurality of delay means 50 and a plurality multipliers 60. There is a multiplier 60 associated with each delay means. For the system defined above, the transversal digital filter has 24 taps, and the delay is 1/9600 s. There are 24 coefficients associated with the filters and their relative values are shown on FIG. 3. If the coefficients are designated as a,b,c, . . . k,l then the sequence in which they are fed into multipliers 60 is in the form a,b,c, . . . k,l,l,k, . . . c,b,a. The results K and K' of the multiplications are fed into respective master summers 70 and the outputs L and L' of the summers are used to multiply a sine or a cosine carrier frequency signal. Thus, as shown in FIG. 2, the output of the filter associated with X-axis address means 10 modulates an 1800 Hz sine wave resulting in output M while the output of the filter associated with Y-axis address means 20 modulates an 1800 Hz cosine wave resulting in M'. The two outputs M and M' are then added at 80 and the result N is the desired output QAM/PSK signal. The system shown in FIG. 2 uses fifty multipliers, forty-eight delay elements, and three summers.

The encoder provided by this invention is shown in FIG. 4 where the binary coded data is fed into delay means 100 and 110. The most significant bit (indicating the silence bit at the origin of the eye diagram in FIG. 1) is fed into delay means 110 at a rate of 1600 inputs per second, from which it is propagated through delay means 130, 150 and 170. Each one of these means is a one bit delay unit. The remaining bits are fed into delay means 100 as 3 bit binary coded data, from which they are propagated through delay means 120, 140 and 160. Each one of these means is a three bit delay unit.

The encoder also comprises a sub-addressing means formed of a carrier oscillator 180 which includes an adder 185 and a delay unit 190 in a feedback loop wherein the delay unit is set so that the oscillator 180 outputs a 4 bit subaddress at a rate of 9600 subaddresses per second. The output of the oscillator is incremented every 360.degree..times.1800/9600=671/2.degree..

Associated with each 3 bit delay means 100, 120, 140 and 160 and each 1 bit delay means 110, 130, 150 and 170 there are a number of circuits collectively indicated by the numeral 200.

These circuits are designed to provide six discrete values to master summer 250. Thus, the four circuits 200 provide a total of 24 discrete values, which are equal to the number of values provided by the standard decoder of FIG. 2. Circuit 200 associated with delay means 110 will now be described in detail, it being understood that unless otherwise noted, the same description applies to all of them.

Circuit 200 comprises a summer 204, sign extractor 206, sine table 208, memory table 210, sign designator 212, and disabling means 214.

The summer 204 adds the four bits generated by the sub-addressing means 180 to the three bits from respective delay line 100. The four bit sum P(I) is fed to sign extractor 206 which determines the sign of the sine function of the angle which corresponds to said sum. Since the sum has four bits, it represents angles which are multiples of 360.degree./16=221/2.degree.. If this angle is less than 180.degree., its sine is positive; otherwise its sine is negative. Next the three least significant bits of the sum are transmitted to sine look-up table which finds the first quadrant equivalent to the sum. Thus for example if the sum P(I) is 1010 or 225.degree., the sin A is negative, and sin 225.degree.=/sin 45.degree./. Therefore for an input of 1010 to the sign extractor, the sine table generates the bits 10 corresponding to 45.degree.. Since there are only four possible values (221/2.degree., 45.degree., 671/2.degree., 90.degree.) for the sine table output only a 2-bit output Si is necessary. This output is fed into memory table 210. Simultaneously with each 2-bit input Si equivalent to the above angles, the memory also receives a 3-bit input I which initially is one and is incremented for every new angle, i.e. every time the output of oscillator 80 is implemented until binary 6 is reached. The next value for I after 6 is 1. Thus I is in the form of I=1,2,3,4,5,6,1,2,3, . . . Each I value is associated with one of the coefficients K(I) of the transversal digital filter. Thus for table 210 K(1)=a, K(2)=b, etc, and for table 220 K(1)=g, K(2)=h, etc. The K's for tables 230 and 240 are the same as the K's for tables 220 and 210 respectively, with the I count reversed by circuit means 270.

The memory table 210 holds an 8-bit equivalent of the product K(I) x sin (Si). This product is fed to sign designator 212 which tacks on a sign as determined by sign extractor 206. The output Q(I) of 212 is fed through zeroing means 214 to master summer 250.

In particular if the delay means 100 holds the binary number 011 the following six outputs Q(I) will be generated:

When a silence bit is fed into any one of the delay means it by-passes the rest of the look-up circuit and goes directly into the respective AND gate 214 disabling its output.

By using the look-up circuits, this invention effectively eliminates the use of multipliers. It is evident that numerous modifications may be made to this invention without departing from its scope as defined in the appended claims.