US 4,525,679 AGrant
High Gain Amplifying Stage by Output Conductance Cancellation
Issue Date:1985-06-25
•6 Claims
•5 Drawing Sheets
Abstract
A Metal-Oxide Semiconductor (MOS) high gain amplifying stage which overcomes the inherently low transconductance, gm, of MOS transistors is described. This is achieved by using a specially configured load transistor in combination with a driver transistor. The load transistor is provided, by means of positive feedback, with a current generator which is dependent on the output voltage of the stage and has an effective negative output conductance. The positive feedback is achieved by connecting an appropriate attenuation stage between the output and the input of the load transistor. By the cancellation of output conductances between the driver and load transistors, a near infinite voltage gain can be achieved despite resistive loading at the output of the amplifier. The MOS amplifying stage has application in amplifiers, comparators and oscillators. A complementary metal-oxide-semiconductor (CMOS) implementation has been realized but the principle is equally applicable to single channel (NMOS or PMOS) MOS technology.
Metadata
Assignee
- The University of Toronto Innovations Foundation
Inventors
- Stephen L. Wong
- Clement A. T. Salama
Application Information
Application Number:US 4525116
Filing Date:1982-12-23
Priority Date:1982-12-23
Art Unit:252
Classifications
IPC:
H03F 316H03F 138H03G 318
Field of Search:
33070;71;291;293;93;284;277;112
Patent Drawings (5 sheets)
Description
Field of the Invention
The subject invention relates to high gain amplifying stages by output conductance cancellation techniques, and in particular, to amplifier stages utilising MOS (Metal-Oxide-Semiconductor) technology.
Background of the Invention
In prior art MOS technology, the gain is severely limited by the inherently low transconductance, g.sub.m, of the MOS transistor. The transconductance in a MOST (MOS transistor) is proportional to the ratio Z/L (the channel width (Z) to the channel length (L) of the device). Any attempt at increasing the gain by increasing the channel width (Z) of the device, or by cascading gain stages, results in large area consumption and increase in parasitic capacitances. Decreasing the channel length (L) of the MOS transistor to increase the transconductance has its limitations in the fact that it causes a degradation (increase) in output conductance g.sub.o of the device and thus causes a degradation of the voltage gain which is proportional to the ratio g.sub.m /g.sub.o. Therefore, attempts to overcome the low transconductance by modifying the Z/L ratio are not suitable.
A MOS transistor, as shown in FIG. 1a, may be represented by a small signal model which consists of a current generator g.sub.m v.sub.i, (where v.sub.i is the input gate voltage) and an output conductance g.sub.o. (FIG. 1b).
An inverting gain stage comprising a driver transistor 10 and a load transistor 12 is shown in its most general form in FIG. 2. The driver transistor current generator (g.sub.md v.sub.i) is a function of the input signal v.sub.i only, while the current generator [g.sub.m1 (k.sub.a v.sub.i +k.sub.b v.sub.o)] in the load transistor can be affected by both the input and/or the output signals. The small signal gain of the generalized inverter of FIG. 2 is given by ##EQU1## where g.sub.load is the effective conductance of the load transistor and is given by g.sub.load =g.sub.o1 +k.sub.b g.sub.m1 The constants k.sub.a and k.sub.b can have a value of one or zero depending on the type of inverter. Examples of which are shown in FIGS. 3(a), (b) and (c).
The principal disadvantage of the above-mentioned gain stage is that the maximum gain obtainable is low due to the low value of g.sub.m and the high value of g.sub.o, particularly in the case of short channel MOS transistors. The maximum gain is given by ##EQU2## and is achieved using the CMOS stage shown in FIG. 3a.
An object of the present invention is to provide a higher gain amplifying stage than is achievable with the prior art.
A higher gain stage is accordingly provided which utilizes a negative conductance to reduce the total load conductance of the amplifying stage. The new arrangement allows positive feedback to be delivered to the input of the load, which causes K.sub.b 0 and effectively reduces g.sub.load. g.sub.load can be reduced from positive to negative values by decreasing the attenuation of a positive feedback stage A. A negative g.sub.load can then be used to cancel the positive output conductance of the driver g.sub.od, as well as the resistance of the load R.sub.L. This can result in a near infinite voltage gain. In addition, the presence of positive feedback introduces phase lead which may have useful implications in amplifier design.
The high gain amplifier of the subject application is particularly adaptable to implementation in amplifiers, comparators and oscillators. An important advantage of this invention is that the high gain is provided by a single stage only; this allows easier composition of the amplifier and also frees the input and the output stages from the requirements of providing gain. Those stages can then be designed to optimise other input/output specifications such as input offset, dynamic range and current driving capability.
Brief Description of the Drawings
The preferred embodiment and best mode contemplated for implementing the subject invention will now be described in detail with reference to the accompanying drawings of which:
FIGS. 1a and 1b are models for a single MOS transistor according to the prior art;
FIG. 2 is the equivalent circuit of an inverting stage using the small signal model of FIG. 1b;
FIGS. 3a, 3b and 3c are three examples of MOS inverters according to the prior art with the type of inverter being selected by the value of the constants k.sub.a and k.sub.b ;
FIG. 4a demonstrates the basic configuration of the improved high gain amplifying stage in small signal equivalent circuit form according to the present invention;
FIG. 4b demonstrates a CMOS implementation of the amplifying stage of FIG. 4a;
FIG. 5a shows a practical circuit configuration of the amplifying stage according to the present invention realised in a CMOS implementation;
FIG. 5b is a graph demonstrating the adjustable (from positive to negative slopes) load lines of the amplifier shown in FIG. 5a;
FIG. 5c shows the corresponding programmable transfer curves obtained by varying the amount of positive feedback with R.sub.L =1k.OMEGA.;
FIG. 6a is a block diagram representing an operational amplifier or comparator using a gain stage realised in accordance with the present invention;
FIG. 6b shows a practical realization of the operational amplifier of FIG. 6a implemented in CMOS technology.
FIG. 6c shows transfer curves obtained with the operational amplifier of FIG. 6 with varying amounts of positive feedback applied to the high gain stage.
FIG. 7a shows the transfer curves obtained when the gain is adjusted to be larger than that required for total conductance cancellation;
FIG. 7b is a circuit diagram of a voltage control oscillator using the principles according to the present invention with the gain adjusted to be larger than that required for total conductance cancellation.
FIG. 7c is a graph of output pulses resulting from the circuit of FIG. 7b when the voltages V.sub.a and V.sub.b are controlled.
Description of Preferred Embodiment
Referring now to FIG. 4a of the drawings, the principle of the invention is demonstrated. The load transistor 20 of the gain stage has been provided by means of positive feedback, with a v.sub.o dependent current generator 22 having an effective negative transconductance value -g.sub.m1 A, where the attenuation A is less than 1, and is provided by the stage 24 (see FIG. 4b). The input signal v.sub.i is delivered to the free input of the driver transistor 21. The effective output conductance of the load transistor 20 in this case can be shown to be
where g.sub.o1 is the actual output conductance of the load transistor 20, and g.sub.m1 is the actual transconductance of the load transistor 20.
A constant attenuator, is not desirable, since g.sub.load would become a direct function of g.sub.m1, whose value depends on the instantaneous value of -Av.sub.o. Since g.sub.load varies with the level of v.sub.o, exact conductance cancellation with g.sub.od can only be attained at a limited output range about the quiescent point.
Referring now to FIG. 5a, the above principle is demonstrated by a novel gain stage which is realized using standard CMOS technology. An optimal A stage 26 was designed to offer improved output swing and maintain high gain over a wider range of output voltages. The attenuation of M2, M3 and M4 (which form the attenuator 26) is not constant and is approximately given by ##EQU3## where g.sub.o2 and g.sub.m4 are the output conductance and transconductance of transistors M.sub.2 and M.sub.4 respectively. Since g.sub.m4 tracks g.sub.m1, the dependence of g.sub.load on g.sub.m1 can be cancelled. The resulting g.sub.load is nearly independent of the operating point and is given by
Therefore, g.sub.o cancellation can be maintained over a wide range of output voltages.
The final voltage gain is given by ##EQU4## where maximum gain is achieved by selecting ##EQU5##
The Zener diode Z.sub.1 and limiting resistor R.sub.1 are required to prevent hard current cutoff in transistor M.sub.4 and transistor M.sub.2, resulting in the characteristic shown by line 28 in FIG. 5b. This occurs when v.sub.o falls below [V.sub.B -V.sub.T2)+V.sub.T3 ], where V.sub.B is the bias voltage and V.sub.T2 and V.sub.T3 are the threshold voltages of transistors M.sub.2 and M.sub.3 respectively (in other words, without Z.sub.1, if the gate to source voltage of transistor M.sub.3 is less than the threshold voltage V.sub.T3 of M.sub.3, the whole stage is driven into hard cut-off).
The adjustable load lines generated by this scheme are shown in FIG. 5(b), the instantaneous slope gives the value for g.sub.load. FIG. 5(c) shows the corresponding programmable transfer curves obtained by varying the attenuation provided by A with R.sub.L =1K.OMEGA.. As the values of A decreased, the transfer curves exhibited higher voltage gain, as well as increased voltage swing.
The embodiment described may be used as an operational amplifier by simply adding an input stage 30 and an output stage 32 as shown in FIG. 6a. The main advantage of this configuration is that the high gain is provided by a single stage.
As an implementation of FIG. 6a, an experimental operational amplifier, designed using short channel MOST's, was fabricated and shown in FIG. 6b. Excellent DC transfer characteristics was observed and illustrated in FIG. 6c. In FIG. 6c when no positive feedback is used, the amplifier has a voltage gain of less than -250 (curve a). The voltage gain is the slope Vo/Vi of the curve in FIG. 6c. As R.sub.2 is decreased, improvements in both voltage gain and output swing are observed. Maximum gain was observed at R.sub.2 .congruent.23k.OMEGA. (curve b). In the range-3V.ltoreq.v.sub.o .ltoreq.0, the effective voltage gain is better than 10,000. The gain stage therefore improved the gain of the operational amplifier by more than 40 times. Higher gain would still be possible with the optimum choice of (Z/L) aspect ratios for the transistor, since this can increase the infinite gain range of the transfer curve. When R.sub.2 is reduced further, a hysterisis effect is observed (curve c).
When "A" is adjusted to be larger than required for total conductance cancellation, the transfer curves obtained exhibit a hysterisis effect as shown in FIG. 7a. Such a characteristic is ideal for the implementation of oscillators. A CMOS voltage controlled oscillator circuit is shown in FIG. 7b. The gain stage differs slightly from the previous case. The Zener diode Z.sub.1, and resistors R.sub.1, R.sub.2, have been eliminated. The voltage V.sub.B applied to the gate of M.sub.2 can be used to control the separation between the triggering points and control the frequency of oscillation. By adding transistor M.sub.5, the voltage V.sub.A can be used to adjust the offset of the trigger which in turn governs the duty cycle of the output pulse. The resulting output pulses shown in FIG. 7c illustrate the different frequencies and duty cycles which can be obtained by controlling V.sub.A and V.sub.B.
It will be readily apparent that various changes may be made to the description of the embodiments and related drawings without affecting the scope of the invention. For example, the principle of the invention could readily be implemented in single channel Metal-Oxide Semiconductor (NMOS or PMOS) technology. The same can be said for implementations using an inverted CMOS configuration, where the roles between the n-channel and p-channel transistors are reversed. In addition, it will be readily appreciated substrates of the MOS devices, may be connected to sources or to the power supplies without significantly affecting the principle of the invention.
Claims
We claim:
1. A metal-oxide semiconductor (MOS) gain stage fabricated on an integrated circuit and having a load transistor, a driver transistor, a gain stage output taken between the load transistor and the driver transistor, and a variable attenuator connected between the output of the gain stage and an input of the load transistor, said variable attenuator including other MOS transistors, coupled together such that the output conductance of the load transistor is substantially independent of the operating point of the gain stage providing, by positive feedback, a current generator dependent on the output voltage, the current generator having an effective negative output conductance which substantially cancels the total load conductance of the gain stage over a wide range of output voltages, and said output conductance cancellation constituting means effective such that the voltage gain of the stage is substantially increased.
2. A MOS gain stage as claimed in claim 1 wherein the variable attenuator is adjustable to provide exact cancellation of the negative effective output conductance of the load transistor with the driver transistor's output conductance and the load resistor is achievable to provide near infinite voltage gain.
3. An MOS gain stage as claimed in claim 1 wherein said gain stage has coupled thereto an input amplifier and an output amplifier, said input amplifier, gain stage and output stage forming an operational amplifier.
4. A complementary metal oxide semiconductor (CMOS) gain stage fabricated on an integrated circuit and comprising a load MOS transistor, a driver MOS transistor, the drain of the driver transistor being connected to the drain of the load transistor, a gain stage output taken between the driver transistor and the load transistor a variable attenuator having an input and an output, the variable attenuator including MOS transistors, the attenuator input being connected to output of the gain stage and to the drain of the load transistor and the drain of the driver transistor, the output of the attenuator being connected to the input of the load transistor, the arrangement being such that the load transistor is provided, by positive feedback from the variable attenuator, with a current generator dependent on the output voltage, the current generator having an effect of negative output conductance to substantially cancel the total load conductance of the gain stage over a wide range of output voltages, and said output conductance cancellation constituting means effective such that said output conductance cancellation is substantially increased.
5. A CMOS gain stage as claimed in claim 4 wherein the variable attenuator includes switching means in parallel therewith, said switching means conducting current when said output voltage is less than the theshold voltage of said attenuator.
6. A CMOS gain stage as claimed in claim claim 4 or 5, said CMOS gain stage having an input amplifier stage and an output stage thereby forming an operational amplifier.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3286189 | 1966-11-01 | Mitchell et al. |