Method and Circuit Arrangement for Synchronous Detection

This invention relates to method and circuit arrangement for synchronous detection useful in a digital signal transmission system.

When a digital signal obtained by digital modulating, such as pulse code modulation (PCM), an analog information signal, is transmitted through a transmission line, a synchronous signal word for separating each data from another and a parity word for the detection and correction of errors made during transmission are usually respectively added to data words constituting the digital signal prior to transmission. The synchronous signal word is added to one end of each block having a plurality of data words and a parity word so that it indicates the boundary between two consecutive data blocks in a digital signal. The data word will be detected at a receiving end of a transmission line to distinguish or separate each data block from another. Therefore, in the conventional digital data transmission systems, addition of such a data word has been essential. However, each synchronous data word occupies a given period of time and therefore, addition of such a synchronous signal to data words has been an obstacle to the increase of transmission rate.

The present invention has been developed in order to remove the above-described drawback inherent to the conventional digital data transmission system.

It is, therefore, an object of the present invention to provide a new and useful method and circuit arrangement for synchronous detection so that synchronism of transmitted data blocks constituting a digital signal can be detected even when no synchronous words are added to the digital signal, resulting in increase in data transmission amount per unit time.

According to a feature of the present invention, a digital signal comprising a plurality of data blocks each having a plurality of data words and a parity word is transmitted without synchronous words or signal, and the boundary between any two consecutive data blocks is detected, at the receiving end, by parity checking the transmitted data bits in such a manner that various combinations of data bits are parity checked to find a particular combination in which no parity error occurs.

In accordance with the present invention there is provided a method of detecting synchronism of input data blocks constituting a digital signal, where each data block comprises a plurality of data words each having "n" bits, wherein "n" is a positive integer, and a parity word generated in such a manner that each bit in the parity word is given by:

p.sub.m,k =a.sub.m,k .sym.b.sub.m,k .sym. . . .

wherein

a.sub.m,k, b.sub.m,k . . . are bits in a single row of the plurality of data words;

m is a positive integer and 1.ltoreq.m.ltoreq.n, and

.sym. indicates modulo-two summation;

the "n" bits of each word being transmitted in parallel in such a manner that the digital signal comprises "n" rows, the method comprising the steps of: storing the digital signal into a memory in such a manner that the bits a.sub.m,k, b.sub.m,k . . . p.sub.m,k of each row are stored according to the order of the received words; reading out a plurality of sets of consecutive bits, whose number equals the total number of words included selected to form each data block, where the combination of bits selected to form each set is different throughout the plurality of sets of bits; parity checking in connection with the plurality of sets of bits read out; detecting a state of the absence of parity error to ascertain which set of the bits does not result in parity error; and deriving a set of bits from the memory in connection with each row in accordance with the result of the detection of the absence of parity error to output the set of bits as a single row constituting a synchronized data block.

In accordance with the present invention there is also provided a circuit arrangement for detecting synchronism of input data blocks constituting a digital signal, where each data block comprises a plurality of data words each having "n" bits, wherein "n" is a positive integer, and a parity word generated in such a manner that each bit in the parity word is given by:

p.sub.m,k =a.sub.m,k .sym.b.sub.m,k .sym. . . .

wherein

a.sub.m,k, b.sub.m,k . . . are bits in a single row of the plurality of data words;

m is a positive integer and 1.ltoreq.m.ltoreq.n, and

.sym. indicates modulo-two summation;

the "n" bits of each word being transmitted in parallel in such a manner that the digital signal comprises "n" rows, the circuit arrangement comprising: first means for storing the digital signal in such a manner that the bits a.sub.m,k, b.sub.m,k . . . p.sub.m,k of each row are stored according to the order of the received words; second means responsive to a plurality of sets of consecutive of bits read out from the first means, the number of the consecutive bits in each set being equal to the total number of words included in each data block, the combination of bits selected to form each set being different throughout the plurality of sets of bits, the second means being arranged to provide respectively parity checking in connection with the plurality of sets of bits read out; third means for detecting the absence of parity error to ascertain which set of the bits does not result in parity error; and fourth means for deriving a set of bits from the first means in connection with each row in accordance with the result of the detection of the absence of parity error to output the set of bits as a single row constituting a synchronized data block.

The object and features of the present invention will become more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a diagram showing an example of a structure of a conventional block signal;

FIG. 2 is a diagram showing an embodiment of the structure of a block signal according to the present invention system;

FIG. 3 is a block diagram for the description of the principle of the present invention system;

FIGS. 4(A) to 4(C) are time charts showing the internal condition and input output signals of the frequency divider shown in FIG. 3;

FIG. 5 is a block diagram of an embodiment of the present invention system;

FIG. 6 is a diagram showing an example of a block signal comprising interleaved bits;

FIG. 7 is a block diagram of another embodiment of the present invention system; and

FIG. 8 is a circuit diagram of a modification of a parity checker shown in FIG. 3.

The same or corresponding elements and parts are designated at like reference numerals throughout the drawings.

Prior to describing the preferred embodiment of the present invention, the above-mentioned conventional system for data transmission will be described for a better understanding of the present invention.

FIG. 1 is a schematic diagram showing the structure of a conventional digital signal comprising a plurality of blocks each having a plurality of data words. In FIG. 1, a synchronous signal word 1 comprises n-bits s.sub.1 to s.sub.n (n is a positive integer), and this is combined with an n-bit data word 2 (a.sub.1,k to a a.sub.n,k) (k is a positive integer) of first data, a data word 3 (b.sub.1,k to b.sub.n,k) of second data, and a parity word 3 (p.sub.1,k to p.sub.n,k) as a time series to form one block and these data are transmitted one after another. In the past, in order to restore a block signal of such a structure into an original analog information signal at the receiving end, the boundaries between blocks received are detected from the synchronous signal word 1. To this end, it has been hitherto thought that a synchronous signal word 1 is essential in a data block to be transmitted.

In the present invention, however, no synchronous data word is added to the data blocks, and therefore, the amount of information to be sent per unit time can be increased as much as the amount or time length of synchronous words. In the present invention, a received digital signal is stored in a memory and parity checking is effected in connection with various combinations of consecutive bits, and the result of parity checking is effectively used to find a particular combination of bits showing no parity error so that the received data blocks of the digital signal can be automatically synchronized when being derived from the memory.

FIG. 2 shows the structure of a data block to be detected by the synchronous detection system according to the present invention. In this diagram the reference 2 is a data word of first data which comprises n-bits a.sub.1,k to a.sub.n,k, and a data word 3 of second data also comprises bits b.sub.1,k to b.sub.n,k, while a parity word 4 comprises bits p.sub.1,k to p.sub.n,k. Each bit of the parity word 4 can be obtained from the following formula (1) using the first and second data words 2 and 3.

wherein

m is a positive integer and 1.ltoreq.m.ltoreq.n, and

.sym. indicates modulo-two summation.

Namely, each block of the input signal to be synchronous detected with the system according to the present invention comprises data words 2 and 3, and a parity word 4, while no synchronous signal word exists, and the block is transmitted in n-bit parallel.

In the absence of a synchronous signal word, the boundary between input block signals cannot be detected at the receiving end with conventional techniques. However, the number of words forming each block, and the formula (1) for the generation of the parity word 4 are usually known at the receiving end, and therefore, if the boundary between input block signals is correct, the result of modulo-two summation in each row constituting each block should equal "0". The present invention has made it possible to detect the boundary between the input block signals shown in FIG. 2, having no synchronous signal word in view of the above.

FIG. 3 shows a block diagram for the explanation of the principle of the system according to the present invention. In this diagram, to an input terminal 6 are fed first row bits (a.sub.1,k, b.sub.1,k, p.sub.1,k etc) among the input block signal, and they are fed to a shift register 7 having cells 7a to 7e. Then they are shifted from the left to the right in FIG. 3 in response to a clock pulse supplied from an input terminal 30. Thus, the bits are in a stored state, for instance such that the bit a.sub.1,k of the data word 2 of the first data block is at the right most place 7a, and the bit b.sub.1,k+1 of the second data block in the left most cell 7e. The place 7a feeds its contents to a terminal 8a1 of a switching circuit 8 and to a parity checker 9, the cell 7b feeds its contents to terminals 8a2 and 8b1 and to parity checkers 9 and 10, the cell 7c feeds its contents to terminals 8a3, 8b2, 8c1 and to parity checkers 9, 10 and 11, the cell 7d feeds its contents to terminals 8b3 and 8c2 and to parity checkers 10 and 11, and the cell 7e feeds its contents to a terminal 8c3 and to parity checker 11. The parity checkers 9, 10, and 11 performs modulo-two summation of the three inputs fed to each of them, and supplies the result of addition to data input terminals D.sub.1, D.sub.2 and D.sub.3 of a latch 12.

The clock pulse from the input terminal 30 is also fed to a frequency divider 13 in addition to the shift register 7. The frequency divider 13 detects the rising edges of the clock pulse shown in FIG. 4(A), and counts them to change the inner state thereof as shown in FIG. 4(B) so as to generate latch pulse at the timing of FIG. 4(C), and this latch pulse is fed to clock input terminals of latches 12 and 15. The latch 12 holds signals, which are respectively fed to the data input terminals D.sub.1, D.sub.2 and D.sub.3, when the latch pulse from the frequency divider 13 is fed thereto, until a subsequent latch pulse comes from the frequency divider 13, so that it outputs signals X.sub.1, Y.sub.1 and Z.sub.1 from output terminals Q.sub.1, Q.sub.2 and Q.sub.3 to input terminals 14a, 14b and 14c of a selection signal generating circuit 14.

In the case that a pulse is output from the frequency divider 13 under the condition in which the first row bit a.sub.1,k of the data word 2 is stored in the cell 7a of the shift register 7 and the bit b.sub.i,k+1 in the cell 7e as shown in FIG. 3, the following relationship is obtained:

In the above X.sub.1 becomes "0" from formula (1), and thereafter, when a latch pulse is generated from the frequency divider 13, the shift register 7 is subjected to 3-bit shifting, so that the signal X.sub.1 equals "0" all the time. The signals Y.sub.1 and Z.sub.1 respectively have a chance that they become "0", but they do not always equal "0". The selection signal generating circuit 14 receives these signals X.sub.1, Y.sub.1 and Z.sub.1 and generates a control signal when detecting the signal X.sub.1, which is always "0", to feed the same to the switching circuit 8. The switching circuit 8 selects so that the terminals 8a1 and 8a4, terminals 8b1 and 8b4, and terminals 8c1 and 8c4 are respectively connected to each other in accordance with the control signal. The selection generating circuit 14 generates a control signal with which the switch 8 selects terminals 8a2, 8b2 and 8c2 when Y.sub.1 is "0" all the time, and terminals 8a3, 8b3 and 8c3 when Z.sub.1 is "0" all the time. To input terminals 15a, 15b and 15c of the latch 15 are respectively fed signals from terminals 8a4, 8b4 and 8c4 so that the signals respectively fed to the terminals 15a, 15b and 15 c are held when the latch pulse is fed thereto from the frequency divider 13, and these signals are respectively output from output terminals 16, 17 and 18. Accordingly, from the output terminal 16 is derived bits a.sub.1,k, a.sub.1,k+, a.sub.1,k+2 . . . of the first row of the first data one after another, from the output terminal 17 bits b.sub.1,k, b.sub.1, k+1 . . . of the first row of the second data, from the output terminal 18 bits p.sub.1,k, p.sub.1,k+1 . . . of the first row of the parity word one after another.

In this way, by changing the cell of the shift register 7 from which stored contents are derived, in accordance with the result of checking in the parity checkers 9, 10 and 11, series of signals added with boundaries are derived from the output terminals 16, 17 and 18.

FIG. 5 shows a block diagram of a first embodiment of the system according to the present invention. In this diagram, the same parts as in FIG. 3 are designated at like references, and description thereof is omitted. In FIG. 5, the first row of the input block signal incoming through the input terminal 6 is shifted in the shift register 7 in the same manner as in FIG. 3, and stored contents of respective places 7a to 7e are modulo-two added to each other, and then signals X.sub.1, Y.sub.1 and Z.sub.1 are respectively fed to input terminals of gate circuits 19, 20, and 21. Simultaneously, the second to "n"th rows of the input block signal shown in FIG. 2 are fed from the input terminal to the shift register (only the "n"th row is shown), modulo-two addition is effected in the parity checkers in the same manner as the first row, so that signals expressed by the following formulas will be derived from latches (12N for the "n"th row) of respective rows.

wherein i is a positive integer and 1<i.ltoreq.n.

These signals X.sub.i (X.sub.2 to X.sub.n) of the respective rows are fed to a gate circuit 19, signals Y.sub.i (Y.sub.2 to Y.sub.n) to a gate circuit 20, and signals Z.sub.i (Z.sub.2 to Z.sub.n) to a gate circuit 21. The gate circuits 19, 20 and 21 are AND gates of negative logic arranged to produce "0" when all the input signals (X.sub.1 to X.sub.n Y.sub.1 to Y.sub.n and Z.sub.1 to Z.sub.n) respectively fed thereto are "0", and supply respective output signals X.sub.0, Y.sub.0 and Z.sub.0 to the selection signal generating circuit 14. When the first row of the input signal as shown in FIG. 5 is stored in the respective places of the shift register 7, while the shift registers for the second to the "n.revreaction.th rows are in the same condition, the output signal X.sub.0 from the gate circuit 19 becomes "0", and the probability that the output signal from the gate circuit 20 becomes "0" is very small, i.e. 1/2 .sup.n, and thus, the selection signal generating circuit 14 detects X.sub.0 which always equals "0" from these signals X.sub.0, Y.sub.0 and Z.sub.0. To shift registers provided for respective rows of the input signal are provided switching circuits and latches (not shown) for each row thereof in the same manner as shown in FIG. 3, and the selection signal generating circuit 14 supplies a control signal corresponding to "0" state of the signal X.sub.0 to the switching circuits of respective rows. With this arrangement, a series of signals added with boundaries between input block signals is derived for each row. Signal derivation is performed in the same manner as in FIG. 3 throughout all the rows, and thus description thereof is omitted.

Next, an example of a modification of the system according to the present invention, in which the input signal is interleaved as shown in FIG. 6 so that restoration is effected even if partial dropout occurs during transmission, is shown in FIG. 7. Here, each bit of the input block signal satisfies p.sub.k =a.sub.k .sym.b.sub.k . . . (5). In FIG. 7, the same parts as in FIG. 3 are designated at like references, and description thereof is omitted. In FIG. 7, the input block signal shown in FIG. 6, from the input terminal 6 is fed to a shift register 22, and then shifted from cell 22k toward a cell 22a in response to a clock pulse from the input terminal 30. The cell 22a of the shift register 22 supplies its stored contents to a terminal 8a1 of the switching circuit 8 and to a parity checker 9, while the cells 22b, 22c, 22e, 22f, 22g, 22i, 22j and 22k respectively supply their contents to terminals 8b1, 8c1, 8a2, 8b2, 8c2, 8a3, 8b3 and 8c3. The parity checker 9 is supplied with the contents of the cells 22e and 22i in addition to the contents of the cell 22a, while the parity checker 10 is supplied with the contents of the cells 22b, 22f and 22j, and the parity checker 11 with the contents of cells 22c, 22g and 22k. Assuming each bit of the input signal is stored in each cell of the shift register 22 as shown in FIG. 7, when the frequency divider 13 produces a latch pulse,

Therefore, the selection signal generating circuit 14 detects the signal X.sub.0, which always equals 0, to generate the control signal with which terminals 8a1 and 8a4, 8b1 and 8b4, and 8c1 and 8c4 of the switching circuit 8 are respectively connected to each other. Therefore bits a.sub.k, b.sub.k-1 and p.sub.k-2 are simultaneously derived from the respective output terminals 16, 17 and 18.

In the case that the input signal shown in FIG. 6 is of n-bit parallel in the same manner as the input block signal shown in FIG. 2, the circuit shown in FIG. 7 may be changed so that the boundaries of the input block signals are detected for each row of the input block signals, increasing detection accuracy, and the invention is not limited to the above-mentioned embodiment.

In the above-described embodiment, although it has been described that a single block comprises three words, i.e. data bits of first and second data, and parity bits, a single block is not limited to such an arrangement, and a single block may comprise more than three words.

In the above-described embodiment, although parity checking is effected in parallel by means of the parity checkers 9, 10 and 11, parity checking may be effected in series by using a circuit shown in FIG. 8. When using the circuit of FIG. 8 in the circuit of FIG. 3, to an input terminal 23 of FIG. 8 are fed bits a.sub.1,k, b.sub.1,k, p.sub.1,k, b.sub.1,k, p.sub.1,k, a.sub.1,k+1 . . . and bits to be checked for parity checking, in a manner of time series, to be supplied to an input terminal of an EXCLUSIVE OR gate 24. To the other input terminal of the EXCLUSIVE OR gate 24 is fed an output signal of a D-flip-flop 25, and exclusive "or" of both inputs is fed to a data input terminal D of the D-flip-flop 25. To a clock input terminal of the D-flip-flop 25 is fed a clock pulse having a frequency which is three times the frequency of the clock pulse from the terminal 30 of FIG. 5, and an output signal is output from an output terminal Q. To a reset terminal R of the D-flip-flop 25 is fed a reset pulse having a frequency which is one-third of the frequency of the clock pulse fed to the clock input terminal thereof. The above-mentioned circuit is arranged such that bits a.sub.1,k, b.sub.1,k, p.sub.1,k are supplied from the input terminal 23 one after another after being reset so that the output signal at the output terminal is 0, and then operation of formula (2) is executed so that the result of operation is fed to the terminal 14a of the selection signal generating circuit 14 from the output terminal 27, and formulas (3) and (4) are executed after being reset so that results of operation are respectively fed to the terminals 14b and 14c of the selection signal generating circuit 14 from the terminal 27. In the above case, the shift register 7 is not limited to one capable of simultaneously reading out from a plurality of cells, and therefore, other type memories, such as a RAM controlled by a CPU, may be used.

From the foregoing description, it will be understood that a digital signal transmitted without any synchronous word can be synchronized at the receiving end so that original analog information can be accurately restored therefrom. Since, it is possible to detect the boundary between consecutive blocks of the digital signal even if no synchronous signal word has been added to the blocks, the transmission rate can be raised compared to the prior art.

The above-described embodiments are just examples of the present invention, and therefore, it will be apparent for those skilled in the art that many modifications and variations may be made without departing from the spirit of the present invention.