Impedance Transformer Circuit

The present invention relates in general to circuits for processing capacitive voltages and in particular to a new and useful impedance transformer circuit for capacitive voltage sources having high output impedance.

It is known that capacitive transducers, particularly capacitor microphones, deliver an undistorted output voltage proportional to a diaphragm displacement only if, with the diaphragm (or equivalent structure) being moved, the electric charge applied to the capacitor transducer remains constant. Consequently, it seems imperative to prevent the amplifier or impedance transformer following the capacitive transducer from taking up any current as far as possible. This requirement can be satisfied only with a series connected amplifier or impedance transformer having a very high input impedance and a negligible input capacitance. Further, to prevent parasitic capacitances which may occur between the connections of active circuit elements, from discharging the capacitor transducer, with current flowing through the parasitic capacitors, general compensating measures are taken which are aimed at decidedly minimizing the differential DC voltage between the connections and the signal voltages appearing relative to the reference potential "zero". For this purpose, amplifiers comprising a field-effect transistor in bootstrap connection are commonly used, following the capacitive transducer. Such an amplifier which is intended to be employed for a standard microphone, is described in the manual for the "Artificial Voice" model 4219, by the company Bruel and Kjaer.

If the amplifier or impedance transformer only comprises a FET in sequential source connection, parasitic currents flowing through the parasitic capacitors of the FET in operation withdraw charges from the capacitive transducer, for example a capacitor microphone, with the result that at high sonic pressures, distortions appear in the output voltage. This may be remedied by operating the FET in bootstrap connection which is almost perfectly suited for removing distortion from the output voltage, however, has the substantial disadvantage of introducing a very strong noise into the signal.

The present invention is directed to a circuit of the above-mentioned kind which comprises two sequentially connected amplifier stages. The circuit of the invention, however, is not affected by any perceivable noise voltage at its output.

An object of the present invention is thus to provide an impedance transformer circuit for capacitive voltage sources having a high output impedance and particularly useful for capacitor microphones, which comprises two sequentially connected amplifier stages having an overall gain of less than 1 with an output of the first amplifier stage which itself exhibits high input impedance and high gain, as applied to an inverting input of the second amplifier stage which itself exhibits a high gain, the output of the second amplifier stage being fed back to its own non-inverting input through at least one feedback loop which contains the first amplifier stage acting as a resistor that is controlled by the capacitive transducer, wherein, with AC current, a load resistance of the first amplifier stage is located between the inverting input and the non-inverting input of the second amplifier stage and a reference potential of zero for the input and output AC voltage signals is not provided by any of the inverting or non-inverting inputs of the two amplifier stages.

The advantages of the invention are that the input impedance is very high and of low capacity, so that parasitic currents at the amplifier input are compensated for, and so that the signal-to-noise ratio at the amplifier output is substantially improved as compared to prior art circuits. The noise level at the output is suppressed by the fact that, although either of the amplifiers of itself exhibits a gain substantially larger than one, the overall amplification does not exceed the unity value due to the inventive negative feedback arrangement.

Another feature of the inventive design is that an FET in common-source connection is provided at the input and electrically conductively coupled to an oprational amplifier representing the second amplifier stage.

This common-source connection in itself already results in a large input impedance and a high gain which is far in excess of unity and proportional to the load resistance. Only, in practice, there are limits to the value of this resistance, since with an increasing resistance, the voltage drop thereacross might become excessive and prevent reaching of the predetermined operating voltage at the transistor. To obtain the maximum gain in such a transistor amplifier, it is provided to substitute for the load resistor a current source with a high dynamic internal resistance, thus a constant-current source.

The combination of an FET with an operational amplifier is advantageous in that the amplifier includes both an inverting and a non-inverting input, exhibits a large gain, and is commercially available at low cost. The operational amplifier might, of course, be replaced by an arrangement with discrete circuit elements, however, this would require at least two transistors and a plurality of passive elements.

A further object of the invention is to provide such a circuit which includes a field-effect transistor that is electrically conductively coupled to an operational amplifier employed as a second amplifier stage, with the field-effect transistor inserted in a common source connection.

Another object of the invention is to provide such a circuit wherein a current source is provided having a high dynamic internal resistance which acts as a load resistor for the field-effect transistor, which current source comprises a transistor connected as a constant current source.

A further object of the invention is to provide such a circuit wherein the second amplifier stage comprises a discrete unity formed of at least two transistors.

Another object of the invention is to provide an impedance transformer circuit which is simple in design, rugged in construction and economical to manufacture.

The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which preferred embodiments of the invention are illustrated.

In the drawings:

FIG. 1 is a basic schematic diagram of the invention;

FIG. 2 is a similar, corresponding AC diagram;

FIG. 3 shows a first embodiment of the inventive circuitry; and

FIG. 4 shows another embodiment thereof.

As evident from FIG. 1, the inventive circuit comprises two amplifiers V.sub.1 and V.sub.2, each having a gain substantially exceeding unity. The output of the capacitive transducer at 100 is applied, on the one hand, to ground having the reference potential "0", and, on the other hand, through a capacitor C.sub.1, to the input 5 of first amplifier stage V.sub.1. The output 4 of stage V.sub.1 is connected to input 2 which is an inverting input, of second amplifier stage V.sub.2. The output 1 of second stage V.sub.2 is returned to the non-inverting input 3 of this stage and to the non-inverting input 6 of first amplifier stage V.sub.1. This constitutes two negative feedback loops, of which one is connected through amplifier V.sub.1.

An AC connection of the inventive circuit is shown in FIG. 2. The first amplifier stage V.sub.1 having a gain v.sub.1 is designed as a common-source connected FET T.sub.1 and its D output is applied to the inverting input 2 of a second amplifier stage V.sub.2 having a gain v.sub.2. The load resistance R of first amplifier stage V.sub.1 is connected between inverting input 2 and non-inverting input 3 of second amplifier stage V.sub.2, and the output 1 of this stage is fed back to the non-inverting input 3 thereof. The AC voltages developing in this circuitry are designated as follows:

U.sub.E : AC voltage at the first stage input;

U.sub.GS : AC voltage between the gate and source electrodes of the FET;

U.sub.D : AC voltage between the drain electrode and ground;

U.sub.A : AC voltage at the output;

U.sub.1 : AC voltage at the second stage input; and

.DELTA.U.sub.R : noise voltage as referred to the inverting input of the second stage, including a-1 noise voltage sources outside the FET.

The gain of the first amplifier stage is given by the equation: ##EQU1## In addition, the following ratios apply: ##EQU2## It immediately follows from (1) and (2) that: ##EQU3## Introducing of terms (5) and (3) results in: ##EQU4## While using the equation (6) and taking into account equation (2), relation (4) can be rearranged to: ##EQU5## For large gains v.sub.1 and v.sub.2, for example v.sub.1 =10.sup.2 and v.sub.2 =10.sup.3, the obtained equations (6) and (7) show that the AC voltages U.sub.A, U.sub.D and U.sub.E are almost equal to each other a numerical example assuming g.sub.m =10.sup.3 (A/V); g.sub.DS =10.sup.-6 mho; R=10.sup.5 ohm; and v.sub.2 =10.sup.3 results in: ##EQU6##

In practice, the AC voltage between the gate and the source electrodes is smaller by five powers of 10 than the input voltage, and the AC voltage between the gate and the drain electrodes (U.sub.GD) is smaller by three powers of 10 than the input voltage. Parasitic currents flowing through the existing parasitic capacitors of the FET are thus compensated for to the largest extent.

If all noises originating in the second amplifier stage and the load resistor of the first amplifier stage, and perhaps in other sources located outside the first amplifier stage, are combined to an equivalent noise voltage source with the voltage .DELTA.U.sub.R and located upstream of the inverting input of the second amplifier stage, the effect of the suppression of the noise voltage may be expressed mathematically as follows:

With the introduction of the noise voltage .DELTA.U.sub.R, equation (2) becomes:

From equations (1) and (3) it follows that: ##EQU7## And is may be derived from equations (8) and (9) that: ##EQU8##

Equation (10) now shows that the AC voltage at the output is smaller than, but almost equal to, the AC voltage at the input, so that the arrangement has an amplification of close to one. However, any noise voltage appearing at the output is reduced by the factor (1/v.sub.1) relative to the AC voltage signal. Numerically, this means that the noise voltage is reduced to its 99th part.

The arrangement described in principle in the foregoing is shown as a diagram in FIG. 3. The first amplifier stage comprises a FET T.sub.1 having its operating voltage +U.sub.B applied to the load resistor R.sub.8 through a resistor R.sub.5. To adjust the operating point of FET T.sub.1, a high-resistance voltage divider formed by resistors R.sub.2 and R.sub.3 and feed resistor R.sub.4 is provided. The second amplifier stage comprises an operational amplifier V.sub.2 to which the operating voltages +U.sub.B and -U.sub.B are applied through terminals 7 and 8. The D output of the first amplifier stage is applied to an inverting input 2 of the second amplifier stage. The operating point for the non-inverting input 3 of operational amplifier V.sub.2 is adjusted through a second voltage divider formed by resistors R.sub.6 and R.sub.7. The feedback of output 1 to the non-inverting input 3 is effected both through a capacitor C.sub.2 to junction K.sub.1, and directly to junction K.sub.2. The AC voltage potentials of junctions K.sub.1 and K.sub.2 are therefore equal to each other and no division by resistors R.sub.6 and R.sub.7 of the AC voltage fed back takes place. The combination of a capacitor C.sub.3 and a resistor R.sub.9 suppresses a possible tendency of the operational amplifier to oscillate at high frequencies in the megaherz range due to the feedback of output 1 to inverting input 2. The electric charge returns to the capacitor microphone capsule 100 through a resistor R.sub.1 of very high resistance, of a magnitude of some gigaohms. The output voltage of the entire arrangement is available at a capacitor C.sub.4.

FIG. 4 shows a circuit arrangement similar to that of FIG. 3, only a constant-current source in the form of a transistor T.sub.2 is provided instead of load resistor R.sub.8.

While specific embodiments of the invention have been shown and described in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise without departing from such principles.