Track and Hold Circuit

The present invention relates to a track and hold circuit and, more particularly, to a track and hold circuit which provides an input signal independent track-to-hold offset and which can be adapted to minimize the effects of feedthrough and droop.

Track and hold circuits, also referred to as sample and hold circuits, provide samples of an analog or digital input signal and maintain the value of each sample for a predetermined time interval. Typical applications for such circuits are in analog-to-digital and digital-to-analog converters.

In general, the track and hold circuit comprises an electronic switch and a signal storing device. During each tracking interval, the switch is closed in response to a track control signal and the input signal is coupled to the signal storing device. During each holding interval, the switch is opened in response to a hold control signal, thereby isolating the signal storing device.

A problem with track and hold circuits is that each transition from track to hold deposits or removes an electronic charge from the stored signal. As a result, a track-to-hold pedestal or offset is produced which generally varies from sample to sample. In many telecommunications applications, the resulting sampling error is unacceptable.

Other problems in track and hold circuits are feedthrough and "droop" which produce variations in the signal stored during the holding interval. Feedthrough is input signal dependent and is related to the time rate of change of the input signal during the hold interval. Droop, on the other hand, is input signal independent and may be related to anomalies in the track and hold circuit components.

A variety of prior art techniques have been utilized to alleviate the problems of track-to-hold offsets, feedthrough and droop. Combining these techniques, however, is expensive to implement and/or reduces the operating speed of the track and hold circuit. Consequently, a low cost track and hold circuit that provides precise samples and is operable at high speeds would be desirable.

In accordance with the present invention, an improved track and hold circuit comprising an electronic switch and a signal storing device is provided. The track and hold functions are respectively provided by operating the switch in response to the track and hold control signals. To eliminate the problems of an input signal dependent track-to-hold offset, selected track and hold control signals are utilized. Specifically, the track and hold control signals respectively vary with the input signal during successive tracking and holding intervals and have a difference therebetween which is substantially constant. As a result, the track-to-hold offset is input-signal independent and substantially constant. Advantageously, this technique does not affect the operating speed of the track and hold circuit and can be readily adapted to minimize stored signal variations during the holding interval caused by feedthrough and/or droop.

FIG. 1 is a first embodiment of the present invention;

FIG. 2 is a second embodiment of the present invention; and

FIG. 3 is a third embodiment of the present invention.

An illustrative track and hold circuit in accordance with the present invention is shown in FIG. 1. Diode bridge 100 comprises four substantially identical and similarly poled diodes 101. Each diode 101 provides a voltage drop of V.sub.D when forward biased. To provide the track and hold functions, diode bridge 100 operates as an electronic switch in response to control signals supplied to bridge control nodes 112 and 113. During a tracking interval, track control signals are supplied which cause the varying input signal (V.sub.in) at bridge input node 110 to be coupled to bridge output node 111. In a holding interval, hold control signals are supplied which isolate input node 110 from output node 111 and the value of V.sub.in at the track-to-hold transition is maintained in capacitor 114.

Current sources 103 and 105, respectively biased by reference potentials +V and -V, generate the track control signals. Sources 103 and 105 are activated by the logical "1" level of bilevel logic signal CLK and a current I.sub.0 flows from nodes 112 to 113. This current flow establishes track control signals at nodes 112 and 113 of V.sub.in +V.sub.D and V.sub.in -V.sub.D, respectively. Hence, due to the symmetry of bridge 100, V.sub.in is coupled to output node 111.

The logical "0" level of CLK turns off current sources 103 and 105. While isolation of node 110 during the holding interval can be provided by supplying nodes 112 and 113 with fixed hold control signals V.sub.L and V.sub.H which back bias diodes 101, such control signals produce a varying track-to-hold offset. The varying offset is due to the fact that at each track-to-hold transition, node 112 must traverse a control signal difference of V.sub.L -(V.sub.in +V.sub.D) and node 113 must traverse a control signal difference of V.sub.H -(V.sub.in -V.sub.D). Since V.sub.in can have a different value at each track-to-hold transition, the time required for diodes 101 to change from the conducting to the non-conducting state varies with the value of V.sub.in. The variation in "turn-off" time permits a varying charge to be coupled between bridge 100 and capacitor 114 at each track-to-hold transition. As a result, a varying, input-signal-dependent track-to-hold offset is produced in capacitor 114 which degrades the precision of the samples provided and is generally unpredictable.

To alleviate the varying, input-signal-dependent track-to-hold offset, current sources 103 and 105, resistors 106 and 109, and diodes 107 and 108 are utilized. During each holding interval, current sources 103 and 105 are turned off by the logical "0" level of CLK and current sources 102 and 104 are activated by the logical "1" level of bilevel logic signal CLK. CLK and CLK are complementary signals and, therefore, current sources 102 and 104 are off during each tracking interval.

The activation of current sources 102 and 104 produces a current I.sub.0 which flows from control node 113 through resistor 106 and diode 107 to node 110 and thence through diode 108 and resistor 109 to node 112. Diodes 107 and 108 are poled oppositely to diodes 101 to prevent current flow through resistors 106 and 109 during each tracking interval. Resistors 106 and diode 107 are selected to provide a voltage drop of V.sub.R and resistor 109 and diode 108 are similarly selected to provide a substantially identical voltage drop. V.sub.R is equal to the maximum peak-to-peak swing of V.sub.in. The resulting hold control signals at nodes 112 and 113 are V.sub.in -V.sub.R and V.sub.in +V.sub.R, respectively. Consequently, at each track-to-hold transition, control nodes 112 and 113 traverse a signal difference of V.sub.D +V.sub.R which is clearly independent of V.sub.in. The track-to-hold offset, therefore, is independent of the input signal and substantially constant in magnitude and polarity.

In the circuitry of FIG. 1, the hold control signals at nodes 112 and 113 vary with V.sub.in over the holding interval and output node 111 is substantially constant. As a result, any difference in the reverse bias capacitance of the two diodes connected to node 111 will cause electronic charge coupling between bridge 100 and capacitor 114. This charge coupling will cause changes in the signal stored during the holding interval. This effect is known as feedthrough and varies with the rate of change of V.sub.in over the holding interval.

To minimize the above-described feedthrough effects, the track and hold circuit can be modified as shown in FIG. 2. FIG. 2 is identical to FIG. 1 except that resistor 106 and diode 107 are connected between output node 111 and control node 113 and resistor 109 and diode 108 are connected between output node 111 and control node 112. Now, at each track-to-hold transition, the hold control signals are V.sub.in *-V.sub.R and V.sub.in *+V.sub.R, where V.sub.in * is the value of V.sub.in stored in capacitor 114 in each holding interval. Therefore, the hold control signals are functions of V.sub.in but are maintained at a constant level during the holding interval.

The embodiments of FIGS. 1 and 2 provide a substantially constant track-to-hold offset. Additionally, the embodiment of FIG. 2 reduces the effects of feedthrough. In FIG. 2, however, variations in the signal stored during each holding interval may occur if there is any mismatch in current sources 102 and 104. For example, if the current I.sub.0 out of source 104 is greater than the current I.sub.o into source 102, electronic charge will be coupled to capacitor 114. Similarly, electronic charge will be removed from capacitor 114 if source 102 sinks more current than that provided by source 104. The resulting variations in the signal stored in capacitor 114 are independent of the input signal and are commonly referred to as "droop".

The embodiment of FIG. 3 can be used to minimize the effects of droop discussed in reference to FIG. 2 as well as the effects of feedthrough discussed in reference to FIG. 1. In FIG. 3, a second diode bridge 300, amplifiers 324 and 325, and transistors 323 and 326 are added to the circuitry of FIG. 1. Alternatively, these components can be added to the embodiment of FIG. 2.

Bridge 300 comprises four similarly poled and substantially identical diodes 315. Input node 310 of bridge 300 is connected to input node 110 of bridge 100. Output node 323 of bridge 300 is connected to capacitor 316 through output lead 350 of the track-to-hold circuit. The operation of bridge 100 is identical to that described hereinabove and bridge 300 operates synchronously with bridge 100. In a tracking interval, current sources 318 and 320, respectively, biased by potentials +V and -V, are turned on by the logical "1" level of CLK. Consequently, as with bridge 100, track control signals are established in bridge 300 which vary with V.sub.in. In a holding interval, current sources 318 and 320 are turned off and current sources 317 and 319, respectively biased by reference potentials -V and +V, are turned on. The control of these current sources is identical to that described in the embodiments of FIGS. 1 and 2. The activation of current sources 317 and 319 forward biases PNP transistor 326 and NPN transistor 323. Amplifier 324 and transistor 326 shift the value of V.sub.in * by +V.sub.R. Amplifier 325 and transistor 323 shift the value of V.sub.in * by -V.sub.R. Consequently, during each holding interval, the hold control signal on control node 321 is V.sub.in *-V.sub.R and the hold control signal on control node 322 is V.sub.in *+V.sub.R. Accordingly, as in the embodiment of FIG. 2, feedthrough is minimized. In addition, output node 323 is isolated from current sources 102, 104, 317 and 319 in the holding interval. Therefore, any mismatch in these current sources does not affect the value stored in capacitor 316 during each holding interval. This is also the case for the addition of second diode bridge 300, amplifiers 324 and 325 and transistors 323 and 326 to the embodiment of FIG. 2.

It is to be understood that the above-described embodiments are merely illustrative of numerous other arrangements which may constitute applications of the principles of the present invention. Such other arrangements and modifications may readily be devised by those skilled in the art without departing from the spirit and scope of the invention. First, for example, while a diode bridge has been used to provide the track-to-hold switching functions, the use of the described track-to-hold control signals may be advantageously applied to other electronic switching devices. Second, while each diode bridge is controlled by two control nodes, one of the control nodes and the corresponding track and hold control signals can obviously be eliminated if V.sub.in is always positive or always negative. Third, while a capacitor has been used as a signal storing device, other electronic signal storing devices may be used. Finally, the duration of the tracking interval and the duration of the holding interval can be independently adjusted. Therefore, the tracking interval and the holding interval need not be of equal duration.