Pulse Motor Driving Apparatus

This invention relates to a pulse motor driving apparatus and, more particularly, to a pulse motor driving apparatus for driving a plurality of pulse motors.

A prior art pulse motor driving apparatus for driving a plurality of pulse motors is provided with a plurality of timer circuits corresponding to a plurality of pulse motors. These timer circuits are respectively connected to latch circuits. Exciting phase designating signals are inputted, from a control circuit, into the latch circuits. The latch circuits latch the exciting phase designating signals in synchronization with slue-up pulses and high speed normal operation pulses supplied thereto from the timer circuits. The pulse motors are driven in accordance with the respective latch signals latched in the latch circuits.

In the above-mentioned prior art apparatus, however, it is necessary to use, as a control circuit for supplying the phase designating signals to the latch circuits, a circuit which is capable of performing a high speed operation corresponding to 6,000 pulses/sec when driving three pulse motors which are so arranged as to be driven by the total number of latch pulses required to drive the pulse motors (e.g., 2,000 pulses per second per motor). Further, in said prior art pulse motor driving apparatus, since the timer circuits are provided with reference to their respective pulse motors, a large number of timer circuits are necessary, with the result that the circuit construction becomes complicated.

In view of the above, the object of the present invention is to provide a pulse motor driving apparatus whose circuit construction is simplified, without necessitating a high speed control circuit.

According to the present invention, when first and second pulse motors, which are so arranged as to rotate at the same speeds, or at different speeds which are simply integer multiples of the same base speed, are in a state wherein they have just begun to rotate, first and second timing pulse generating circuits supply first and second slue-up pulses to first and second driving circuits, respectively, thereby causing the first and second pulse motors to be driven by their respective slue-up pulses. When the pulse motors have been brought into a state wherein they make their normal rotations, the first timing pulse generating circuit supplies a normal pulse to the first and second driving circuits, thereby driving the first and second pulse motors.

FIG. 1 is a block circuit diagram of the pulse motor driving apparatus according to an embodiment of the present invention;

FIG. 2 is a time chart of the pulse motor drive instruction signals; and

FIG. 3 is a time chart of the output signals of the switching circuit shown in FIG. 1.

In FIG. 1, a control circuit, e.g., CPU 1, is comprised of a central processor unit (e.g., CPU 8049 of Intel Corporation), and a data output section thereof is connected to the input section of an I/O port 2 (e.g., I/O port 8243 of Inter Corporation). The output section is connected to latch circuits 3, 4 and 5, the output terminals of which are connected to the input terminals of driving circuits 6, 7 and 8, respectively. The output terminals of the driving circuits 6, 7 and 8 are connected to motors 9, 10 and 11, respectively. Motors 9 and 10 are pulse motors which are arranged to rotate in response to, for example, 1,500 pulses/sec, while the motor 11 is one which is arranged to rotate in response to, for example, 2,000 pulses/sec. The preset data output section and clock output terminal of CPU 1 are connected to the preset data input section and clock input terminal of a timer circuit 12, respectively. The timer circuit 12 is comprised of a first counter 12.sub.1 and a second counter 12.sub.2. One output terminal O.sub.0 of this timer circuit 12 is connected to input terminals A1, A2 and B1 of a switching circuit 13, while another output terminal O.sub.1 thereof is connected to input terminal B2 of the same switching circuit 13 as well as to a latch input terminal of a latch circuit 5. The switching circuit 13 includes a TC-4019 switching circuit, which is manufactured by Toshiba. Output terminals X1 and X2 of this switching circuit 13 are connected to the latch input terminals of latch circuits 3 and 4, respectively.

In the above-mentioned circuitry, the CPU 1 operates in accordance with the control program stored in a ROM which is built therein. For instance, the CPU 1 conducts a slue-up operation, or an operation of increasing the rotational speed of the pulse motors 9 to 11 from a low speed to a high speed in the initial period of rotation thereof. When a drive command signal shown in FIG. 2, e.g., a signal A for driving the pulse motor 9, is inputted from an external device to the CPU 1, CPU 1 supplies an exciting phase (e.g., an A-phase) designating signal (encoded in, for example, four-bits) to the I/O port 2. The I/O port 2 transfers the A-phase designating signal to the latch circuit 3. Further, at this time, the CPU 1 supplies an item of preset data, i.e., a preset value for starting the slue-up operation, to the timer circuit 12, thereby setting the first counter 12.sub.1 to the preset value. Further, the CPU 1 supplies to the switching circuit 13 a switching signal which activates input terminals B1 and B2. The first counter 12.sub.1 of the timer circuit 12 counts the clock pulses inputted thereto from the CPU 1 and, when this counted value reaches the preset value, the timer circuit 12 supplies a latch pulse to the switching circuit 13 through the output terminal O.sub.0. This latch pulse is inputted into the latch circuit 3 through the output terminal X1 of the switching circuit 13. Since, on the other hand, the latch circuit 3 is supplied with the A-phase designating signal from the I/O port 2, the circuit 3 latches this A-phase designating signal in response to the latch pulse. When the latched A-phase designating signal is inputted into the driving circuit 6, this circuit 6 supplies an exciting current to an A-phase coil of the pulse motor 9, thereby driving the pulse motor 9.

When the first counter 12.sub.1 has its counted value made consistent with the preset value, the CPU 1 operates to preset the first counter 12.sub.1 to the next preset value and, at the same time, to supply a B-phase designating signal to the I/O port 2. The I/O port 2 transfers the B-phase designating signal to the latch circuit 3. When the counted value of the first counter 12.sub.1 reaches the new preset value, the timer circuit 12 again supplies a latch pulse to the switching circuit 13 through the output terminal O.sub.0. The switching circuit 13 supplies the latch pulse inputted thereto to the latch circuit 3 through its output terminal X1. The latch circuit 3 latches the B-phase designating signal and supplies this latched signal to the driving circuit 6. Consequently, a B-phase coil of the pulse motor 9 is energized, whereby this motor 9 is allowed to rotate further.

In the above-mentioned manner, the pulse signal shown in FIG. 3, whose pulse interval gradually decreases or a slue-up pulse signal D, is outputted from the output terminal X1 of the switching circuit 13. After the lapse of the slue-up period T1, a pulse signal of specified pulse width or interval, or a normal operation pulse signal, is supplied to the latch circuit 3 through the switching circuit 13 as a latch pulse. At this time, A-, B-, C- and D-phase designating signals are repeatedly inputted sequentially into the latch circuit 3 through the I/O port 2, and are sequentially latched in the latch circuit 3 in synchronization with the latch pulse. The driving circuit 6 supplies, in sequential order, the exciting current to A-, B-, C- and D-phase coils of the pulse motor 9, whereby the pulse motor 9 is rotated at a high speed normal rotation.

When, during the slue-up period, a drive command signal B (FIG. 2) for driving the pulse motor 10 is supplied to the CPU 1, the CPU 1 presets the second counter 12.sub.2 of the timer circuit 12 to a preset value corresponding to the slue-up pulse of the pulse motor 10, and the I/O port 2 transfers the phase designating signals to latch circuits 3 and 4. When the second counter 12.sub.2 counts the clock pulses and this counted value reaches the preset value, the timer circuit 12 supplies the latch pulse to the input terminal B2 of the switching circuit 13 through the output terminal O.sub.1. The switching circuit 13 transfers the latch pulse to the latch circuit 4 through the terminal X2, thereby making the latch circuit 4 ready for the latching operation. Thus, the latch circuit 4 latches the phase designating signal inputted thereto through the I/O port 2. When the latched signal is supplied to the driving circuit 7, the pulse motor 10 commences the slue-up operation. Thereafter, similar operations are carried out, whereby a slue-up pulse signal E shown in FIG. 3 is outputted from the terminal X2 of the switching circuit 13 during the period T2. Once the slue-up operation of the pulse motor 10 is complete, the CPU 1 makes operative only the counter 12.sub.1 preset to the preset value corresponding to the normal operation and, at the same time, supplies a switching signal to the switching circuit 13 in such a way as to activate the terminals A1, A2 of the switching circuit 13. Accordingly, the normal operation pulse, or latch pulse, which is outputted from the counter 12.sub.1 of the timer circuit 12, is inputted to the latch circuits 3, 4 through the terminals (A1, A2 and X1, X2). Thus, the latch circuits 3, 4 are controlled by the same latch pulse and latch the phase designating signals inputted thereto. Upon supply of the latched signal to the driving circuits 6, 7, pulse motors 9 and 10 are driven to rotate with the same timing. When, thereafter, the phase designating signals are input to latch circuits 3 and 4 through the I/O port 2, while being repeatedly renewed, and the normal operation latch pulse is sequentially input to latch circuits 3 and 4, pulse motors 9 and 10 make their normal rotation at the same rate of speed.

When, during the period in which pulse motors 9 and 10 are in normal rotation, the drive command signal C for pulse motor 11 is supplied to the CPU 1, the CPU 1 presets the second counter 12.sub.2 of the timer circuit 12 to the preset value corresponding to the slue-up pulse, and the I/O port 2 transfers the phase designating signals to latch circuit 5, as well as to latch circuits 3 and 4. When the counted value of the counter 12.sub.2 reaches the preset value, a latch pulse is inputted into the latch circuit 5 through the output terminal O.sub.1 of the timer circuit 12. Thus, the latch circuit latches the phase designating signal inputted thereto through the I/O port 2 and supplies the latched signal to the driving circuit 8. The driving circuit 8 causes the pulse motor 11 to start its slue-up operation. The slue-up operation of the pulse motor 11 is carried out by supply of the slue-up pulse to the latch circuit 5, as a latch pulse, as in the case of pulse motors 9 and 10. Upon completion of the slue-up operation, a normal operation pulse is supplied to the latch circuit 5, whereby the pulse motor 11 commences normal operation.

As stated above, where a plurality of pulse motors are driven, these motors are driven during the slue-up period, in synchronization with their corresponding slue-up pulses from a plurality of timing pulse generating sources. When the pulse motors come into a state of normal operation, one of the plurality of timing pulse generating sources is commonly used for the normal driving of the plurality of pulse motors, which are driven to rotate in synchronization with the timing pulse of this timing pulse generating source, the remaining timing pulse generating sources being used for the slue-up operations of the remaining pulse motors. Moreover, since this type of pulse motor driving apparatus does not require use of the same number of timing pulse generating sources as pulse motors, its circuit construction is simplified.

Further, the control circuit controlling the timing pulse generating sources can have its control capacity reduced to an extent corresponding to the reduction of the number of timing pulse generating sources to be controlled and, thus, does not require a high speed control function.