Image Data Conversion Method and Character Code/Character Pattern Conversion Apparatus

1. Field of the Invention

This invention relates to an image data conversion method which is capable of primarily compressing at a high speed the image bit trains and to a character code/character pattern conversion apparatus which converts character codes to character patterns utilizing said image data conversion method.

2. Description of the Prior Art

In image processing apparatus, for example, facsimile equipment, the number of picture elements of a line of the draft paper of size A4 (corresponding to one scanning line of a CRT, not a line of a sentence) is determined as 1728 bits or 2432 bits for the size A3. In the case of facsimile equipment, the amount of data to be transmitted is reduced since a photo-electric image conversion output is not transmitted directly but in general a band compression is carried out. Also, in the case of transmitting code output from computer to the facsimile equipment, band compression is required in the same way in place of the character pattern itself. If an access is made to a character generator (CG) with the code signal transmitted from the computer and the character pattern signal such as 5.times.7 or 16.times.16 dots/character is output and is subjected to the band compression for transmission to the facsimile equipment and characters are all fixed to a small constant size since the dot interval is small and constant as explained above. However, in some cases it is actually desirable to recognize that the title needs to be written in large size characters to be read easily and that the comments are written unattractively by small size characters. Therefore, it is desired to carry out character expansion and reduction processing for the output of CG.

In the case of ordinary facsimile equipment, the bit information for the image data of the pictures is converted to an intermediate code, for example, into a run length code in order to compress the bit information to be transmitted. This run length code indicates the same code bit a plurality of times and includes information indicating its length. For example, the bit train "001111000" is converted in such a way that 0 has a 2-bit length, 1 has a 4-bit length and 0 has a 3-bit length.

In the existing conversion system for converting image data into the runlength code, the image bit information is converted in to serial bits by a parallel to serial convertor and the number of bits appearing during the period between a first changing point (changing from 0 to 1 or from 1 to 0) and the next changing point is measured by means of a counter. This method results in a disadvantage in that the conversion processing requires a longer time because the serial bits must be checked or counted bit by bit and when the time required for the parallel to serial converter to output one bit is considered as t, the time n xt is necessary for converting the bit information of the image bit of n-bit into the bit length information.

Therefore, in order to improve such conversion time, it is possible, for example, to employ a system where a code conversion table is prepared and the input image data is converted to the runlength code only with an access to the table. According to this conversion table, a problem arises, where the conversion time can be improved considerably because it is determined only by the retrieval time of conversion table because the table size becomes large where the image data length in units of data to be converted such as the facsimile data is comparatively long.

For this reason, a conversion system is proposed herein which respectively solves the disadvantages of the existing bit serial conversion system by means of the conversion table.

An object of this invention is to execute at a high speed a runlength code conversion with less hardware than conventional converters and facilitate character expansion and character interval setting as desired for the character data pattern to be transmitted.

In order to attain such an object, an image data conversion method of the present invention holds in the runlength conversion table at least the runlength code in one or plural storage areas which corresponds to the image data signal, calculates by using calculating means which is controlled for calculation by the output of said runlength conversion table and provides a calculation output which is used as a part for the access address of said runlength conversion table, and holding in a register means temporarily the runlength code ouput from said runlength conversion table. The method also includes detection with the detection means which detects the change of white/black codes output from said runlength conversion table and addition with addition means which adds the content of said register means and the output of said runlength conversion table under the control of said detection means when the same type of codes appear continuously and outputs the result to said register means. The method further includes converting the image data signal to the runlength code signal by a process of reading once or plural times the runlength code from said runlength conversion table for the given image data signal and the process of adding the pertinent runlength codes when the same type of runlength codes appear continuously.

Moreover, in order to attain such object, the character code/character pattern conversion apparatus of the present invention includes means for generating a character a pattern signal

corresponding to the character code from said character code signal input, means for converting said character pattern signal into the runlength code in units of line, means for multiplying a character expansion coefficient with the runlength code output from said converting means, and character interval insertion means which adds a character interval width to the enlarged runlength code output from said multiplication means, and outputs the input character code after converting it into an enlarged character pattern.

FIG. 1 is a runlength code conversion circuit of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the circuit-operation of FIG. 1.

FIG. 3 is an input-output relation diagram of the conversion table of an embodiment of FIG. 1.

FIG. 4 shows in detail the circuit of FIG. 1.

FIG. 5, including 5(a) and 5(b), explains character enlarging procedures.

FIG. 6 is a circuit block diagram of a character code/character pattern conversion apparatus of an embodiment of the present invention.

FIG. 7, including 7(a)-7(d), to FIG. 9 are block diagrams indicating detailed portions of FIG. 6 and tables explain the block diagram.

FIG. 10 is a flow chart indicating the enlarging operation procedures.

FIG. 11 is a block diagram of the facsimile communication equipment using the circuit of the embodiment of FIG. 6.

The preferred embodiment of the present invention will be explained, with reference to the drawing. In FIG. 1, 11 is a conversion clock signal line; 12 is a bit train update signal line; 13 is a input bit signal line to be converted; 14 is a conversion cycle signal line; 15 is a conversion end flag signal line; 16 is a partial bit length signal line; 17 is a code output signal line indicating 1 and 0 of bit train; 18 is a code output change detecting signal line; 19 is an added value signal line; 110 is a conversion result output line; 111 is a conversion table or read only memory (ROM); 112 is the adder; 113 is an counter; 114 is a D type flip-flop; 115 is an exclusive OR gate; and 116 is a register.

In FIG. 2 and FIG. 3, the portions with the same numbering, as in FIG. 1, indicate the signal waveform and logical condition on the corresponding signal lines of FIG. 1.

The following bit train is considered for conversion:

A triangle .DELTA. indicates the location of a partitioning of the bit train into a partial train (split bit train). In this example, the input data is split every 8-bits for conversion.

The clock on the conversion clock signal line 11 is input into the counter 113, generating the conversion cycle signal on the conversion cycle signal (counter value) line 14. The input data on the input bit signal line 13, along with the conversion cycle signal data, is applied to the conversion table 111 inputs and a conversion output is read from the conversion table 111. The signal on the line 15 is the conversion end flag signal, the signal on the line 16 is the partial bit length signal indicating one same code length for the divided input data, the signal on the line 17 is the code output signal indicating "1" or "0" (black or white in the image data) of the same code. The signal on the bit train update signal line 12 is used to control updating the bit train on the input bit signal line 13 with the next split bit train to be converted next by detecting the conversion end flag signal. The signal on the code output change detecting signal line 18 is used for detecting a change of signal type on the code output signal line 17 and is an output of the code output change detecting means which comprises the type D flip-flop 114, which receives the data input from the code output signal line 17 and the clock input from the conversion clock signal line 11, and the exclusive OR gate 115.

Namely, when the code output before one conversion clock and the code output in the next conversion clock match, an output becomes "0" as shown in t.sub.5 of FIG. 3.

When the code change detecting signal is "0", the content of the partial bit length output signal before one conversion clock stored in the register 116 is input as the adder value signal to the adder 112 and it is added to the partial bit length output signal in the next conversion clock. Thereby the partial bit length output can be obtained.

Namely, addition control by the signal on the code output change detecting signal line 18 is carried out for adding the partial bit length output signal 16 of the conversion output and executing the operation for obtaining a larger value in case no code change occurs between the split bit trains (namely, the same white or black continues).

Each circuit of FIG. 1 changes its status at the rising portion of the clock signal on the conversion clock signal line 11. The signal on the bit train update signal line 12 is generated so that it can update the bit train at its rising portion. In actual practice, since the memory address of the conversion table or ROM 111 is updated by the signal on the bit train update signal line 12 and an output of the memory is considered as the input bit signal to be converted, a memory access time is required until said input bit signal to be converted is stabilized from the rising of the memory output. Because of the address input of conversion table (ROM) 111, the conversion end flag signal (line 15), partial bit length signal (line 16) and the code output signal (line 17), which indicates 1 or 0 of bit train are output require a considerable time to stabilize from the rise of clock signal on this conversion table 111 because this conversion table 111 provides a delay time since it is a memory. As a result, the code output change detection signal (line 18) and the added value signal (line 19) changes into a meaningless fashion during this period and it is considered as invalid during this period (Refer to the hatched area of FIG. 2). The operation of the circuit now will be explained with reference to FIG. 1 and FIG. 2. The converstion table output (lines 15, 16, 17) of the time t.sub.1 for the inputs (input bit signal, conversion cycle signal) becomes black 1 (the code output signal line 17 indicates black by 1, while the partial bit length signal line 16 indicates one bit length by 1) and then the length code is input to the adder 112. The signal on the added value signal line 19 is not input to the adder 112 if the code output signal line 17 is changed with respect to the code output before one conversion clock. Therefore, the information of black 1 is stored into the register 116 at the rising portion of the conversion clock (line 11) at the beginning of the timing t.sub.2 and then output on the conversion result output line 110. In addition, when the conversion clock rises at the beginning of t.sub.2, the conversion end flag (line 15) indicates continuation of conversion by 0. As a result, the counter 113 counts up and outputs the conversion cycle signal (line 14) indicating that the conversion cycle is updated.

In the same way, the cycle continues up to t.sub.4, the conversion end flag (line 15) indicates the end of conversion by 1. Therefore, the counter 113 is initialized (ALLO) and the bit update pulse for the bit train update signal is transmitted. The added value (line 19) at the time t.sub.5 and the code output signal 110 (white) at the time of t.sub.5 match. The white 2 which is the result at the time of t.sub.4 is input to the adder 112 and is added to the table output at time t.sub.5. The result is output to the conversion result output line 110 at the time t.sub.6. In the detailed view of FIG. 4, those elements which are the same in FIG. 1 and FIG. 4 are given the same numbering. The numbering 112-1 to 112-3 in FIG. 4 corresponds to the adder 112 in FIG. 1 and the numbering 116-1 to 116-3 in FIG. 4 corresponds to the register 116 in FIG. 1, and the numbering 19-1 to 19-3 in FIG. 4 corresponds to the added value signal line 19 in FIG. 1.

According to the image data conversion method explained in FIG. 1 to FIG. 4, the clock cycle which is the same as that in the existing system is required for the conversion of pattern where 1 and 0 of the bit information appears alternately, but a large effect can be obtained with the present invention, where conversion can be realized at a high speed with the very least number of clocks (about a half of the existing method in the case of this example) as compared with the existing method, in a case 1 or 0 appears continuously for several numbers in the input information.

In this system, the input bit train is converted by the conversion table after it is divided and as a result a large conversion table is no longer required. This is a notable advantage of this method.

A character code/character pattern conversion apparatus will now explained. When enlarging characters, the number of picture elements of a line of a facsimile picture is fixed to 1728 bits (size A4) or 2432 bits (size A3) and characters and character intervals must be given in this bit length without any vacant area. Therefore, when a unit bit of one character is considered as A, an enlargement coefficient of character as N, a number of characters of a line as M and a character interval as B, each parameter must be determined so that the respective following equation is satisfied.

Size A4: 1728=(A.times.N+B).times.M, A.times.N.gtoreq.B

Size A3: 2432=(A.times.N+B).times.M, A.times.N.gtoreq.B

(Where, A, N, B, M are integers)

Here, a line starts with a character and the last character is followed by the character interval B. Values of parameters when the unit bit of one character is determined as 16 are shown in Table 1.

As shown in Table 1, a problem arises here that the number of characters to a line, the size of character and the character interval are fixed in relation to the divisor of the number of picture elements of a line, and the desired size of character and desired character interval cannot be accomplished because an uneven enlarged fit occurs. This invention has solved this problem by the method explained later and makes it possible to set in units of line any desired size of character and any desired character interval.

As shown in FIG. 5(a), when the unit bit of one character A=16, the character interval B=11, the character enlarging coefficient N=1, the relations 1728=(A.times.N+B).times.M, A.times.N.gtoreq.B (A, N, B, M are integers) can be obtained. But, as shown in FIG. 5(b), when enlarged as A=16, N=2, B=10, the remainder S=6 can be obtained. This remainder S satisfies or completes the number necessary for bits of a line and makes it possible to set any desired character size and any character interval with a satisfactory condition when the remainder is placed between the line starting edge and the first character.

FIG. 6 shows the circuit block for said control which is connected to an MPU (microprocessor unit). 10 is a circuit or code memory for storing code information. In this embodiment, this circuit comprises a RAM (random access memory) and allows the desired character code to be written from the MPU. 28 is a code memory control counter and changes the mode of write and read of said memory 10 and controls the number of characters. For example, when the number of characters M=41 is obtained by the MPU's operation in accordance with the respective equation, said MPU loads the number of characters 41 into the counter 28 and moreover writes the character code required, 41 as a maximum, into the memory 10. When the start signal St is input from the MPU under this condition, the counter 28 executes the processing, for example, sequentially reads said 41 codes from the memory 10. 30, 32 are registers, into which the character enlarging coefficient N and character interval B are respectively loaded by the MPU.

122 is the code converter including the CG and ROM (read only memory), which converts the input character code signal to the image (character pattern) and further converts such image signal to the run-length code.

A detailed explanation will be given below, with reference to FIG. 7. 34, 36 are the CG and ROM mentioned above and 38, 40 are counters for outputting a part of the address signals necessary for making access. When the character code bits A.sub.0 to A.sub.5 being input from the code memory 10 are code "100000" indicating the character "A", said code is input to CG 34 as a part of the address signal and the 3-bit output of the counter 38 is input to the CG 34 as a remainder of said address signal. The former address signal indicates the characters and the latter address signal indicates the line including said character image and outputs the pattern signals (image data) D.sub.0, D.sub.1, . . . , D.sub.6 of the pertinent line. The image data D.sub.0 to D.sub.6 are 0011100 for the first line (A.sub.6, A.sub.7, A.sub.8 =0) as shown in FIG. 7(b) in the case of character A, 0100010 for the second line (A.sub.6 =1, A.sub.7, A.sub.8 =0) and . . . for the third line (A.sub.6 =A.sub.8 =0, A.sub.7 =1) etc. After an output of one line is obtained, the clock S.sub.1 is input to the counter 38 and thereby said counter makes an increment of +1 to the counter value and outputs the image data corresponding to the next line. In this example, each 3-bits in the former half and the latter half of the character codes A.sub.0 to A.sub.5 designates the row and column of the character pattern groups arranged in the form of a matrix. Herein, the character pattern is indicated by 7.times.7 dots and a number of characters as little as 8.times.8=64 are used. But actually in practice the character pattern is expressed by 16.times.16 dots as explained above and a considerable number of characters are actually used.

The image data D.sub.0 to D.sub.6 sent from CG becomes the address signal of ROM 36 in combination with the 4-bit output of the counter 40 and the ROM 36, which is to be accessed by said signal, sequentially outputs the runlength codes O.sub.0 to O.sub.5. For example, in case the image data D.sub.0 to D.sub.6 is 0011100, white 2, black 3, white 2, white 0 are sequentially output. The last white 0 indicates the character interval and this is attached to the output of all CG's. The counter 40 is reset at the timing of the output of said white 0 and gets ready for runlength code conversion of the next image data. S.sub.2 is the clock for making an increment of +1 to the counter 40.

This will be further explained with reference to FIG. 7(c). As indicated in the figure, O.sub.0, O.sub.1, O.sub.2, O.sub.3 of image data indicate the number of whites and blacks, respectively the numbers as 2.sup.0, 2.sup.1, 2.sup.2, 2.sup.3. O.sub.4 indicates white or black and it indicates black when it is 1 or white when it is 0. O.sub.5 is used for resetting the counter 40 and reading the next character code. When it is 1, this image data resets the counter 40 and reads the next character code. As in the case of above shown in FIG. 7(d), when A.sub.0 to A.sub.6 is S0011100, the address signals A.sub.0 to A.sub.10 of the ROM 36 become as follows in the initial condition where the count value of counter 40 is 0. A.sub.0 to A.sub.6 is 0011100, A.sub.7 to A.sub.10 is 0000 and the ROM output is 010000 as shown in FIG. 7(d) at O.sub.0 -O.sub.5. (Data is written as indicated above.) It is apparent from FIG. 7(c) that this indicates white 2. When it is output, the counter makes an increment of +1 and the output A.sub.7 to A.sub.10 becomes 1000. The output A.sub.0 to A.sub.6 does not change. When accessed by such addresses A.sub.0 to A.sub.10, the ROM 36 outputs O.sub.0 to O.sub.5 =110010 and as shown in the FIG. 7(c) indicates black 3. The similar operations are also carried out successively. Finally, O.sub.5 becomes 1 and the counter 40 is cleared to 0000 and then next character code is read.

In FIG. 6, 144 is the multiplier comprisinsg a ROM. This multiplier outputs the runlength.times.N (data is being written in such a manner) with the address of the runlength (RL) code of the output of coder converter 112 and the output N (character enlarging coefficient) of the register 30. In the above example, since runlength is 01000, 11001, 01000, when it is doubled (N=2), 00100, 01101, 00100 is obtained and these runlength codes are sequentially output. Such runlength can be multiplied by N easily. The character interval B is set as white 0, namely as 00000. Thereby, it is 0 when it is multiplied by N, making easy the operation for character enlargement. FIG. 8 shows, as an example, the outputs O.sub.0 to O.sub.7 of the multiplier 144 when N=2, white 3. In FIG. 6, 166 is the character interval insertion circuit and includes an adder ADD and multiplexer MPX. This circuit has the structure shown in FIG. 9. 42, 44 are said multiplexer, while 46 and 48 are total adders. In a case of a runlength code other than the white 0 runlength code 00000 which indicates the character interval, the signal S.sub.3 is 0 and when the multiplexers 42, 44 select the signal S.sub.2 which is always 0 and outputs 0 when it receives such runlength code, ignoring the content of character interval register 32. The signal S.sub.2 becomes 1 with the character interval white 0 runlength code and at this time the multiplexers 42, 44 select the register 32 and output the content of said register, namely the character interval B to the total adders 46, 48. Therefore, the adders 46, 48 add the output of multiplier 144 (white 0 in this case) and the output B of the multiplexer and then outputs the results S.sub.0 to S.sub.7. Thus, the interval B is inserted between characters.

In FIG. 6, 18, 20 and 22 function as a runlength code adder. The MPX 18 selects the initial value S sent from the MPU and this is set to the register 22. Thereafter, MPX 18 selects the character interval insertion circuit 16 and causes the adder 20 to add the white or black runlength codes. For example, if the initial values S indicates the white interval, when the first output of the circuit 16 after taking S is white x1, the adder 20 is caused to execute S+x1. In case a character appears successively, the runlength code becomes black x2 and the addition of white runlengths terminates. But in case many white codes continue such as the white in the latter part of the preceding character like the character interval, white of character interval and white at the former part of the next character, and all white runlengths are added. In case any change appears, for example, a black code appears next, addition is suspended and the result obtained is loaded into the buffer 24.

The runlength addition by this adder 20 and register 22 is similar to the runlength addition in FIG. 1 explained above.

The buffer 24 is a first-in, first-out type register and it is intended to absorb the runlength calculation time which changes depending on the image pattern. 26 is a circuit which converts the runlength code to the one-dimensional coding code. In this embodiment, this circuit comprises a ROM and previously stores the data and number of bits of primarily compressed code corresponding to the runlength code, and then outputs the corresponding primarily compressed code. Examples of the code conversion carried out by the conversion circuit 26 are shown in Table 2 and Table 3.

As the runlength code sent from the buffer 24, the white and black runlength appear alternately and these are converted to the codes indicated in Table 2 and Table 3 by the circuit 26. The runlength of 0 to 63 is coded only by the terminating code. For runlenth 64 and higher, the make-up codes expressing the runlength which indicates that it is equal to such run or shorter is used at first and thereafter the remaining runlengths indicated by the terminating code are placed. An output of the convertor circuit 26 is transmitted to the remoted facsimile receiver via the modem and transmission line.

The operations of this apparatus already explained in previous sections are summarized as indicated in FIG. 10. In FIG. 10, A is 16, N is 2 and B is 10. In this example, the MPU calculates at first the equation 1728=(16.times.2+10).times.M+S, 16N.gtoreq.B, and outputs M=41, S=6. These parameters B, N, S and M are set to the registers 32, 30, 22 and counter 28. successively, the processings indicated in the figure, such as entry of character code to RAM 10 are carried out.

It is apparent that the embodiment shown in FIG. 6 to FIG. 10 utilizes the embodiment shown in FIG. 1 to FIG. 4. Namely, the ROM 36 shown in FIG. 7 corresponds to the conversion table or ROM 111 shown in FIG. 1, while the counter 40 shown in FIG. 7 corresponds to the counter 113 shown in FIG. 1, the adder 20 shown in FIG. 6 corresponds to the adder 112 shown in FIG. 1 and the register 22 shown in FIG. 6 corresponds to the register 116 shown in FIG. 1, respectively.

The embodiments shown in FIG. 6 to FIG. 10 realize effectively and simultaneously the runlength conversion operation, character enlargement and character interval inserting operation by adding the multiplier 14, character interval inserting circuit 16 and multiplexer 18 between the conversion table 111 and adder 112 shown in FIG. 1.

FIG. 11 shows the block diagram of facsimile communication equipment where the character code/character pattern conversion apparatus using the embodiment explained in FIG. 6 to FIG. 10 is included.

In FIG. 11, 60 is the facsimile communication equipment; 61 is the micro-processor unit; 62 is a host interface controller; 63 is a RAM; 64 is a ROM; 65 is a timer; 66 is the character code/character pattern compression converter; 67 is a high-level data link controller; 68 is the low speed modem; 69 is a high speed modem; 70 is a line interface and; 71 is a G2 option circuit.

In FIG. 11, the character code/character pattern compression converter 66 corresponds to the circuit shown in FIG. 6.

As explained above, the present invention realizes high speed conversion of an image pattern to runlength data and also realizes desired character enlargement and character interval insertion simultaneously with conversion to the runlength data. Particularly, the present invention provides such an excellent effect of alleviating the load on a computer when transmitting character image data to the facsimile terminal from the computer.

While the present invention has been described with respect to a specific embodiment thereof, it is to be understood that the present invention is not limited thereto in any way but covers any and all changes and modifications which are possible within the scope of the appended claims.