Single Input Oscillator Circuit

This invention relates generally to oscillator circuits and, more particularly, to oscillator circuits having a wide operating frequency range and low current consumption.

Oscillator circuits vary greatly in complexity and current consumption. Typical examples of oscillator circuits are the Schmitt trigger oscillator and a timing circuit commercially available as an MC1555 from Motorola Inc. which utilizes a resistor-capacitor (RC) circuit. Known RC oscillator circuits do not always function properly over wide frequency ranges extending into the MHz range. Process, temperature and voltage variation are a few examples of sources of unstable operation at very high frequencies. Further, some oscillator circuits consume large quantities of current and have a slow self start-up. Other oscillator circuits may not be directly functional for low power supply voltages such as 1.8 volts, and some oscillators provide an output pulse of very narrow width.

It is an object of the present invention to provide an improved single input oscillator circuit.

Another object of the present invention is to provide an improved oscillator circuit having stable high frequency operation during temperature and power supply voltage variations or due to process variation.

Yet another object of the present invention is to provide an improved oscillator circuit which minimizes current consumption and has rapid self start-up.

In carrying out the above and other objects of the present invention, there is provided, in one form a single input oscillator circuit for providing an oscillating output signal in response to the presence of an input waveform at an input terminal. In a preferred form, the input waveform is created, in part, by an RC network coupled to the input terminal. A differential amplifier having a first input coupled to the input waveform and a second input coupled to a reference voltage is provided. A first output of the differential amplifier provides a signal which is proportional to the difference between the reference voltage and the input signal. A second output of the differential amplifier provides a signal which is used for biasing purposes. Reference voltage means provide the reference voltage. A gain stage with variable biasing is coupled to the input terminal and provides the oscillating output signal. Latch means are coupled to both the differential amplifier and the gain stage, for providing a latch signal which is latched at a predetermined level in response to both the differential amplifier and the gain stage. Discharge means couple the input terminal to a reference potential node in response to the output of the latch means, thereby providing oscillating circuit operation.

The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

FIGS. 1(a), 1(b) and 1(c) illustrate in schematic form single input oscillator-circuits known in the art;

FIG. 2 illustrates in schematic form a single input oscillator circuit in accordance with a preferred embodiment of the present invention; and

FIG. 3 illustrates in graphical form waveforms associated with the oscillator circuit of FIG. 2.

Shown in FIG. 1(a) is an oscillator circuit 10 known in the art and comprising a resistor 11 having a first terminal connected to a first power supply voltage V.sub.DD and a second terminal connected to an input terminal. A capacitor 12 has a first electrode coupled to the input terminal and a second electrode coupled to a second power supply voltage V.sub.SS. An N-channel transistor 13 has a first current electrode coupled to the input terminal and a second current electrode coupled to the second power supply voltage V.sub.SS. A non-inverting Schmitt trigger circuit 14 has an input coupled to the input node and an output coupled to a control electrode of transistor 13.

In operation, Schmitt trigger circuit 14 has two threshold voltage levels. When the level of the output voltage is at a logic high level, the threshold level of Schmitt trigger 14 is lower than if the level of the output voltage is a logic low level. This is accomplished by a hysteresis operation of Schmitt trigger 14. Transistor 13 functions as a discharge means of capacitor 12. Resistor 11 charges capacitor 12 until the upper threshold voltage of Schmitt trigger 14 at the input node is exceeded. At that time, the output of Schmitt trigger 14 makes transistor 13 conductive. Capacitor 12 is then discharged until the lower threshold voltage of Schmitt trigger 14 at the input terminal is reached, thereby changing the voltage level of the output of Schmitt trigger 14 to a logic low. Transistor 13 is again made nonconductive allowing capacitor 12 to recharge to the upper threshold voltage level. Oscillator circuit 10 continues to oscillate at a frequency determined by the values of resistor 11 and capacitor 12, by the conductivity of transistor 13 and by the value and variations of the threshold voltages and propagation delays of Schmitt trigger 14 due to its design.

Disadvantages with oscillator circuit 10 include the fact that the Schmitt trigger threshold voltages are not very controllable in non-complex circuits. As a result, the stability of the frequency of operation varies to a large extent because the difference between the Schmitt trigger threshold voltages vary. Further, the time to discharge the input node is primarily dependent upon the output impedance of the discharge device, transistor 13. The consequence of a short discharge time is a very narrow output pulse. Therefore, a distorted duty cycle results which is difficult to utilize without adding pulse stretching circuitry.

Shown in FIG. 1(b) is a time delay discharge oscillator circuit 16 which is also known in the art. A comparator circuit 17 has a noninverting input coupled to an input node 18. An inverting input of comparator 17 is coupled to a reference voltage VTH which sets the threshold voltage of comparator 17. An output of comparator 17 is coupled to a trigger input of a one-shot circuit 19. An output of one-shot circuit 19 provides an output signal and is also coupled to a control electrode of an N-channel transistor 20. A first current electrode of transistor 20 is connected to input node 18 and a second current electrode of transistor 20 is connected to a first supply voltage V.sub.SS. A capacitor 21 has a first electrode connected to first supply voltage V.sub.SS and a second electrode connected to input node 18. A resistor 22 has a first terminal connected to input terminal 18 and a second terminal connected to a second supply voltage V.sub.DD.

In operation, time delay discharge circuit 16 uses a single threshold voltage which is applied to the negative or inverting input of comparator 17. Instead of using a second threshold voltage to effect a change in the level of the output signal, comparator 17 triggers the one-shot circuit 19. The one-shot circuit 19 can provide a wider output pulse signal than the output signal of Schmitt trigger 14. However, time delay discharge oscillator circuit 16 only has one threshold voltage and the pulse width of the pulse from one-shot circuit 19 must always be sufficiently wide to discharge capacitor 21. The one-shot pulse width may vary with supply voltage, temperature and process variations. If the pulse width varies so that capacitor 21 is not totally discharged, the operating frequency becomes unstable. Although the propagation delay dependency upon the impedance of transistor 20 is minimized, a reference voltage source is required to provide reference voltage V.sub.TH.

Shown in FIG. 1(c) is a CMOS circuit 25 similar to an application of a timer which is commercially available in a bipolar process as an MC1555 from Motorola Inc.. A resistor 26 has a first terminal connected to a first supply voltage V.sub.DD. A second terminal of resistor 26 is connected to a first electrode of a capacitor 27, to a first current electrode of an N-channel discharge transistor 28 and to a negative or inverting input of both a comparator 29 and a comparator 30 via an input terminal. Both a second electrode of capacitor 27 and a second current electrode of transistor 28 are connected to a second supply voltage V.sub.SS. A resistor 31 has a first terminal connected to a first terminal of first supply voltage V.sub.DD and a second terminal connected to both a positive or noninverting input of comparator 29 and a first terminal of a resistor 32. A second terminal of resistor 32 is connected to both a positive or noninverting input of comparator 30 and a first terminal of a resistor 33. A second terminal of resistor 33 is connected to second supply voltage V.sub.SS. An output of comparator 29 is connected to a complementary set input, S, of a set-reset type latch circuit 34. An output of comparator 30 is connected to a reset input, R, of latch circuit 34. An output of latch circuit 34 labeled "Q" provides an oscillating output signal and is connected to a control electrode of transistor 28.

In operation, circuit 25 utilizes two trip points by using two reference voltages, each of which is a fixed proportion of supply voltage V.sub.DD. Use of two references voltages stabilizes the voltage difference, .DELTA.V, between the upper and lower trip points because both the current in the RC network and .DELTA.V are proportional to supply voltage V.sub.DD. In operation, when the voltage level at the inverting input of comparator 29 exceeds the reference voltage applied to its noninverting input, a logic zero is applied by the output of comparator 29 to the S input of latch circuit 34. Simultaneously, a logic zero input signal is coupled to the reset input, R, of latch circuit 34 by the output of comparator 30. Therefore, the Q output of latch circuit 34 is set to logic one and retains the desired output voltage level thereby enabling transistor 28. Transistor 28 discharges capacitor 27 such that the voltage to the inverting input of comparator 29 falls below the reference voltage applied to the noninverting input of comparator 29. At that time, the output of comparator 29 returns to a logic one removing the complementary set signal, S, condition while the output of comparator 30 remains at logic zero. As transistor 28 discharges capacitor 27 below the reference voltage on the noninverting input of comparator 30, the output of comparator 30 transitions to logic one, thereby applying a reset signal to latch 34. The output of latch 34 returns to logic zero and renders transistor 28 nonconductive. At this time, resistor 26 begins recharging capacitor 27. It can therefore be shown that such operation repeats continuously without any coincidence of complementary set, S, and reset, R, signals. Typically, an external resistor connected in series with an external capacitor is utilized. A disadvantage with circuit 25 is that discharge transistor 28 must overcome the current supplied to the first capacitor terminal via resistor 26 in order to discharge capacitor 27. Utilizing a dual threshold voltage circuit requires the resistor reference voltage string of resistors 31, 32 and 33. For low current operation, resistors 31, 32 and 33 or other voltage divider circuits require high resistance and hence excessive integrated circuit die area.

Shown in FIG. 2 is a preferred form of a single input oscillator circuit 40 comprising generally a bias generator portion 41, a differential amplifier portion 42, a reference voltage portion 43, a gain stage portion 44, a buffer portion 45, a latch portion 46 and a discharge portion 47. An external RC circuit 48 may be coupled to a single input terminal of circuit 40.

Bias generator portion 41 comprises a P-channel transistor 50 having a first current electrode connected to a terminal for receiving a supply voltage V.sub.DD, a control electrode connected to a terminal for receiving a supply voltage V.sub.SS, and a second current electrode. An N-channel transistor 51 has a first current electrode connected to both the second current electrode of transistor 50 and a control electrode thereof, and a second current electrode connected to a terminal for receiving the supply voltage V.sub.SS.

Differential amplifier portion 42 comprises a P-channel transistor 52 having a first current electrode connected to the terminal for receiving the supply voltage V.sub.DD, a control electrode, and a second current electrode connected to a first current electrode of an N-channel transistor 53 to form a first output. A control electrode of transistor 53 functions as a first input of differential amplifier portion 42 and is connected to a single input terminal. A P-channel transistor 54 has a first current electrode connected to the terminal for receiving supply voltage V.sub.DD, and both a control electrode and a second current electrode connected together to form a second output of differential amplifier portion 42. The second output of differential amplifier portion 42 is connected to both the control electrode of transistor 52 and a first current electrode of an N-channel transistor 55. A second current electrode of N-channel transistor 55 is connected to both a second current electrode of N-channel transistor 53 and a first current electrode of an N-channel transistor 56. A control electrode of transistor 56 is connected to the control electrode and first current electrodes of transistor 51, and a second current electrode of transistor 56 is connected to the terminal for receiving supply voltage V.sub.SS.

Reference voltage portion 43 comprises a P-channel transistor 58 having a first current electrode connected to supply voltage V.sub.DD, and both a control electrode and a second current electrode connected to both a control electrode of transistor 55 and a first current electrode of a P-channel transistor 59. Transistor 59 has both a control electrode and a second current electrode connected together and to a terminal for receiving supply voltage V.sub.SS.

Gain stage portion 44 has a P-channel transistor 61 having a first current electrode connected to the terminal for receiving supply voltage V.sub.DD, a control electrode connected to the second output of the differential amplifier portion 42, and a second current electrode. A P-channel transistor 62 has a first current electrode connected to the terminal for receiving supply voltage V.sub.DD, a control electrode, and a second current electrode connected to both the second current electrode of transistor 61 and a first current electrode of an N-channel transistor 63. A control electrode of transistor 63 is connected to the single input terminal of circuit 40, and a second current electrode of transistor 63 is connected to the terminal for receiving supply voltage V.sub.SS.

Buffer portion 45 comprises a P-channel transistor 65 having a first current electrode connected to the terminal for receiving supply voltage V.sub.DD, a control electrode connected to both a control electrode of an N-channel transistor 66 and the first current electrode of transistor 63. A second current electrode of transistor 65 is connected to a first current electrode of transistor 66, to a control electrode of a P-channel transistor 67 and to a control electrode of an N-channel transistor 68. A second current electrode of transistor 66 is connected to the terminal for receiving supply voltage V.sub.SS. A first current electrode of transistor 67 is connected to the terminal for receiving supply voltage V.sub.DD, and a second current electrode of transistor 67 is connected to the first current electrode of transistor 68 for providing the output of circuit 40. A second current electrode of transistor 68 is connected to the terminal for receiving supply voltage V.sub.SS.

A latch portion 46 comprises a P-channel transistor 69 having a first current electrode connected to the terminal for receiving supply voltage V.sub.DD, a control electrode labeled S connected to the first output of differential amplifier portion 42, and a second current electrode. An N-channel transistor 70 has a first current electrode connected to the second current electrode of transistor 69, a control electrode labeled R connected to the second current electrode of transistor 67, and a second current electrode connected to the terminal for receiving supply voltage V.sub.SS. A P-channel transistor 71 has a first current electrode connected to the terminal for receiving supply voltage V.sub.DD, a control electrode and a second current electrode. An N-channel transistor 72 has a first current electrode connected to the second current electrode of transistor 71 and a second current electrode connected to the terminal for receiving supply voltage V.sub.SS. The control electrode of transistor 71 is connected to a control electrode of transistor 72, to the second current electrode of transistor 69, to a first current electrode of a P-channel transistor 73 and to a first current electrode of an N-channel transistor 74. A second current electrode of transistor 73 is connected to the terminal for receiving supply voltage V.sub.DD, and a second current electrode of transistor 74 is connected to the terminal for receiving supply voltage V.sub.SS. A control electrode of transistor 73 is connected to a control electrode of transistor 74 and both control electrodes are connected to a control electrode of a P-channel transistor 75, to a control electrode of an N-channel transistor 76, to the second current electrode of transistor 71, and to the control electrode of transistor 62. A first current electrode of transistor 75 is connected to the terminal for receiving supply voltage V.sub.DD, and a second current electrode of transistor 75 which provides an output of latch portion 46 labeled "Q", is connected to a first current electrode of transistor 76. A second current electrode of transistor 76 is connected to the terminal for receiving supply voltage V.sub.SS.

Discharge portion 47 comprises an N-channel transistor 80 having a first current electrode connected to the input terminal of circuit 40, a second current electrode connected to the terminal for receiving supply voltage V.sub.SS, and a control electrode connected to the second current electrode of transistor 75 labeled "Q" of latch portion 46. The external RC portion 48 comprises a resistor 81 having a first terminal connected to the terminal for receiving supply voltage V.sub.DD and a second terminal. A capacitor 82 has a first electrode connected to the second terminal of resistor 81 and is adapted to be coupled to the single input terminal of circuit 40. A second electrode of capacitor 82 is connected to the terminal for receiving supply voltage V.sub.SS. While specific N-channel and P-channel MOS devices are shown, it should be clear that oscillator circuit 40 could be implemented by completely reversing the processing techniques (e.g. P-channel to N-channel) or by using other types of transistors.

By referring to the associated signals illustrated in FIG. 3, the operation of the present invention may be readily explained. Assume that upon application of power supply voltages V.sub.DD and V.sub.SS, a brief but rapid start-up time is required to establish bias currents and voltages, after which oscillator circuit 40 becomes operational. The start-up time is substantially the time required to couple full power supply voltage to circuit 40 and is very fast. Further assume, for purposes of illustration, that capacitor 82 is initially totally discharged and that resistor 81 and capacitor 82 are coupled to oscillator circuit 40 at the single input terminal. Therefore, initially both the first output of differential amplifier portion 42 and the output of gain stage 44 at the first current electrode of transistor 63 are at a logic high or one level. Therefore, the output of oscillator circuit 40 at the output of buffer portion 45 is at a logic one level thereby applying a reset condition to the set-reset latch portion 46. This causes the Q output of latch portion 46 to be at a logic zero level thereby disabling capacitor discharge transistor 80. The Q output of latch portion 46 is at a logic one level which disables transistor 62 by making transistor 62 nonconductive. This reduces the bias current in gain stage portion 44 thereby conserving power.

Simultaneously, resistor 81 charges capacitor 82 until the voltage charged across capacitor 82 reaches the threshold voltage of N-channel transistor 63, say V.sub.TL. Once transistor 63 is made conductive, the output of gain stage portion 44 becomes a low logic level. This causes the output signal of circuit 40 and the reset signal input of latch portion 46 to transition to a low logic level as shown in FIG. 3. Resistor 81 continues to charge capacitor 82 until the threshold voltage of differential amplifier stage 42, say V.sub.TH, is reached. Differential amplifier stage 42 functions as a comparator. The threshold voltage is determined by the voltage coupled to the second input of differential amplifier stage 42 by reference voltage portion 43. Bias generator transistors 50 and 51 provide a bias voltage to transistor 56 which functions as a regulated current source for differential amplifier stage 42. Once the voltage of capacitor 82 exceeds the threshold voltage of differential stage 42, the first output of differential stage 42 transitions to a low logic level which sets latch portion 46. A low logic level at the control electrode of transistor 69 couples a high logic level to the control electrodes of transistors 71 and 72 which couples a low logic level to the control electrodes of transistors 75 and 76. Therefore, the Q output of latch portion 46 transitions to a high logic level thereby enabling capacitor discharge transistor 80. To guarantee circuit oscillation, the impedance of transistor 80 when conductive must be considerably lower than the resistance of resistor 81. Simultanouesly, the Q output of latch portion 46 enables transistor 62 of gain stage portion 44 thereby increasing the bias current in the gain stage portion 44 and greatly improving its response time to a fast negative transition on the input of oscillator circuit 40.

After discharge transistor 80 is conductive a predetermined amount of time, capacitor 82 is discharged. When the voltage across capacitor 82 becomes less than the threshold voltage level V.sub.TH of differential amplifier portion 42, the first output of differential amplifier portion 42 transitions to a high logic level thereby removing the set condition of latch portion 46. As the voltage on capacitor 82 falls below the threshold voltage of transistor 63 of gain stage 44, the output of gain stage 44 at the first current electrode of transistor 63 transitions to a high logic level. Therefore, the output signal at the output of buffer portion 45 transitions from a logic low level to a logic high level and a reset condition is thus applied to latch portion 46 thereby causing the Q output to become a logic zero and the Q output to become a logic one thus initiating another oscillator cycle. Simultaneously, transistor 62 is disabled thereby conserving power.

In an analogous manner to the circuit operation previously described, if capacitor 82 is initially charged to supply voltage V.sub.DD rather than being discharged, differential amplifier portion 42 and gain stage portion 44 would immediately initiate a discharge phase previously described. Further, if capacitor 82 is initially charged to a voltage which is somewhere between the threshold voltage levels V.sub.TH and V.sub.TL, the initial state of latch portion 46 would determine whether oscillator circuit 40 would start in a charge or discharge phase.

Although an external resistor-capacitor voltage input is shown, other embodiments of the use of oscillator circuit 40 may include applying a clock input to the single input terminal where the clock input has an amplitude which varies above and below the threshold voltage of gain stage portion 44.

Advantages of oscillator circuit 40 include the feature that a wide range of external R-C networks may be used to provide an oscillating output signal having a wide operating frequency range. Further, oscillator circuit 40 can provide a stable high frequency output signal over a range of process, temperature and voltage variations and utilizes low current consumption. The oscillator also has rapid self start-up. The output waveshape is improved by using a common source gain stage having variable bias with a differential comparator stage utilizing a single reference voltage.

While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.