Detector Mismatch Correction Apparatus

In the Norman L. Stauffer U.S. Pat. No. 4,185,191 issued Jan. 22, 1980, and assigned to the assignee of the present invention, a range determination system is shown which is usable in a through-the-lens camera for positioning the taking lens at a desired correct focus position with respect to a remote object within the field of view. The system utilizes a plurality of small detectors such as charge coupled devices (CCD) or Charge Injection Devices (CID) mounted in an array to receive radiation from the scene being viewed. The detectors are arranged in pairs with each pair being mounted behind a small lenslet so that each pair receives a view of the exit pupil of the taking lens but one of the detectors in each pair receives radiation primarily from a first portion of the taking lens while the other of the detectors in each pair receives radiation primarily from a different portion of the taking lens. The result is to create two similar curves indicative of the radiation distribution pattern from the scene being viewed. At the proper focus position, both of the detectors of each pair receive substantially the same amount of radiation and the two curves coincide, but as the object changes position with respect to the camera, the detectors in each pair receive different amounts of radiation and the two curves move with respect to each other to indicate an out-of-focus situation.

The accuracy of the system depends upon the matching of the detector pairs so that when they receive the same amount of radiation they produce substantially the same output signals. Unfortunately, it is extremely difficult to manufacture detector pairs that are always closely matched and accordingly in the past, attempts have been made to vary the output of one of the detectors in the pair so as to cause it to match the output of the other detector in the pair when both are subjected to the same radiation. For example, in the co-pending application of Norman L. Stauffer, Ser. No. 213,438, filed Dec. 5, 1980 now U.S. Patent No. 4,359,636 issued Nov. 16, 1982, a detector balance apparatus and method is shown in which portions of one or both of the detectors in a pair are shadowed by pins or strips in order to cause the outputs of the two detectors to be the same under the same conditions. While such apparatus as this is satisfactory to balance a detector pair, it is time consuming and expensive to perform this operation on all of the detector pairs particularly when, as often happens, a mismatch in detector pairs is caused by a manufacturing problem which mismatches all of the detectors in a certain batch.

The present invention operates to correct the mismatch which occurs in detector pairs by providing a correction to the detectors in an amount which is determined from the outputs of all the detectors in the array. More specifically, the signals from at least one of the detectors in each pair is modified by an amount which depends upon the average mismatch of all of the detectors so that the modified signals become substantially the same as the signals, which may or may not also be modified, from the other of the detectors in each pair, on the average. After thus matching the outputs, the detectors are used, as before, to sense radiation intensities, or other condition magnitudes for auto focus or for other purposes as desired.

FIG. 1 is a graph showing the outputs of detector pairs in a system where the detector pairs are satisfactorily matched;

FIG. 2 shows a graph of a system in which the outputs of the detector pairs are mismatched;

FIG. 3 shows a schematic representation of a system for correcting the outputs of mismatched detectors in an array; and

FIG. 4 shows a schematic representation of a specific circuit for correcting the output mismatching in a detector array.

FIG. 1 shows a graph depicting the outputs of 24 pairs of detectors as they might be received in series fashion from the output terminal of a shift register, for example, when all detectors are illuminated substantially equally. In FIG. 1 the outputs of a first of the detectors in each pair, the "a" detectors, are shown as dots such as are indicated by reference numeral 10 while the outputs of the other detectors, the "b" detectors, are shown as X's such as are shown by reference numeral 12 in FIG. 1. It is seen in FIG. 1 that the outputs of the detector pairs are fairly close together throughout the entire range of the 24 detectors shown. There are, very slight mismatches which may occur in a single detector pair by overall the outputs of the detector pair are substantially the same. It is seen that the voltage drops from a high point at the detector 1 pair on the left side of FIG. 1 slightly to a low point at detector 24 on the right side of FIG. 1 which is accounted for by virtue of the fact that as the shift register shifts the charges from one position to the next so as to bring them out of the CCD device in series, a small amount of charge is lost with each shift. This does not affect the output of the device significantly and accordingly when the outputs of the detectors are matched as shown in FIG. 1, they can be utilized to sense a condition such as radiation intensity to determine the proper focus position as explained in the above referred to Stauffer U.S. Pat. No. 4,185,191.

FIG. 2 shows 24 pairs of detectors in which the outputs in each pair are mismatched considerably probably because of an error in the manufacturing process even though all detectors are illuminated substantially equally. In FIG. 2 the outputs of the "a" detectors are shown by reference numeral 10' and the outputs of the "b" detectors are shown by reference numeral 12' and it is seen that the outputs of the "b" detectors are higher than the outputs of the "a" detectors. It is also seen that the detector pair 1 at the left side of FIG. 2 is mismatched by a greater amount than the detector pair 24 at the right side of FIG. 2 but that the percentage of mismatch is approximately the same throughout the entire set of detectors. Accordingly, if either the "a" or "b" detectors are multiplied by a predetermined percentage value indicative of the average percentage mismatch or, if both "a" and "b" detectors are multiplied by a different value so as to raise the level of the "a" detector outputs and lower the level of the "b" detector outputs, then the outputs of the detector pairs can be brought closely together so that they will resemble the graph shown in FIG. 1.

One way of accomplishing the modifications of the signals from one or both of the detectors in each of the pairs by a predetermined value is shown in FIG. 3. In FIG. 3 a moveable lens 13 is shown positioned by an auto focus apparatus 14 through a mechanical connection shown as dashed line 15. Radiation from a remote object travels to lens 13 along a path shown by arrow 16 and from lens 13 to a plurality of lensletts 17 and detector pairs 18 shown connected by a line 19 to a CCD device 20. As explained in the above-mentioned U.S. Pat. No. 4,185,191 signal from the detector pairs indicative of radiation distribution patterns may be used to determine the range to the remote object so that with proper auto focus circuitry the lens 13 may be positioned at a desired proper focus position.

The CCD device 20, may include a shift register for producing a chain of output voltages serially on an output line 22 representative of the individual voltages from the "a" and "b" detectors in the detector pairs in a manner such as is shown in the James D. Jospeh et al U.S. Pat. No. 4,250,376 issued Feb. 10, 1981, and assigned to the assignee of the present invention. Line 22 is shown connected to a gain modulator 24 which has an additional input 26 shown connected to the CCD device 20 for purposes of synchronization, as will be explained, and operates to change the gain produced by modulator 24 selectively in accordance with the detector pair signals being produced by the CCD device 20. Gain modulator 24 is shown producing an output on line 28 connected to auto focus apparatus 14. The output on line 28 will be a series of signals representing the individual detector outputs as modified by the modulator 24 and, when properly modulated, those signals would be substantially equal on the average when the detectors received the same radiation. More specifically, if it were determined, for example, that in FIG. 2 the "a" detector outputs 10' should be multiplied by a factor 1.02 to bring them up to substantially match the outputs of the "b" detectors 12' then the synchronized input 26 to the gain modulator 24 would cause the gain modulator 24 to increase the gain to 1.02 when the "a" detector signals were present on line 22 but not when the "b" detector signals were present on line 22. Accordingly, each "a" detector signal would have its gain multiplied by 1.02 whereas each "b" detector signal would not. Thus the output on line 28 would have "a" and "b" signals more closely approximating that shown in FIG. 1 since all of the "a" detector signals would have been increased by a multiple 1.02 to bring them up to the "b" signal level when both detectors in each pair are subjected to the same intensity of radiation. Of course, the outputs of the "b" detectors could be decreased to the "a" signal level, or, as will be shown in FIG. 4, the "a" detector outputs could be decreased some while the "b" detector outputs were decreased even more to again bring them to the same level when the detectors in each pair received the same radiation.

In FIG. 4, a specific circuit for providing the correction described in connection with FIG. 3 is shown. In FIG. 4 the lens 13, auto focus circuit 14, detector pairs 18 and the CCD device 20 are again shown operable to produce an output on a line 22 comprising the series of signals representing the outputs of the "a" and "b" detectors. In FIG. 4 these signals are fed through a resistor 30 labelled R.sub.1 to a junction point 32 connected as the output 28 to the auto focus circuit 14. Junction point 32 is also connected by a line 34 to the wiper of a variable resistor 36 having a resistance portion 37. The resistance portion 37 is shown divided into two sections, that on the left hand side of the wiper 34 is labelled R.sub.2a while that on the right hand side of wiper 34 is labeled R.sub.2b. By moving wiper 34 from the left to the right R.sub.2a can be made greater while R.sub.2b is made smaller. Likewise, moving the wiper 34 from the right to the left will make R.sub.2b larger while making R.sub.2a smaller. The left hand side of the resistance portion 37 of variable resistor 36 is shown connected by a line 38 to the emitter 40 of a PNP transistor 42 labeled QA which operates as a switch. The right hand side of the resistance portion 37 of variable resistor 36 is shown connected by line 44 to the emitter 46 of a PNP transistor 48 labelled QB which also operates as a switch. A collector 50 of transistor 42 and a collector 52 of transistor 48 are connected together at junction point 54 which is shown connected to a source of voltage V.sub.REF. The value of V.sub.REF is chosen to be the same as the signal from the CCD detectors on line 22 when they are not exposed to any radiation at all. This value has been predetermined for a particular detector array and may be transmitted as one of the first signals appearing from the CCD device 20 before the signals from the "a" and "b" detectors start to emerge. The V.sub.REF may then be set by moving a voltage divider wiper (not shown) to the proper position. Of course if the detectors used have a zero output signal in the absence of radiation, the voltage V.sub.REF will be made zero or ground.

The base 56 of transistor 42 and the base 58 of transistor 48 are shown connected to a control device 60 which may be a standard divide-by-two flip-flop with its Q output connected to base 56, its Q output connected to base 58 and its CP input connected to a line 62 from the CCD device 20 for purposes of synchronization. More particularly, CCD device 20 will produce a first signal when any "a" detector signals is present on line 22 causing control device 60 to turn on transistor 42 and a second signal when any "b" detector signals is present on line 22 causing control device 60 to turn on transistor 48. When control device 60 is a flip-flop, the Q and Q outputs would be alternately controlled by signals on line 62 to bring the voltage on the bases 56 and 58 to the required potential to turn transistors 42 and 48 on and off. Since CCD device 20 produces the "a" and "b" signals alternately, normally, a clock could generate the control signals on line 62.

With the wiper of variable resistor 36 set at its midpoint, the value of R.sub.2a and R.sub.2b are the same and both "a" and "b" signal values will be decreased by essentially the same amount, the exact amount of the decrease being dependent upon the resistor divider R.sub.1,R.sub.2a and R.sub.1,R.sub.2b. For the wiper of variable resistor 36 set to any other than its midpoint position, the decrease in the signal of "a" will be different than the decrease in the signal of "b" and thus the relative mismatch such as shown, for example, in FIG. 2 can be corrected.

By observing the outputs of the detector pairs and forming a graph such as shown in FIG. 2 it may be determined by what value the "a" and "b" detector signals should be multiplied in order for them to produce substantially the same output on line 28 when they are subjected to the same radiation. If, for example, it is determined that the "b" detectors are, on the average, 2% higher than the "a" detectors, then the wiper 34 of variable resistor 36 may be moved slightly to the right in FIG. 4 so that the resistance R.sub.2a is slightly more than the resistance R.sub.2b causing the decrease in the "a" signal to be slightly less than the decrease in the "b" signal.

In synchronization with the "a" and "b" signals on line 22, control signals will be presented via line 62 to the control 60 which then will produce a first output on line 56 turning transistor 42 to an "on" condition and transistor 48 to an "off" condition when a signal from an "a" detector is being presented by the CCD device 20 on line 22. When this occurs, current will flow through Resistor R.sub.1, junction point 32, resistor R.sub.2a and transistor 42 to junction point 54. The size of the signal at junction point 32 (which at this time is an "a" signal) will be decreased by a percentage representative of the position of wiper 34 on variable resistor 36. When the CCD device 20 produces the next signal it will be indicative of a "b" detector signal and accordingly the signal on line 62 from the CCD device 20 to control device 60 will cause control device 60 to turn on transistor 48 via line 58 and shut off transistor 42. The current will now flow through resistor R.sub.1 , junction 32, resistor R.sub.2b and transistor 48 to junction point 54. The size of the signal at junction point 32 (which at this time is a "b" signal) will be decreased by a percentage representative of the position of wiper 54 on variable resistor 36. Since R.sub.2b is set to be slightly less than R.sub.2a the decrease of the "b" signal will be more than that of the "a" signal and accordingly at the output 28, when the variable resistor wiper 34 has been properly set, the "a" and "b" signals will be substantially the same. The next signal from the CCD device 20 will be another "a" signal and again the control device 60 will turn off transistor 48 and turn on transistor 42 so that the "a" signal will be decreased at junction point 32 according to the value set by resistance R.sub.2a. This process is repeated for each "a" and "b" signal coming from CCD device 20 and it is seen that each of the "a" signals will be decreased by a certain percentage, and each of the "b" signals decreased by a slightly larger percentage thereby causing the output shown in FIG. 2 to be more like those shown in FIG. 1. Of course, one need not make a plot of the output of each detector as in FIG. 2 in order to calculate where wiper 34 should be placed, and, in fact, no calculation need be made at all. In practice, the detectors will be subjected to the same light intensity so that their outputs ought to be equal. The signals on line 22 from the detectors are presented to the circuit of FIG. 4 and the V.sub.REF value set by observing the coded value presented as an early output from CCD device 20. The when the "a" and "b" signals are being presented on line 22 and the synchronized control signals are being presented on line 62, the operator need only to manually move the wiper 34 until the output signals on line 28 are equal. He will know which way to move wiper 34 by the sign of the signal difference on the line 28. For example, if the "b" signals are larger than the "a" signals, as in the example of FIG. 2, then the wiper 34 should be moved to the right, if the opposite is the case, then the wiper 34 should be moved to the left. A simple indicator attached to lines 28 and 62 would provide the desired direction information.

If the detector outputs were properly matched to begin with, as is shown in FIG. 1, then the voltage divider wiper 34 in FIG. 4 would be set on resistance portion 37 at a position where R.sub.2a was substantially equal to R.sub.2b in which case both the "a" and "b" signals from CCD device 20 would be decreased by the same factor and would emerge on the output 28 substantially equal with regard to respective magnitude.

Of course it will be obvious to one skilled in the art that there are many other ways of multiplying the "a" signals so that they match the "b" signals throughout the entire range of all of the detectors in the array. For example, if the output of CCD device 20 were a series of digital words, each word being representative of the value of an "a" or "b" signal, then a software correction performed by a computer would be entirely possible.

Assume, for example, as is shown in the above referenced U.S. Pat. No. 4,250,376 that the outputs of the "a" and "b" detectors are presented to an Algorithm Processor which operates upon them in accordance with the equation: ##EQU1## then the Algorithm Processor could be arranged to process all of the "a" signals so as to form a partial sum S1 representative of the total of the "a" signals and similarly to process all of the "b" signals to form a second sum S2 representative of the total of the big "b" signals. The Algorithm Processor could then, by the subtraction S1-S2, determine the average error between the "a" and the "b" signals and the desired correction factor and use this correction factor to multiply all of the "a" and/or "b" signals in the above equation to provide the desired correction.

These and many other obvious modifications will occur to those skilled in the art. I therefore do not wish to be limited by the specific disclosures used in connection with the description of the preferred embodiments. I intend only to be limited by the following claims.