Interconnection and Addressing Scheme for LCDs

This invention relates to liquid crystal displays (LCDs) and, more particularly, to interconnection and addressing schemes which reduce the number of external leads needed to operate an LCD.

Only a dozen years after their introduction, liquid crystal displays now comprise a $500 million market, establishing them as the most important multicharacter display technology after CRTs. World-wide LCD production is well over 200 million pieces annually, largely for consumer electronics applications such as digital wristwatches and credit-card calculators which would be impractical with any other type of display. While most LCDs today are used in such battery-powered portable devices, they are capturing new areas of application because of their improving information capacity, unique optical properties, and their low system cost which arises from batch fabrication and a good match to low-voltage integrated circuits.

The overwhelming majority of LCDs use twisted nematic (TN) liquid crystal (LC) materials which are sandwiched between opposing glass substrates. Segmented transparent electrodes are deposited on the substrates. In the absence of an applied field, the TN-LC molecules form a spiral between aligned surfaces. Polarized light follows the spiral and experiences a 90.degree. rotation. However, the application of only a few volts across the electrodes suffices to destroy the spiral in the region of the LC where the opposing electrodes overlap; i.e., the molecules line up like compass needles in a magnetic field so that the polarization of the light transmitted along the molecules is unaffected. The addition of polarizers and a reflector yields a device which can produce visible patterns by selectively modulating ambient white light. Thus, the LCD achieves high contrast over an acceptable field of view even in direct sunlight, with a power dissipation which is lower by several orders of magnitude than comparable displays which generate light themselves.

In a simple watch or instrument LCD, every individual display segment is connected to its own independent driver. No voltage is applied to unselected segments, while selected segments are turned on as hard as the supply voltage (typically 1.5-3 V) will allow. Because an unrestricted choice of drive voltage maximizes display performance, this simple direct-drive scheme is preferred whenever the number of display segments is not too large.

Direct addressing proves to be too expensive, however, for more complex displays. For example, at least two integrated circuits (ICs) would be needed for direct drive of the more than 64 character segments in the eight-digit calculator display. Matrix addressing provides a solution by allowing each drive line to control several segments. Connecting the segments of a calculator display into a matrix with three rows reduces the number of drive lines from 68 to 28, making possible an LCD calculator with only one IC. Today, most calculator displays are organized as matrices with three or four rows. The same matrix addressing technology is increasingly being used for digital displays in telephones, laboratory instruments and boating equipment. The fact that the display "segment" at each matrix intersection can have a complex shape is widely utilized in electronic games, with pictures ranging from Pac-man.TM. to Popeye.TM..

Unfortunately, the substantial economies of the matrix connection are won only with some sacrifice in simplicity and performance. When many elements are interconnected on the same address line, it is not possible to drive one element arbitrarily hard without inadvertently affecting other elements. An attempt to address a single element by energizing a single row and column may result in "sneak" conduction paths through nominally off LC elements, thereby giving rise to crosstalk. However, the sneak paths can be limited by connecting every lead to a low-impedance voltage source, with none left floating.

Typically, rows are pulsed cyclically while the information to be displayed is multiplexed onto the columns by synchronously choosing the polarity of column voltages to add to or subtract from the corresponding row pulses. It follows that, unlike direct addressing, the unselected elements in a matrix see a non-zero voltage with rms value V.sub.off. In order for unselected elements to appear off, the LCD must have an electrooptic threshold higher than V.sub.off.

It turns out also that the rms voltage V.sub.on which is seen by a selected element is not independent of V.sub.off, rather it is proportional to V.sub.off. Thus, raising V.sub.on also increases V.sub.off so a given segment cannot be driven too hard without causing spurious turn-on of other segments connected to the same matrix lines. Successful multiplexed operation, therefore, requires that the LCD be turned on acceptably by voltages not too far above threshold. FIG. 1 shows schematically the kind of electrooptic characteristic needed for multiplexing. The attainable ratio of V.sub.on to V.sub.off decreases as the number of rows in the matrix increases, because the dwell time for driving any given row becomes a smaller fraction of the addressing period. Clearly, a steeper curve is needed for a matrix with more rows.

In addition, a matrix with more rows, hence more picture elements and higher resolution, means higher addressing cost largely because the number of leads that must be driven increases with the number of resolution elements. For M elements interconnected as a matrix at least 2M.sup.1/2 leads are required. Conversely, N leads can address a matrix which contains no more than 1/4N.sup.2 elements. This limit was recently exceeded by an interconnection scheme which permits N leads to control N(N-1) light emitting diodes (LEDs) through an addressing method based on three-state logic. See, K. Gillessen et al, Proceedings of SID, Vol. 22, p. 181 (1981). Both the reverse blocking characteristic and the sharp threshold for forward conduction of the LED are essential to this approach, so its extension to LCDs is not straightforward.

In accordance with my invention, the number of leads N needed to drive an array of M liquid crystal elements is reduced by a unique combination of an interconnection scheme and an addressing scheme. Although each LC element is connected to a column bus and a row bus, these buses are not independent of one another. Thus, the elements are arranged so that the first row and first column each contain (N-1) elements, the second row and second column each contain (N-2) elements, etc., and the last row and last column each contain a single element. That is, the n-th row and n-th column each contain (N-n) elements with one element in common. In addition, the first row of elements is connected to the first row bus, the second row of elements and the last column of elements (actually a single element) are both connected to the second row bus, the third row of elements and the penultimate column of elements are both connected to the third row bus, etc., and the last (N-th) row bus is connected only to the first column of (N-1) elements. Using this electrical interconnection scheme, the physical arrangement of the elements may take on a variety of geometrical patterns, e.g., rectangular, triangular or linear arrays. These arrays are addressed via N external leads connected to the N row buses.

In one embodiment for displaying any possible pattern on the array, the addressing scheme utilizes a pulsed signal having M time slots per frame applied to each row bus. Each time slot is uniquely associated with a distinct element. Only the coincidence of two pulses of opposite polarity applied to an element from different buses is sufficient to turn on an LC element. In particular, each bus contains (N-1) pulses divided into two illustratively time-wise sequential subsets. To address (turn on or off) an element (x,y) in the x-th column and y-th row, a row-select signal on the y-th row is constructed so that its first subset contains (N-y) pulses of one polarity in the time slots corresponding to the (N-y) elements in the y-th row, and its second subset contains (y-1) pulses (one or more of which may have the opposite polarity, but these pulses are related to the selection of other elements). In addition, a column-select signal on the (N+1-x)th row is constructed so that its first subset contains (x-1) pulses of one polarity, and its second subset contains (N-x) pulses of either polarity in the time slots corresponding to the (N-x) elements in the x-th column. The y-th pulse in the second subset of (N-x) pulses is of opposite polarity if the element (x,y) is to be turned on and of the same polarity if it is to be held off. For TN-LC elements all signals are repeated in the next frame with opposite polarity to complete the two-frame period with zero average voltage (i.e., to avoid generating a dc voltage which is known to have damaging electrochemical effects on a LC element).

This arrangement tacitly assumes that the addressing scheme must be capable of displaying any possible pattern on the array. However, considerable improvement in performance can be realized by taking advantage of a priori restrictions on the set of allowable patterns. This approach is employed illustratively in two alternative embodiments of my invention: a pseudo-analog pointer display which is addressed via mutually orthogonal signals applied to on elements and via identical signals applied to the single off element; and a bargraph which is addressed via bipolar pulsed signals in which m columns containing only on elements are addressed in m time slots of each frame, and a (m+1)th time slot has reversed polarity pulses to cancel dc. A column containing both on and off elements is addressed in a (m+2)th time slot, and the pulses of a (m+3)th time slot again cancel dc. These time slots may occur in any sequence.

My invention, together with its various features and advantages, can be readily understood from the following, more detailed description taken in conjunction with the accompanying drawing, in which:

FIG. 1 is a graph of contrast versus the ratio of the on-off voltages of a LC element. The graph demonstrates that increasing the number of rows N in an array reduces the attainable selection ratio, requiring a LC element with a steeper threshold curve;

FIG. 2, Part (a) shows how an array of 10 LC elements are interconnected and addressed via only 5 leads in accordance with an illustrative embodiment of my invention; and Part (b) shows the waveform for turning on LC element F at location (x,y)=(2,2);

FIG. 3 shows how a modified meander interconnection scheme of LC elements is addressed for a pseudo-analog pointer display with fully saturated contrast in accordance with another embodiment of my invention;

FIG. 4 shows an addressing scheme for a bargraph display in accordance with yet another embodiment of my invention;

FIG. 5 is a cut-away, isometric view of an LCD of the type shown in FIG. 2 but has not been drawn to scale in the interest of clarity of illustration; and

FIG. 6 shows that the interconnection scheme of my invention can be laid out to realize a rectangular pattern of elements.

With reference now to FIG. 5, there is shown a LCD which includes a LC material in the form of a thin layer 10 (e.g., about 10 .mu.m thick) sandwiched between opposing glass substrates 12 and 14. An illustrative array of elongated column electrode x1-x4 is deposited on the inside surface of substrate 12, and an array of elongated row electrodes y1-y5 is deposited on the interior surface of substrate 14. The two arrays are orthogonal to one another and comprise transparent material such as indium tin oxide. Thus, a LC element is defined as the portion of this structure at the intersection between a pair of overlapping electrodes. In this example there are M=10 such elements designated A to J.

In the interest of simplicity, the side members, which form a chamber with the substrates to enclose the LC material, as well as the usual polarizers, have been omitted.

In accordance with my invention, the row and column electrodes are not independent of one another. Rather, they are connected to one another, illustratively via cross connections 18, as follows: four column electrodes x1, x2, x3 and x4 are connected, respectively, to row electrodes y5, y4, y3 and y2 via cross connections x1/y5, x2/y4, x3/y3, and x4/y2. Row electrode y1 has no such cross connection. Pulsed voltage signals V1 to V5 are applied to the N=5 row electrodes y1 to y5, respectively, via a low impedance voltage source 20. Of course, a suitable computer may be used to control the waveforms generated by source 20.

The cross connections 18 may be made by several techniques known in the art; for example, by separate wires run to a printed circuit board or by silver epoxy dots located at appropriate locations between the substrates.

As mentioned previously, using this electrical interconnection scheme, the physical arrangement of the elements may take on a variety of geometrical patterns. A triangular array is shown in FIG. 5, a linear array is shown in FIG. 3 (to be described later) and a rectangular array is shown in FIG. 6. Rectangular arrays of elements are used for alphanumeric and graphics display in which any or all of the elements may be freely selected. FIG. 6, Part (a) illustrates how the interconnection scheme of FIG. 2 may be rearranged to form a rectangular array with an aspect ratio approaching 2:1. FIG. 2, Part (b) illustrates the electrode pattern on one substrate to implement the Part (a) interconnection. The staggered arrangement of elements, like bricks in a wall, can be rectified if desired as shown in Part (c).

The manner in which this interconection of LC elements is addressed is best understood with reference to FIG. 2, Part (a) which depicts the waveforms of a sequence of five pulsed signals V1 to V5 applied, respectively, to the row electrodes y1 to y5 which are shown as the inputs to a schematic representation of the interconnection of the row and column electrodes. Only a single frame of each signal V1 to V5 is shown.

The 10 LC elements designated A to J are located at the intersections of each row and column. In a corresponding fashion, each frame of the signals is divided into 10 time slots which have also been designated A to J. Each time slot, therefore, has a one-to-one correspondence with one, and only one, LC element. Further, each time slot may contain either a positive pulse (+V) or negative pulse (-V). In this example, there are four pulses per frame on each external lead. If the element responds to peak voltages, then .vertline.V.vertline. is less than the LC threshold (V.sub.th), but 2.vertline.V.vertline. is greater than the threshold. But, if the element is rms-responding, as with TN-LCs, then .vertline.V.vertline..ltoreq.(V.sub.th /2)[N(N-1)/(N-2)].sup.1/2.

These pulses are divided into two illustratively time-wise sequential subsets: a first subset of positive pulses and a second subset (cross-hatched) of either positive or negative pulses depending on which LC elements in a particular column are to be turned off or on. Thus, the first subset of signal V1 applied to row Y1 contains four positive pulses, one in each of time slots A, E, H, and J corresponding to LC elements A, E, H, and J in that row. But, the second subset contains no pulses. Similarly, the first subset of signal V2 has positive pulses in time slots B, F, and I corresponding to the same elements in row Y2, and its second subset has a single pulse in time slot J which is either negative or positive depending on whether element J is to be turned on or off, respectively. Continuing in the same fashion, the first subset of signal V3 contains positive pulses in time slots C and G, and its second subset contains pulses in time slots H and I each of which is either negative or positive depending upon whether elements H and I are to be turned on or off, respectively. Signal V4 has a first subset which includes a single positive pulse in time slot D and a second subset which includes three pulses in time slots E, F, and G each of which, as before, is either negative or positive depending on whether elements E, F, and G are to be on or off, respectively. Finally, signal V5 contains no pulses in its first subset but contains four pulses in time slots A, B, C, and D of its second subset, and each of these pulses is either negative or positive depending on whether elements A, B, C, and D are to be on or off, respectively.

To turn on a particular element requires signals on two rows: a row-select and a column-select signal; i.e., it requires the coincidence of a positive pulse on one of the rows and simultaneously a negative pulse on another row. The negative pulse occurs on the row which is connected to the column containing that element. For example, in FIG. 2, Part (a) the LC element J is turned on by controlling source 20 to supply a negative pulse via column-select signal V2 in its time slot J. Thus, the coincidence of the positive pulse (+V) from row-select signal V1 and the negative pulse (-V) from column-select signal V2, both pulses being in time slot J, is effective to turn on LC element J. In a similar fashion, LC element B is turned on by the coincidence of the positive pulse in signal V2 and a negative pulse in signal V5, both pulses occurring in time slot B.

A specific illustration of the half-period (single frame) waveforms for turning on element F, with all other elements off, is shown in FIG. 2, Part (b). In time slot F the positive pulse in row-select signal V2 and the negative pulse in column-select signal V4 (both pulses are shown stippled) are effective to turn on element F. Meanwhile, it can be shown by inspection of these waveforms that no other element in the array experiences simultaneously a positive and a negative pulse. Therefore, all other elements are off. This situation, of course, is illustrative only. It is indeed possible and often desirable that more than one element can be turned on simultaneously by simply providing the necessary simultaneity of positive and negative pulses in the same time slots of different signal waveforms.

In all of these cases, the signal waveforms in FIG. 2 represent a single frame which, as is well known in the art, should be repeated in the next frame of the waveform, but with opposite polarity for all pulses, so that the average value over two frames (one period) is essentially zero and no net dc voltage as supplied to the LC elements.

Although the foregoing illustration of a 10 element array driven by only five external leads is illustrative of the concepts of my invention, it should be clear that this scheme can be generalized to different size arrays in which M=(N-1)N/2 elements are addressed by N external leads. Briefly, to address an element (x,y) in the x-th column and y-th row, a row-select signal on the y-th row is constructed so that its first subset contains (N-y) pulses of one polarity in the time slots corresponding to the (N-y) elements in the y-th row, and its second subset contains (y-1) pulses (one or more of which may have the opposite polarity, but these pulses are related to the selection of other elements). In addition, a column-select signal on the (N+1-x)th row is constructed so that its first subset contains (x-1) pulses of one polarity, and its second subset contains (N-x) pulses of either polarity in the time slots corresponding to the (N-x) elements in the x-th column. The y-th pulse of the second subset of (N-x) pulses is of opposite polarity to turn (x,y) on or of the same polarity to turn (x,y) off. In the example given above in FIG. 2, Part (b), the element F corresponds to element (x,y)=(2,2).

Several practical considerations, the need to refresh and the available contrast, are worthy of comment. Regarding a refresh cycle, if the display device does not have intrinsic memory or long persistence, it should be refreshed fast enough that flicker is not perceptible; i.e., the addressing signals should be repeated at faster than a 30 Hz frame rate. Regarding contrast, to leave off, for example, element A, the signals V1 and V5 are both +V in time slot A to produce zero potential difference across element A during the A interval. However, during the remainder of the frame, the addressing of the other elements will disturb element A by signals of .+-.V. Counting these disturbances, one finds there are 2(N-2) pulses in the frame. For the example illustrated, N=5 and there are six disturb pulses on each and every element. If the display device is a refreshed liquid crystal display which responds to the rms value of the signals applied to it, then the performance obtained will be determined by the ratio of rms voltages on selected and unselected elements. Taking into account the disturb pulses gives to the following equation: ##EQU1##

It is to be understood that the above-described arrangements are merely illustrative of the many possible specific embodiments which can be devised to represent application of the principles of the invention. Numerous and varied other arrangements can be devised in accordance with these principles by those skilled in the art without departing from the spirit and scope of the invention. In particular, considerable improvement in performance can be realized by taking advantage of a priori restrictions on the set of allowable patterns, as in a bargraph or pointer display.

Thus, in accordance with another embodiment of my invention, a ten-element pseudo-analog pointer display 40 shown in FIG. 3 utilizes a modified meander layout 42 so that the elements A to J can be arranged physically in a straight or curved line and can be interconnected electrically with fewer leads (N=5) than required in a matrix. Layout 42 is equivalent to the interconnection scheme of FIG. 2 except that the columns x1 to x4 are arranged in a straight line. Accordingly, like elements in FIGS. 2 and 3 are given identical reference numerals. The addressing scheme, however, is different. In particular, each lead y1 to y5 is connected to a voltage V1 to V5, respectively, whose waveform is a unique member of a set of orthonormal functions. Suitable sets of waveforms include phase-shifted pulses (shown), pseudorandom binary sequences (see I. A. Shanks et al, SID Symposium Digest, Vol. 10, p. 112 (1979)), and walsh functions (see A. R. Kmetz, Swiss Pat. No. 620036-C47 (1978)). Then every display element turns on equally because the rms potential difference across every intersection is equal. To create the dark pointer 44 against this bright background, any single intersection (x,y) can be turned off my making V.sub.N+1-x =V.sub.y so that the potential difference across the selected display element becomes zero. As illustrated, element G, which is circled and corresponds to (x,y)=(2,3), is turned off by making V.sub.4 =V.sub.3 ; i.e., by making V.sub.4 and V.sub.3 to be identical waveforms. Implementation of this addressing scheme is simplified by the fact that the low-voltage binary waveforms used can be generated by ordinary digital integrated circuits.

A linear array of 28 LCD segments was interconnected according to a modified meander scheme of the type shown in FIG. 3. The twisted nematic LCD had parallel polarizers to obtain positive contrast; positive contrast would have been obtained directly if the usual guest-host effects had been used instead. A total of eight external connections, with seven front-to-back-plate crossovers, was sufficient. Three additional connections would have been needed for a conventional matrix arrangement.

These eight pins were driven directly by the standard digital output port of a CMOS EPROM which contained the layout and waveform information. The three low-order (rapidly changing) bits of an oscillator/counter cycled through the addresses corresponding to the different waveform intervals, while the high-order bits slowly swept the quantity displayed by the pointer to exercise the demonstration device. Connecting the high-order address bits instead to an A/D converter would yield a voltmeter.

Another embodiment of my invention which exploits a priori pattern limitations is the pseudo-analog bargraph display 30 shown in FIG. 4. The bargraph format conveys no more information than the pointer, but it may be more legible. Here, N=6 leads drive a linear arrangement of M=15 adjacent display elements which indicates some variable such as temperature or speed. Every display element below the indicated value T.sub.o is turned on and every element above the indicated value is turned off. The display elements are interconnected electrically into a linear array 32 of the type shown as array 42 in FIG. 3, and the bipolar pulsed signals V1 to V6 are used advantageously for addressing.

These signals each have N=6 time slots which contain either a positive or negative voltage pulse (.+-.V) or a reference voltage (e.g., zero). First, each lead which connects only to elements which are to be turned on (black dots) is driven with a positive pulse (+V) while simultaneously all other leads are held negative (-V). Thus, lead y6 connected to column x1 is driven with a positive pulse 34 in the first time slot, and leads y1 to y5 are driven with negative pulses. Similarly, lead y5 connected to column x2 is driven with a positive pulse 36 in the second time slot. This procedure is repeated for each of the m columns (here m=2) which contain only on elements. Then, in the (m+1)th time slot (here, the third), the m leads which had been driven positive in the preceding m time intervals are driven negative simultaneously while all other leads are held positive. This has the effect of applying +2 V and -2 V in different intervals to each element in columns x1 to xm which contain only on elements. Consequently, columns of all-on elements are addressed in m+1=3 intervals, with zero average dc value and with no disturbance of unselected elements.

Unless the end of the bar happens to coincide with the end of a column, the group of elements containing the end of the bar remains to be addressed. This group includes a column (e.g., x3) containing both on elements (black dots) and off elements (absence of dots). Such a column is labeled mixed. A mixed column such as x3 is addressed in the (m+2)=4th time slot by applying a positive pulse 38 to the (N+1-x)=4th lead which is common to that column while simultaneously applying negative pulses 37 and 39 to leads 2 and 3 so as to turn on elements 31 and 33 in that group. The reference level (zero) is simultaneously applied to the leads 1, 5 and 6 connected to off elements (e.g., 35). Then, in the (m+3)=5th time slot the pulses of the (m+2)=4th time slot are repeated with reverse polarities to cancel any dc value. On elements (e.g., 31, 33) in this mixed group receive twice the voltage of off elements (e.g., 35) in that group, and half-select disturbances appear elsewhere in the array. At most N intervals are needed in the addressing period, where, as before, N is the number of leads. On elements see an rms voltage of V(8/N).sup.1/2 or V(10/N).sup.1/2 '; off elements see V(2/N).sup.1/2 or 0. The worst-case discrimination ratio is thus 2, with a .+-.6% nonuniformity in the voltage on selected elements.

The various embodiments of my invention may incorporate different types of LC elements; i.e., rms-responding elements (such as TN-LCs or guest-host LCs) or memory elements (such as those described by D. W. Berreman et al in SID Symposium Digest, Vol. 13, p. 242 (1982)).