Constant Current Source Circuit

1. Field of the Invention

This invention relates to a constant current source circuit, and more particularly, to a semiconductor current source circuit having constant current characteristics whose current level is substantially unaffected by a change in the source voltage which biases the circuit.

2. Description of the Prior Art

Constant current source circuits are often used in integrated circuit (IC) design, and many forms of these circuits have been developed. A requirement for constant current sources is that the operating current does not change when a variation in the power source voltage occurs. Constant current source circuits are also ideally required to operate at a low power supply voltage with low power consumption.

In practice, certain of the constant current source circuits used in integrated circuits have low power consumption but fail to achieve good constant current characteristics. Alternatively, other constant current source circuits are able to maintain a constant current level but are found to be less efficient insofar as power consumption is concerned.

Two types of conventional constant current source circuits are shown in FIGS. 1 and 2 and are more fully discussed below in the section entitled "Description of the Preferred Embodiments".

The subject invention relates to a novel constant current source circuit for producing an operating current which remains substantially stable in the presence of fluctuations in power source voltage, yet which is able to operate at a relatively low power supply voltage with low power consumption.

These and other objects are achieved in the constant current source circuit of the invention which includes a power source voltage supply terminal which is designed to receive a DC power source voltage; a reference potential terminal; a current source; a first transistor connected at its collector to said power source voltage supply terminal via said current source and at its emitter to said reference potential terminal; a current mirror circuit; a second transistor connected at its collector to the base of said first transistor via said current mirror circuit and at its emitter to said reference potential terminal, the base of said second transistor being connected to the collector of said first transistor, to effect a closed feedback loop through said second transistor, said mirror circuit and said first transistor for maintaining a constant current to the load; and a third transistor connected between said power source voltage supply terminal and said reference potential terminal via output terminals to which the load is designed to be connected, the base of said third transistor being connected to be driven by a current proportional to a current of said second transistor.

Accordingly, an object of the present invention is to provide a constant current source circuit which produces a stable current substantially unchanged by variations in its power source voltage.

Another object of the present invention is to provide a constant current source circuit which is able to operate with a low power supply voltage.

A further object of the present invention is to provide a constant current source circuit which is low in power consumption.

Additional objects, advantages, and features of the present invention will further become apparent to persons skilled in the art from a study of the following description and of the accompanying drawings, in which:

FIGS. 1 and 2 are circuit diagrams of conventional constant current source circuits relating to the field of the invention.

FIG. 3 is a circuit diagram showing a preferred embodiment of the constant current source circuit of the present invention.

FIGS. 4 to 7 are circuit diagrams of modified embodiments of the embodiment of FIG. 3.

The present invention will now be described in detail with reference to the accompanying drawings, namely, FIGS. 1 to 7. Throughout the drawings like reference numerals and letters are used to designate like or equivalent elements for the sake of simplicity of explanation.

Referring now to FIG. 1, there is shown an example of a constant current source circuit in common use in transistor circuits. As shown, NPN transistor 10 is connected at its collector to power source voltage supply terminal 12 to which is applied the positive power source voltage V.sub.cc. The emitter of transistor 10 is connected to reference potential terminal 14 via current source 16. The base of transistor 10 is connected via load resistor 18 to its collector and the power source voltage supply terminal 12. If the output current of current source 16 is I.sub.16, and grounded emitter circuit current amplification factor of transistor 10 is .beta..sub.1, the output current I.sub.out flowing through load resistor 18 (i.e., base current i.sub.b of transistor 10) is as follows: ##EQU1## and output current I.sub.out is thus kept constant.

However, current source 16 and the base-emitter junction of transistor 10 become connected in series between power source terminal 12 and reference potential terminal 14 when load resistor 18 is shunted, and thus a problem arises of a reduction in the utilization factor .eta.V.sub.cc of power source voltage V.sub.cc in respect of load resistor 18. In other words, if the voltage of the base-emitter junction of transistor 10 is V.sub.be, and the saturation voltage of current source 16 is V.sub.16(sat), the above-mentioned utilization factor .eta.V.sub.cc can be expressed as follows: ##EQU2##

If we assume, for example, that V.sub.cc =3 V, V.sub.be =0.7 V, and V.sub.16(sat) =0.1 V: ##EQU3##

Thus, only 73% of power source voltage V.sub.cc is supplied to load resistor 18.

One means of increasing power source voltage utilization factor .eta.V.sub.cc that has been devised previously is the constant current source circuit illustrated in FIG. 2. As shown, NPN transistor 10 and constant current source circuit 16 are connected in series between power source voltage supply terminal 12 and reference potential terminal 14 as in FIG. 1. However, the base of transistor 10 is connected to load resistor 18 via a first current mirror circuit 20 consisting of PNP transistors 22, 24, and a second current mirror current 26 consisting of NPN transistors 28, 30. Thus transistor 10 is supplied its base current I.sub.b from load resistor 18 via first and second current mirror circuits 20, 26.

If the saturation voltage between the collector and emitter of transistor 30 is taken as V.sub.ce(sat), power source utilization factor .eta.V.sub.cc can be expressed as follows: ##EQU4##

If we assume, for example, that V.sub.cc =3 V and V.sub.ce(sat) =0.1 V, then ##EQU5## which means that 97% of power source V.sub.cc is supplied to load resistor 18, representing an increase in .eta.V.sub.cc as compared with the constant current source circuit shown in FIG. 1.

However, in the conventional constant current source circuit shown in FIG. 2, current source 16 and the base-emitter junctions of transistors 10, 22 are all connected in series between power source voltage supply terminal 12 and reference potential terminal 14. This being so, the minimum value of power source voltage V.sub.cc(min) required to operate the constant current source circuit shown in FIG. 2 is, if the voltage of the base-emitter junction of transistor 22 is taken as V.sub.be22 and V.sub.be10 is the voltage of the base-emitter junction of transistor 10 as follows:

If we assume that V.sub.16(sat) =0.1 V, V.sub.be10 =0.7 V, and V.sub.be22 =0.7 V, we have the following:

Thus, although the power source utilization factor has been increased, another problem has arisen, namely, the minimum operating voltage V.sub.cc(min) is high.

Referring now to FIG. 3, there is shown that circuit diagram of a constant current source circuit constructed according to the present invention. In FIG. 3, first NPN transistor 10 has its collector connected to power source voltage supply terminal 12 via current source 16 and its emitter connected to reference potential terminal 14. The base of first NPN transistor 10 is connected to current mirror circuit 20 consisting of PNP transistors 22, 24. First PNP transistor 22 is connected between the base of first NPN transistor 10 and power source voltage supply terminal 12. Second PNP transistor 24, which is connected in a diode configuration, is connected between power source voltage supply terminal 12 and the base of first PNP transistor 22. The collector of second PNP transistor 24 is connected to reference potential terminal 14 via second PNP transistor 32. The base of second PNP transistor 32 is not only connected to the collector of first NPN transistor 10 but also connected to the base of third PNP transistor 34. The collector of third PNP transistor-34 is connected to power source voltage supply circuit 12 via load resistor 18, and its emitter is connected to reference potential terminal 14.

The constant current source circuit illustrated in FIG. 3 forms a closed loop circuit, consisting of the base of transistor 32, the collector of transistor 32 (i.e., the collector of transistor 24), the base of transistor 22, the collector of transistor 22 (i.e., the base of transistor 10), and the collector of transistor 10 (i.e., the base of transistor 32). In operation, when, for example, collector current I.sub.c10 of transistor 10 increases, negative feedback is effected, with base current I.sub.b32 of transistor 32, collector current I.sub.c32 of transistor 32, base current I.sub.b22 of transistor 22, collector current I.sub.c22 of transistor 22 (i.e., base current I.sub.b10 of transistor 10), and collector current I.sub.c10 of transistor 10 all decreasing. Thus, output current I.sub.out flowing through load resistor 18 is kept constant at the desired value, this value being established by current source 16 and transistors 10 to 34.

To find output current I.sub.out flowing to load resistor 18, taking the grounded emitter circuit current amplification factors of NPN transistors 10, 32 and 34 all to be equal to .beta..sub.n, and the grounded emitter current amplification factors of PNP transistors 22, 24 to be equal to .beta..sub.p, and assuming that the characteristics of PNP transistors 22, 24 of current mirror curcuit 20 are exactly matched, and assuming likewise that the characteristics of NPN transistors 32, 34 are exactly matched, we have the following formula: ##EQU6## where I.sub.c34, I.sub.c32 represent the collector of NPN transistors 34, 32, respectively, and I.sub.16 represent the current of current source 16.

Assuming that .beta..sub.n >>2, .beta..sub.p >>2, then 2/.beta..sub.n .apprxeq.0, 2/.beta..sub.p .apprxeq.0, and the load current or output current I.sub.out can be expressed, from the formula given above, as follows: ##EQU7##

Thus, if all current I.sub.16 of current source 16 can be considered to be the collector current I.sub.c10 of transistor 10, then it is B.sub.n times the base current I.sub.b10 of transistor 10 which is the collector current I.sub.c22 of transistor 22, which latter current equals the collector current I.sub.c32 of transistor 32 or collector current I.sub.c34 of transistor 34, i.e., output current I.sub.out flowing to load resistor 18.

In the circuit shown in FIG. 3, if the saturation voltage between the collector and emitter of transistor 34 is taken as V.sub.ce34(sat), the power source voltage utilization factor .eta.V.sub.cc can be expressed by the following: ##EQU8##

If, for example, V.sub.cc =3 V, and V.sub.ce34(sat) =0.1 V, then; ##EQU9## which gives a high power source voltage utilization factor .eta.V.sub.cc, with 97% of power source voltage V.sub.cc being supplied to load resistor 18.

Further, if the base-emitter junction voltages V.sub.be10, V.sub.be24 of transistors 10, 43 are taken as V.sub.be10 =V.sub.be24, and collector-emitter saturation voltages V.sub.ce22(sat), V.sub.ce32(sat) of transistors 22, 32 are taken as V.sub.ce22(sat) =V.sub.ce32(sat), then the minimum operational value V.sub.cc(min) of power source voltage V.sub.cc is as follows: ##EQU10##

If, for example, V.sub.be10 =V.sub.be24 =0.7 V, and V.sub.ce22(sat) =V.sub.ce32(sat) =0.1 V, then:

which is lower than in the conventional constant current source circuit in FIG. 2.

Referring now to FIG. 4, there is shown a partly modified form of the constant current source circuit of FIG. 3. The connection of the base of transistor 22, the base and collector of transistor 24, and the collector of transistor 32, is connected to the base of PNP transistor 34. The emitter of transistor 34 is connected to power source voltage supply terminal 12, and its collector is connected to reference potential terminal 14 via load resistor 18. With this type of configuration, since the collector current I.sub.c22 of transistor 22 is base current I.sub.b10 of transistor 10, then, if the characteristics of transistors 22, 34 are exactly matched, collector current I.sub.c34 of transistor 34, that is to say, output current I.sub.out, is:

with output current I.sub.out equal to base current I.sub.b10 of transistor 10. It will be readily understood from the above explanation that the same results as with the circuit of FIG. 3 can be obtained with the configuration shown in FIG. 4.

FIGS. 5 and 6 show further modified circuits in which the polarity of each of transistors 10 to 34 in the circuits illustrated in FIGS. 3 and 4 has been inverted. In these two cases, the power source voltage becomes negative, i.e., -V.sub.cc. With the polarity of current source 16 inverted, circuit operation is similar to that of the circuits of FIGS. 3 and 4, and similar results are obtained.

Next, referring to FIG. 7, there is shown an example of still another modified form of the circuit of FIG. 3. The area ratio of the emitters of transistors 32, 34 has been set at 1:N. In this case, output current I.sub.out is as follows: ##EQU11##

In the circuits depicted in FIGS. 3 to 7, by changing the emitter area ratios of any of the transistors except transistor 10, or inserting a resistance in series with any of the emitters, the collector current ratios of any of transistors 22 to 34 can be changed, and made into N-times or 1/N-times the base current of the transistor 10.

The present invention is not restricted to the embodiment described above. It can be embodied in various modified forms, provided there is no departure from the essential substance of the invention as defined in the accompanying claims.