Frequency to Voltage Converter

This invention relates to frequency to voltage converters usable in integrated circuits, and more particularly to frequency to voltage converters utilizing switched capacitor techniques to provide tightly controllable tolerances in an integrated circuit embodiment.

Frequency to voltage converters are used in many functions, such as phase-locked loops and tracking filters, designed for integration onto integrated circuits.

In the past, frequency to voltage converters have primarily relied upon RC networks in their design. Since resistors have a relatively poor tolerance factor in MOS integrated circuits, and are sensitive to process variations, such RC based designs were not acceptable where precision was required or, alternatively, off-chip resistors were used in the circuits.

The invention of the instant application is intended to rectify the above disadvantages of the prior art circuit. This is accomplished by utilizing, in several embodiments, switched capacitive devices as substitutes for resistors, and for additionally utilizing sized capacitors switched at a frequency such as to produce the desired voltage output as a function of frequency.

FIG. 1 shows an operational amplifier with a resistive feedback path as is well known in the prior art.

FIG. 2 is a circuit using an operational amplifier and having a switched-capacitor input.

FIG. 3 is a circuit similar to that of FIG. 2, but additionally employing a switched-capacitor feedback loop and a sample-and-hold output.

FIG. 4 is a schematic diagram of one MOS implementation of the circuit of FIG. 3.

FIG. 1 shows a conventional operational amplifier 20 as is known in the prior art, wherein the amplifier 20 has a feedback resistance R.sub.2, an input resistance R.sub.1 which is connected to an input voltage source, and the output is taken off the output of the operational amplifier.

As is well known, the gain of such a circuit may be represented by the formula V.sub.out /V.sub.in =-R.sub.2 /R.sub.1 or V.sub.out =-R.sub.2 .times.V.sub.in /R.sub.1. Thus, the gain of such a circuit is a function of the ratio of the two resistive elements therein.

As previously noted, resistors have a poor tolerance factor in integrated circuit design since variations in resistance are introduced by process variations. Therefore, the circuit shown in FIG. 1 may be improved by substituting a switched capacitor for the input resistor R.sub.1 as shown in FIG. 2. This circuit will generate a stable output voltage that is directly proportional to the switching frequency of the capacitor. The slope of the characteristic (V.sub.out /f.sub.Cl) can be varied by varying the size of the switched capacitor, the input (reference) voltage, or the feedback resistor.

As can be seen, the circuit uses a damped integrator for its gain element. The capacitor C.sub.3 is necessary in this implementation to absorb the current burst when C.sub.1 is switched to the input of the operational amplifier 20. With a DC reference voltage or input voltage, the switched capacitor circuit in the input path simulates a resistor with an effective value of: R.sub.EFF =1/f.sub.c C.sub.1 where f.sub.c =clock frequency. Utilizing the same formula as set forth with respect to FIG. 1, for the circuit for FIG. 2:

In operation, the capacitor C.sub.1 is switched first to the reference voltage level V.sub.in, and the capacitor is charged to V.sub.ref. The capacitor is then switched to the input of the operational amplifier and the charge on the capacitor is transferred to that input. Since the operational amplifier itself is connected as a damped integrator, the successive charges transferred from C.sub.1 to the input of the operational amplifier as C.sub.1 is switched a plurality of times, accumulates as a charge on capacitor C.sub.3.

It can be seen that the voltage characteristic of this device is linearly dependent on the switching frequency of the input capacitor C.sub.1. Because of the presence of the feedback resistor R.sub.2, however, the voltage characteristic is also dependent on an RC product (R.sub.2 C.sub.2), which, again, has a poor tolerance in integrated circuit design.

In FIG. 3, the resistor R.sub.2 is replaced by a second switched capacitor network which may have a constant reference switching frequency.

In the circuit of FIG. 3, the function V.sub.out is equal to -V.sub.ref (f.sub.in /f.sub.ref) (C.sub.1 /C.sub.2).

In this case, if C.sub.1 and C.sub.2 are identical, the output appears directly as a linear function of the input switching frequency for a set reference frequency, thus performing the frequency to voltage conversion desired.

In a preferred embodiment, the frequency f.sub.in may be several times the frequency f.sub.ref. Each time capacitor C.sub.1 is charged by application of the capacitor through the switch to V.sub.ref, and is thus switched to the negative input of the operational amplifier 20 the charge on capacitor C.sub.2 increases with each application of the charge from capacitor C.sub.1. When capacitor C.sub.2 is ultimately switched to its output position, the voltage is transferred to the input of a sample and hold circuit 21.

In order to generate a V.sub.out /f.sub.in function with a positive slope, the voltage/frequency characteristic must be made non-linear. This is accomplished by maintaining V.sub.in as shown in FIG. 3 at ground potential and applying a reference voltage V.sub.ref to the positive input of the operational amplifier. The output voltage would then be a function of the V.sub.ref (1+F.sub.in /F.sub.ref) (C.sub.1 /C.sub.2). This function is, of course, non-linear. In a system such as a phase-locked loop, a non-linear transfer characteristic is acceptable. Some applications, particularly telecommunications applications, require a linear positive slope on the V.sub.out /f.sub.in curve. In devices used in such telecommunications applications, an analog ground is typically generated somewhere between V.sub.DD (the most positive power supply) and V.sub.SS (the most negative power supply). This analog ground (V.sub.AG) is typically at 1/2 (V.sub.DD +V.sub.SS). If this analog ground can be held accurately while sinking or sourcing in current, a positive slope linear voltage/frequency can be generated by grounding the negative input V.sub.in and applying V.sub.AG to the positive input of the operational amplifier. Then if V.sub.in and V.sub.out are taken with respect to V.sub.AG, the resulting slope will be positive and linear.

FIG. 4 shows a typical complimentary MOS (CMOS) implementation of a circuit such as is shown in FIG. 3. An operational amplifier 20 is shown with a capacitor 22 forming one feedback path, and a second feedback path which comprises capacitor 24 and a pair of transmission gates 26 and 28 which are switched on by opposite phases (.phi.1, .phi.2) of a two phase, non-overlapping clock driven at a frequency f.sub.ref.

The negative input of the operational amplifier 20 is connected to a capacitor 30 which is switched between an input at V.sub.SS potential and the negative input terminal of the operational amplifier 20 by a pair of transmission gates 32 and 34 which are also opened alternately by two non-overlapping phases of a clock with a frequency f.sub.in.

The positive input to the operational amplifier 20 is connected to a voltage divider network comprising a N-channel transistor 36 having its drain and gate connected to a positive power supply V.sub.DD, and its source and bulk connected to the drain of an N-channel transistor 38 which has its source connected to the negative voltage supply of the circuit V.sub.SS. The source and bulk of transistor 36 and drain of transistor 38 are connected together and the node formed thereby is at the analog ground potential V.sub.AG which is applied positive input to the operational amplifier 20.

The output of the operational amplifier 20 is connected through a transmission gate 40 to a sample and hold capacitor 42 across which the output voltage V.sub.out is taken.

In operation, one plate of capacitor 30 is connected to the analog ground voltage V.sub.AG and during phase one of the F.sub.in clock, capacitor 30 is charged between V.sub.SS and V.sub.AG by allowing the transmission gate 32 to conduct. At the end of phase one, transmission gate 32 is rendered non-conductive and transmission gate 34 conducts, thus connecting capacitor 30 to the negative input of operational amplifier 20. Capacitor 22, forming a portion of the feedback network of the operational amlifier 20, is a filtering capacitor of relatively small size, provided merely to absorb the current burst when transmission gate 34 conducts the charge from capacitor 30 to the input of the operational amplifier. The operation of transmission gates 32 and 34 may occur any number of times desired with respect to one operation of transmission gates 26 and 28 depending upon the gain requirement of the particular circuit involved.

Initially, transmission gate 26 is conducting and transmission gate 28 which is operated off the opposite phase of the reference clock F at a frequency f.sub.ref is non-conducting. Each time the charge from capacitor 30 is applied to the negative input terminal of the operational amplifier a charge is built up on capacitor 24. After successive charges from capacitor 30 have accumulated on capacitor 24, transmission gate 26 will be rendered non-conductive and transmission gate 28 made conductive in order to transfer the charge on capacitor 24 to the sample and hold capacitor 42. To accomplish this transfer, the sample and hold transmission gate 40 operated at a frequency f.sub.sh will be rendered conductive until the charge is transferred to capacitor 42. Transmission gate 40 is then rendered non-conductive to isolate the sample and hold capacitor 42 from the operational amplifier circuit. The output voltage is read across sample and hold capacitor 42.

As noted above, the output voltage V.sub.out is equal to the reference voltage (which in this case is V.sub.AG) times the ratio of the input frequency to the switching frequency of capacitor 24, times the ratio of capacitor 30 to capacitor 34 in size. By selection of appropriate capacitor sizes and frequencies a linear positive slope of the curve V.sub.out versus f.sub.in is produced, with the slope being proportional to the relative sizes of capacitors 30 and 24.

While specific embodiments of the invention as a whole have been disclosed, many modifications may become apparent to those skilled in the art. The scope of the invention is intended to encompass such modifications and be limited only by the scope of the claims appended hereto.