High Speed Low Power MOS Buffer Circuit for Converting TTL Logic Signal Levels to MOS Logic Signal Levels

1. A buffer circuit for providing a MOS logic level from a TTL logic level comprising: a cross coupled latch formed from a first pair and a second pair of transistors, said pairs connected together in parallel, each of said transistor pairs including an N channel FET and P channel FET serially connected, the gate connections of each transistor pair forming first and second nodes with the common channel connection of the remaining transistor pair, said first and second switches serially connected to each end of said parallel pairs for supplying current to first and second ends of said transistor pairs in response to a clock signal, CSI, and an inverse clock signal, CSI,; means for connecting a power supply across ends of said first and second switches; first and second transistor gates connected to provide first and second signal paths to said nodes, one of said transistor gates connected to receive a TTL logic input level, and the second to receive a reference voltage level, said transistor gates operating in response to said CSI signal; first and second FET inverter chains, each having an input and output, said inverter chains connected to a supply of voltage for establishing a MOS logic level; and first and second current path means connecting one of said inverter chain inputs to one of said nodes and the remaining of said inverter chain inputs to the remamining of said nodes, said current path means operative in response to said CSI signal and CSI signal to open and close said current path means; whereby said signals at a first logic state connect said nodes to said reference level and TTL logic level, and open said current path means, and at a second logic state operates said cross coupled latch and connect said nodes to said inverter chain inputs whereby complementary MOS logic levels are produced.

2. A buffer circuit for providing a MOS logic state from a TTL logic signal comprising: a MOS FET latch comprising first and second parallel connected, pairs of series connected transistors, each pair comprising an N channel FET and P channel FET having a common gate connection, said common gate connection connected to the series channel connection point of an opposite transistor pair; first and second switches connected to supply and deliver current to one end and from a remaining end, respectively, of said parallel connected pairs of series connected transistors, one of said switches being connected to be enabled to a clock signal, CSI, and the remaining of said switches by an inverse clock signal, CSI; first and second input transistors connected to provide a reference voltage and said TTL logic signal through its respective channel to a respective one of said common gate connections, said input transistors having a gate connection operable in response to said CSI signal; first and second inverter chains for providing complementary MOS logic levels in response to first and second complementary logic levels applied to an input of said inverter chains; and path means for connecting one of said inverter chain inputs to one of said transistor pair common gate connections, and the remaining inverter chain input to said remaining transistor pair common gate connections, in response to a first state of said CSI signal and said CSI signal, and for isolating said inputs from said common gates in response to a second state of said CSI and CSI signals, whereby said inverters provide complementary outputs indicating the state of said latch during said first state of said signals.

3. A buffer circuit for providing complementary MOS logic levels in response to a TTL logic level comprising: a cross coupled MOS FET latch, said latching having first and second nodes, said latch assuming a logic state representing the difference of respective input potentials, at said nodes; means for coupling a reference voltage to one of said nodes and a TTL logic level to the remaining of said nodes in response to a first state of a clock signal, CSI, and an inverse clock signal, CSI; means for activating said latch in response to a second state of said CSI signal and CSI signal whereby said latch nodes assume a state dependent upon a previous voltage difference between said nodes; first and second inverter chains for providing complementary MOS logic levels in response to first and second complementary input logic levels; first and second path means connected to provide a connection between said first and second inverter chains and said first and second nodes, respectively, in response to said second state of said CSI and CSI signals, and for isolating said nodes from said inverter chains in response to said first state of said CSI signal and CSI signal, whereby said nodes assume a state determined by said TTL logic level and reference voltage, and said inverter chains are isolated from said latch, and during a subsequent state of said CSI and CSI signals, said latch is activated and said inverter chains are connected to nodes of said latch for providing complementary MOS levels, each said path means including first and second MOSFETS having channels connected in parallel, one of said MOSFETS being of an N type, and the second of said MOSFETS being a P type; one end of said parallel connected MOSFETS connected to a node, and the other end to an inverter chain; a third MOSFET having a channel connected from said other end to a common voltage potential, said MOSFETS having gates connected to receive one of said CSI and CSI signals, whereby during one state of said signals said node is connected to said inverter chain and during a subsequent state of said signals, said inverter chain is isolated from said node and connected to said common voltage potential.