Electrical Power Matching System

This invention relates to solar power systems, and more particularly to apparatus for operating a photovoltaic array at maximum power transfer conditions.

In recent years, the use of solar energy has become increasingly important as an alternate source of energy. Such a system is useful in an area having plentiful sunlight but little conventional energy resources. However, a photovoltaic array having a useful capacity is relatively expensive, and it is therefore important that it be operated at maximum efficiency conditions.

Numerous systems have been proposed and utilized for extracting the maximum power available from an array under varying conditions. As is well known, the available power varies with changes in the solar radiation level and the ambient temperature, and such systems include a power matcher for operating the system at peak power conditions. Prior art power matchers include the use of a temperature compensated reference voltage, the use of a pilot or reference photovoltaic cell, and means for measuring the power over a range of power outputs and then adjusting the system to the peak power point.

These foregoing prior art systems have the disadvantage that they only approximate the peak power point, or that their response time is too slow to make them usable in all types of power systems.

It is a general object of the present invention to provide an improved power matching system that is operable under various conditions, accommodates various arrangements of photovoltaic cells, and responds rapidly to changes in operating conditions.

A system in accordance with the present invention is particularly useful in connecting a power source such as a photovoltaic array to a load such as a synchronous electric motor. The system comprises means for sensing the voltage and the current of the source, means for adjusting the value of the load, means for incrementally changing the volt-ampere operating point of the source and thereby its incremental resistance, and control means responsive to said voltage, said current and said incremental resistance, and connected to said load adjusting means for adjusting said load to the level where the ratio of DC voltage to current is substantially equal to the incremental resistance.

The invention will be better understood from the following detailed description of specific examples of the present invention, the examples being shown in the figures of the accompanying drawings wherein:

FIG. 1 a block diagram of a system embodying the present invention;

FIG. 2 shows curves illustrating the operation of the system;

FIG. 3 is a schematic diagram of a circuit according to a preferred embodiment of the invention;

FIG. 4 shows another curve illustrating the operation of the invention;

FIG. 5 is a diagram of an alternate form of the invention; and

FIG. 6 is a diagram of still another alternate form of the invention.

FIG. 1 illustrates a system in accordance with this invention and comprises a DC source such as a panel or array 10 of, for example, crystal silicon photovoltaic cells. The panel is connected by lines 11 and 12 to a DC/DC converter 13, such as a buck converter, having a voltage ratio V.sub.out /V.sub.in =N (or I.sub.in /I.sub.out =N). A DC/AC inverter bridge 14 is connected between the converter 13 and a load 16 such as a synchronous motor 17 coupled to drive a centrifugal pump 18. The speed of the motor 17 is a function of the frequency of the AC output of the inverter 14, and the load imposed by the pump 18 is a function of its speed. Thus, the load of the system may be controlled by adjusting the frequency of the inverter.

The system further includes a circuit 21 for sensing the panel current I.sub.p, a circuit 22 for sensing the panel voltage V.sub.p, and a circuit 23 for controlling the frequency of the inverter 14 and, thereby, the value of the load. The current sensing circuit 21 includes a current resistor 26 having two taps 27 and 28. The tap 27 is connected to a capacitor 29 which blocks the DC current component but passes an AC current to be described, a full-wave rectifier 31, and a circuit 32 which receives the rectified current signal and the signal from the tap 28. The output of the control circuit 32 is connected by a line 33 to an input of the converter 13 and, as will be described, controls the conversion ratio N. The voltage sensing circuit 22 includes a voltage resistor 36 connected between the line 11 and ground, the resistor 36 also having two taps 37 and 38. The tap 37 is connected to capacitor 39, and a full-wave rectifier 41 is connected between the capacitor 39 and the control circuit 23. The tap 38 is connected directly to the control 23.

Capacitors 42 and 43 are connected across the lines 11 and 12 on opposite sides of the converter 13, and a resistor 44 in the line 11 represents the small signal AC panel resistance r.sub.p.

Before discussing the operation of the system, reference is made to FIG. 2 which shows volt-ampere curves for different solar radiation (insolation) levels of the panel 10 at a particular temperature. The numerals 46 and 47 indicate low and high insolation levels, respectively. The voltage and current values shown in FIG. 2 are, of course, only examples. The source 10 has a nonlinear voltage-current characteristic as shown, and different load magnitudes result in operation of the system at different positions on any given curve.

It is important for optimum utilization of the system that it always operate at the peak power point (PPP). As in other types of systems, this occurs when the load resistance is equal to some optimum value. Since this optimum load resistance changes with the panel temperature and the solar radiation level, to achieve and maintain maximum power transfer it is necessary to constantly adjust the motor load. As previously mentioned, the motor 17 drives the centrifugal pump 18 and the load on the motor is a function of its speed which, in turn, is a function of the AC frequency (for a synchronous motor). Thus the load is adjusted to match the panel maximum power point by changing the inverter frequency.

An important aspect of this invention is the discovery that the peak power point is that point on the panel curve, such as one of the curves shown in FIG. 2, at which the ratio of I.sub.p to V.sub.p is equal to the negative of the slope of the IV curve. This occurs at the knee of the curve 47 at substantially the point 48. This may also be stated as V.sub.p =I.sub.p r.sub.p where V.sub.p and I.sub.p are the DC voltage and current of the panel 10 and r.sub.p is the resistance 44 for a small incremental change in the current at the operating point on the curve. At the point 48, for example, the DC voltage is approximately 16 volts and the current is approximately 2.4 amps. Thus the ratio 2.4/16 equals the negative of the slope or tangent 49 at the maximum or peak power point 48. If the system were operating at the point 51 or at the point 52, for example, the above equality would not exist and maximum use would not be made of the system.

As previously mentioned, the control 23 operates to adjust the frequency of the inverter 14 to achieve the peak load point. Where a synchronous motor 17 is being powered, the motor speed follows the inverter frequency, and it is important that the frequency be changed slowly when an adjustment is made. If the frequency were changed rapidly, the motor 17 might not be able to change its speed at the same rate, and accordingly it might be pulled "out of synch" and stop. To prevent such an occurrence the variation, or ramp, of the frequency f with time is made gradual.

In the present system, the load is ramped or varied in accordance with the equation dp/dt=A.sub.o (V.sub.p -I.sub.p r.sub.p), where P is the load imposed on the panel, A.sub.o is a constant and the other terms are as previously defined. This is achieved by programming the frequency control chip of the inverter 14, which varies the frequency in response to a control voltage from the circuit 23, to operate according to this equation. The peak power point was earlier defined as V.sub.p =I.sub.p r.sub.p, and consequently dp/dt=0 at the peak power point. At loads less than maximum, dp/dt is positive; and at loads greater than maximum, dp/dt is negative. FIG. 4 shows this ramp signal plotted against the ratio V.sub.p /V.sub.pp where V.sub.p is the voltage at the actual operating point and V.sub.pp is the voltage at the peak power point. It will be noted that when V.sub.p =V.sub.pp, the ramp signal equals zero.

As mentioned, the criterion for operation at the peak power point is V.sub.p /I.sub.p =r.sub.p, and V.sub.p and I.sub.p may readily be measured. The small-signal AC resistance r.sub.p of the panel 10 could be determined by injecting a small AC current into the panel or by superimposing a small AC voltage on the panel DC voltage, measuring the AC components of the voltage and current, and determining their ratio to obtain r.sub.p. Such arrangements are shown in FIGS. 5 and 6. The system shown in FIGS. 1 and 4, however, accomplishes the same end without explicitly determining r.sub.p.

It is an important feature of this invention that the voltage of the panel 10 is modulated and the frequency of the inverter 14 is controlled in a novel and advantageous manner. The DC/DC converter 13, which is a buck converter, switches the panel DC voltage at a converter switching frequency to produce an alternating signal having an adjustable duty cycle. The voltage ratio N=V.sub.out /V.sub.p of the converter 13 is essentially equal to the duty cycle, and therefore N may be adjusted by changing the duty cycle. The output filter capacitance 43 of the converter 13 is substantially larger than the capacitance 42 across the panel 10, and, at a modulating frequency to be described hereinafter, the reactance of the capacitor 43 is much less than r.sub.p. Consequently a small change in the converter 13 duty cycle produces a proportional change in the panel 10 voltage. Further, because of the relatively large filter capacitor 43, the output voltage V.sub.out of the converter 13 is approximately constant at the frequency of modulation. As a result, .DELTA.V.sub.p =-.DELTA.N V.sub.out /N.sup.2, and .DELTA.VP=-V.sub.p /N .DELTA.N, where .DELTA.N is a small change in N and represents a small signal AC component of the converter ratio N=V.sub.out /V.sub.p. The DC panel voltage and current are thus modulated by modulation of the buck converter ratio, N, which in turn is modulated by modulation of the switching duty cycle. While these relations are approximations, they are sufficiently accurate to closely match the power in the present system.

In the specific example of the invention shown in FIGS. 1 and 3, the switching frequency of the converter 13 is approximately 10,000 Hz, and the modulation of the duty cycle is at approximately 300 Hz.

With specific reference to FIG. 1, the panel current, including the DC component and the AC modulating component, flows through the resistor 26. The DC component is blocked by the capacitor 29, and the AC component is rectified and is indicated by the notation V.sub.2. A percentage k of the full panel current, comprising essentially the DC component, is represented by the voltage V.sub.1 on the tap or terminal 28. The control circuit 32 subtracts V.sub.2 from V.sub.1, and the difference, or error signal, is fed back in the line 33 to the converter 13. The modulating circuit in the converter 13 adjusts by servo action, the modulation of the duty cycle in order to null the quantity (V.sub.1 -V.sub.2) and thereby maintain the percent modulation of the panel current constant. The terminal or tap 28 is located to provide k of approximately 5% peak-to-peak modulation of the current when V.sub.1 =V.sub.2.

Similarly the panel voltage V.sub.p appears across the resistor 36. The AC component at the terminal 37 is rectified and is indicated by V.sub.4. The percentage k of the full voltage at the terminal 38 is indicated at V.sub.3, and the control 23 subtracts V.sub.4 from V.sub.3. The percentage k of total voltage sensed at the tap or terminal 38 is identical with the percentage k of total current sensed at the terminal 28. The difference between V.sub.3 and V.sub.4 represents the resulting deviation in the percent modulation of V.sub.p, and it is fed to the inverter 14 and serves as the load ramp control signal.

It was previously mentioned that load ramp control signal of the inverter 14 is represented by the equation dp/dt=A.sub.o (V.sub.p -I.sub.p r.sub.p). It can be shown mathematically that, when the feedback loop including the control 32 operates on .DELTA.N to maintain V.sub.2 substantially equal to V.sub.1 at all operating points of the operating curve, such as curve 47 of the panel, then V.sub.3 -V.sub.4 =k (V.sub.p -I.sub.p r.sub.p). The right-hand term, of course, is the same as the load ramp control signal previously discussed and shown in FIG. 4, and the system operates to maintain V.sub.3 -V.sub.4 =0 where the system is at the peak power point. If the insolation level increases, V.sub.3 -V.sub.4 becomes positive and increases the inverter frequency and hence the motor speed; this action changes the operating point on the curve 47 to achieve V.sub.3 =V.sub.4.

A circuit for continuously maintaining the system at the peak power operating point is shown in FIG. 3. The circuit of FIG. 3, which is the preferred embodiment of the invention, has a slightly different construction from that of FIG. 1 but its operation is essentially the same.

A voltage representing the array current appears at terminal 27 and passes through a buffer amplifier 61; the amplifier 61 output branches at point 62, and one branch includes a capacitor 63, an amplifier 64 and a full wave rectifier 65. The capacitor 63 and the rectifier 65 function the same as the capacitor 29 and the rectifier 31 in FIG. 1. The output voltage V.sub.2 of the rectifier 65 represents the panel AC current and it is fed to an input 67 of a summing amplifier 68.

The other branch from the point 62 is fed on a line 69 to the same input 67, and this signal-V.sub.1 represents the panel DC current. The difference (V.sub.1 -V.sub.2) appears at the output 71 of the amplifier 68.

The AC panel current is much smaller than the DC panel current, and in the arrangement shown in FIG. 1, they are brought to equality by locating the tap 28 so that it sees only a small proportion, such as 5%, of the total current. The same result is achieved in FIG. 3 by branching the signal at the point 62 and then amplifying the AC current signal in the amplifier 64 by a factor of approximately twenty. In both circuits the two current components are made approximately equal, and the difference or error signal, if any, appears at the input 67 and is amplified and passed to the output 71. This error signal is passed through a variable resistor 72 to a summing amplifier 73. A zero-offset variable resistor 74 adjusts the magnitude of the other input to the summing amplifier 73. The output of amplifier 73 is fed to the cathode of a diode 76.

A square wave generator 77 produces a square wave having a 50% duty cycle on a line 78 which is connected to the anode of the diode 76. The voltage level at the output of the circuit 73 and on the cathode of the diode 76 controls the amplitude of the square wave pulses which are fed on a line 79 to a control circuit 81 for the converter 13.

This converter 13 is a type known as a buck converter, and as previously described it converts an input DC voltage to a different level output DC voltage by repetitive switching between the input voltage and an inductor connected to the output. The switching frequency may be on the order of 10,000 Hz, and the voltage ratio of the converter is a function of the duty cycle (% on-time) of the switch. The converter includes the input 79 and the switch duty cycle is varied in accordance with the magnitude of the voltage on the input 79. Thus, the duty cycle is changed or modulated at the 300 Hz frequency of the signal on the input 79, and the difference between the two values of the duty cycle depends on the magnitude of the square wave pulses at the input 79. The control 81 of the converter adjusts the duty cycle which, as previously mentioned, changes the panel AC current component and the value of V.sub.2, which, in turn, controls the control 81. The feedback loop thereby operates to hold V.sub.1 equal to V.sub.2.

The panel voltage signal appears at the terminal 37 and passes through a buffer amplifier 86. The signal branches at the point 87, and the AC component passes through a capacitor 88 and a full wave rectifier 89, whereas the DC component passes through a line 91. A summing amplifier 92 combines V.sub.4 and V.sub.3 and produces an output signal (V.sub.3 -V.sub.4). This panel voltage circuit is constructed and operates similarly to the panel current circuit described above.

The output signal (V.sub.3 -V.sub.4) is fed to a chip in the inverter 14 which may be a conventional six step inverter. The inverter output forms a three-phase AC power supply for the motor 17. The motor is a synchronous AC motor and its speed is controlled by the inverter output frequency which, in turn, is controlled by the signal (V.sub.3 -V.sub.4). As previously described, the motor speed controls the value of the load and holds it at the value to extract maximum power from the panel 10.

FIGS. 5 and 6 show alternate forms of the invention. With reference first to FIG. 5, a DC power source 101, such as a solar panel, having a nonlinear voltage-ampere characteristic includes an internal resistance r.sub.p indicated by the numeral 102, and it is connected across an adjustable load R.sub.L 103. Connected across the power lines 104 and 105 is a parallel branch including a switch 106 and a test resistor r 107 which has a high value as compared with R.sub.L.

When the switch 106 is open, a source voltage V (which is essentially equal to the load voltage) exists across the lines 104 and 105 and a source current I flows through the circuit. When the switch 106 is closed, there is a slight change in the load; the line voltage becomes V+.DELTA.V and the load current becomes (V+.DELTA.V)/R.sub.L, where V is the source voltage and .DELTA.V is the change in the source voltage.

As previously described, at the peak power point, or maximum power transfer point, .DELTA.I/.DELTA.V=-I/V, and this relation is valid in the FIG. 5 circuit because the test resistance r is very large compared to R.sub.L and consequently the changes in the voltage and current are very small. .DELTA.I/.DELTA.V therefore approximates the derivative of the conductance of the source 101. The source current I and the incremental current .DELTA.I are sensed by components 108 and 109 connected across a current resistor 110 in the line 105, which is very small compared with r.sub.p and R.sub.L, and the source voltage V and incremental voltage .DELTA.V are sensed by components 111 and 112 connected across the lines 104 and 105. Thus, R.sub.L may be adjusted to make .DELTA.I/.DELTA.V=-I/V as previously described.

Further, it can be shown that

where I.sub.r is the current through resistor 107. Also,

The last equation shows that the current through resistor 107 equals the negative of twice the change in load current at the peak power point, and accordingly the load may be adjusted to achieve this equality. A sensor 113 senses I.sub.r.

The load R.sub.L in FIGS. 5 and 6 may be a DC load or it may include an inverter and an AC load, as shown in FIG. 1. The switch 106 and the resistor 107 may, of course, be formed by electronic components which periodically produce a small current change in the test branch.

The circuit shown in FIG. 6 is similar to that of FIG. 5, but in FIG. 6 the test resistor 116 is connected in series with the source and the load, and a switch 117 is connected across the resistor 116. The resistor 116 has a very low value compared with the load R.sub.L.

When the switch 117 is closed, the voltage is V and the current is I, and when the switch 117 is opened there is a slight change in panel voltage to V+.DELTA.V and the current through R.sub.L to (V+.DELTA.V)/(R.sub.L +r).

Further,

since

Consequently the voltage V.sub.r (measured by a circuit 119) across the test resistor 116 is equal to the negative of twice the change in the source voltage when the system is operating at the maximum power transfer point.

It will be apparent that a novel and useful system has been provided. It operates to maintain the system at the maximum power transfer point despite changes in operating conditions, and it responds relatively quickly to such changes. This last factor is important where the load is a synchronous motor which may drop out of synchronism if the frequency does not quickly follow changes in conditions. The system is usable with different types of DC power sources and loads. In the instance when the source is a solar panel, no adjustment is needed for varying numbers of series or parallel array modules. Further, the system is not sensitive to the solar cell characteristics, operating temperature, insolation level or dirt accumulation, because the system functions by sensing the panel voltage and current. Loads other than an AC synchronous motor may, of course, be used. For example, in FIG. 1 the load may include a brushless DC motor, in which case the inverter 14 would be deleted and the control circuit 23 would be constructed and connected to adjust the DC output voltage of the converter 13. The control circuit 23 in such a construction would be an average ratio control connected to adjust the ratio N of the converter 13.