Field Programmable Device

The present invention relates to a field programmable device, more particularly, a programmable read-only memory (P-ROM) with junction-shorting type memory cells.

FIG. 1 shows a programmable device in which the contents of a ROM can be written in accordance with a user's need. As shown in FIG. 1, each memory cell of the junction breakdown type employed in the programmable ROM device has the structure of a transistor whose base is not wired. Such memory cells M.sub.11, M.sub.12 . . . are connected at the point of intersection between word lines W.sub.1, W.sub.2 . . . and bit lines B.sub.1, B.sub.2 . . . . A writing operation is carried out in such a way that the cell is supplied with a writing current (programming current) to break down the emitter-base junction of the cell (i.e., to bring the cell into its conductive state) and thus turn the cell into a P-N diode (e.g., M.sub.12 or M.sub.21) formed at the base-collector junction. More specifically, one of the bit lines and one of the word lines are sequentially selected in accordance with data to be written, and the aforementioned writing operation is executed for each cell located at the intersection point between the particular word line and bit line. A P-N-P-N structure is therefore formed between the cell for which the writing operation has been completed (and which has become a diode), and the cell for which the writing operation has not been completed which remains a transistor. In order to stably and reliably program the ROM, the writing current needs to be applied between the selected bit line and word line without turning the SCR "on", thereby permitting the writing current to be supplied to the cell at the intersection point of these lines.

The aforementioned word line is formed of a diffused layer. In a case where the diffused layer has defects and where the non-selected word line, which ought to hold a high withstand voltage during the writing operation, allows current to leak out, the programming (writing) current flows out to the substrate of the cell through a parasitic P-N-P transistor which is formed by the cell and the substrate. Even when the leakage current is slight, it is multiplied by .beta. (current gain) by means of the P-N-P transistor. Therefore, the leakage current needs to be suppressed to the utmost.

An object of the present invention is to provide a programmable device capable of stable and reliable programming.

Another object of the present invention is to prevent the turn-on of a P-N-P-N structure in a junction breakdown type memory; the P-N-P-N structure being formed by a memory cell in which data has been written (which has become a diode), and a memory cell in which data has not been written (which remains a transistor).

Still another object of the present invention is to suppress a leakage current which is attributed to a vertical type parasitic transistor appearing in the writing mode of the memory; in a junction breakdown type memory.

In one aspect of performance of the present invention, a field programmable device comprises a plurality of word lines, a plurality of bit lines which are disposed in a manner to intersect the word lines, a plurality of cells which are respectively connected to the word lines and the bit lines, and a voltage supply means. The voltage supply means supplies non-selected ones of word lines with voltage large enough to prevent parasitic P-N-P-N elements, which are formed by the cells and the word lines, from turning on, whereby the programming current for the cells is hindered from flowing out.

Further objects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

FIG. 1 is a circuit diagram schematically showing a P-ROM;

FIGS. 2 and 3 are circuit diagrams of the arrangement of a word driver in the P-ROM;

FIG. 4 is a schematic sectional view of an example of the bit lines of the semiconductor of the P-ROM in FIG. 1;

FIG. 5 is an equivalent circuit diagram of the bit lines in FIG. 4;

FIG. 6A is a circuit diagram of a first embodiment of the present invention;

FIG. 6B is a detailed circuit diagram of the embodiment of 6A,

FIGS. 7 and 8 are circuit diagrams of second and third embodiments of the present invention; respectively,

FIGS. 9 and 10 are a schematic perspective view and an equivalent circuit diagram, respectively for explaining a problem which is involved in the memory illustrated in FIG. 4; and

FIG. 11 is a circuit diagram of a fourth embodiment of the present invention.

Referring to FIG. 1, symbol WD represents a word driver which drives the corresponding word line to a H (high) or L (low) level. As shown in FIG. 2 or FIG. 3, the circuit arrangement of the word driver comprises transistors Q.sub.1 -Q.sub.3 (FIG. 3) (or Q.sub.1 and Q.sub.2 (FIG. 2)), resistors R.sub.1 -R.sub.3 (FIG. 2) (or R.sub.1 and R.sub.2 (FIG. 3)) and a diode D (FIGS. 2 and 3). In operation, the input transistor Q.sub.1 receives an output RD from a row decoder, and the output stage (transistor Q.sub.2 (FIG. 2) or transistors Q.sub.2 and Q.sub.3 (FIG. 3)) drives the word line W. In FIG. 3 when the decoder output RD=H, the transistors Q.sub.1 and Q.sub.2 turn "on" and the transistor Q.sub.3 turns "off", so that the word line W becomes the L level. This is the selected state of the word line. In the non-selected state of the word line, the decoder output RD=L is received, the transistors Q.sub.1, Q.sub.2 turn "off" and the transistor Q.sub.3 turns "on", and the word line W becomes the H level. The word driver in FIG. 2 is called a resistor drive type word driver, while the word driver in FIG. 3 is a type provided with an off-buffer. Shown at P.sub.1, P.sub.2 . . . in FIG. 1 are programming terminals, which are supplied with the writing current during the writing mode of the programmable ROM. (More specifically, the writing current is fed from a constant-current source of approximately 120 mA and the corresponding voltage becomes approximately 15 V at the maximum. A supply voltage Vcc is 5 V. In writing data into, for example, the memory cell M.sub.11, the word line W.sub.1 is an L level because of the word driver WD, and the writing current is applied from the terminal P.sub.1 to the cell M.sub.11. Then, this cell M.sub.11 has its emitter-base junction broken down and becomes a diode, allowing current to flow from the bit line B.sub.1 to the word line W.sub.1. Shown at R.sub.1, R.sub.2 . . . are reading terminals which receive outputs from a column decoder in the reading mode of the P-ROM. By way of example, when an H (high) level voltage is applied to the terminal R.sub.1 with the word line W.sub.2 selected, current flows through a path including the terminal R.sub.1, a diode D.sub.1, the memory cell M.sub.21, the word line W.sub.2 and the word driver WD, hence, the bit line B.sub.1 becomes an L (low) level. Consequently, a transistor T.sub.1 is in an "off" state, and a sense amplifier SA, which is composed of resistors R.sub.5 -R.sub.7, transistors Q.sub.5 -Q.sub.7, etc., turns the transistors Q.sub.5 and Q.sub.6 "off" and the transistor Q.sub.7 "on", so that the output OUT of the P-ROM becomes an H (high) level. On the other hand, when the memory cell is not written into, e.g., M.sub.11 is selected, the corresponding bit line becomes an H (high) level, and the output of the sense amplifier SA becomes an L (low) level. In this way, the stored contents of the P-ROM are read out.

FIG. 4 shows a particular structure of the essential portions of a P-ROM. Numeral 10 designates a P-type semiconductor substrate, which is formed with an N-type epitaxial layer 12 on its surface portion and an N.sup.+ -type buried layer 14 in its interior. The epitaxial layer 12 is formed containing P-type diffused regions 16. In each P-type diffused region 16 an N-type diffused region 18 is formed. These parts, 12, 16 and 18, serve as the collector, base and emitter regions of the memory cell transistor, respectively. It is assumed that the memory cell M.sub.11 of the structure has not been written into, whereas the memory cell M.sub.12 has been written into, as in FIG. 1. Since the emitter-base junction of the written cell M.sub.12 is in a short-circuited state, the bit line B.sub.2 is formed with a lateral P-N-P transistor (Tr.sub.1 in the equivalent circuit diagram FIG. 5) which is constructed of the P-type regions 18 of the cell M.sub.12, the N-type layer 12, and the P-type region of the cell M.sub.11. The unwritten cell M.sub.11 constructs a vertical transistor (Tr.sub.2 in FIG. 5) out of the N-type layer 18, and P-type layer 16, and the N-type layer 12. These transistors Tr.sub.1 and Tr.sub.2 and the bit lines B.sub.1 and B.sub.2 are connected as shown in FIG. 5. A P-N-P-N element, a thyristor, is connected between the bit lines B.sub.2 and B.sub.1, that is, between the bit line of the written cell and the unwritten cell.

Since this P-N-P-N element does not have a trigger terminal, it may seem not to turn "on". However, the N-type layer 12 which acts as the base of the lateral transistor Tr.sub.1 and the collector of the vertical transistor Tr.sub.2 has a large capacitance C with respect to ground of the P-ROM. Therefore, when a voltage is applied to the bit line B.sub.2, a charging current flows through a path comprising the bit line B.sub.2, the N-type layer 18 as well as the P-type layer 16, the N-type layer 12 and the capacitor C, and it triggers the P-N-P-N element. The transistor Tr.sub.1 is rendered conductive with the charging current acting as its base current and causes its collector current to flow. This collector current becomes the base current of the transistor Tr.sub.2 and renders the transistor Tr.sub.2 conductive. Once the transistor Tr.sub.2 has turned "on", the base current of the transistor Tr.sub.1 is maintained by the transistor Tr.sub.2, so that the transistors Tr.sub.1 and Tr.sub.2 hold their "on" states even when the charging current disappears. Since the collector voltage of the transistor Tr.sub.2 is fixed to a voltage being about 0.2 V higher than that of the bit line B.sub.1, the base voltage of the transistor Tr.sub.1 rises to prevent this transistor from turning "off". Under this condition, when it is intended to write data into another memory cell belonging to the bit line B.sub.2, a high voltage is applied to bit line B.sub.2. Even when the constant-current source of 120 mA is connected, the writing current flows through a path consisting of the bit line B.sub.2, the transistors Tr.sub.1 and Tr.sub.2, the bit line B.sub.1, the written cell of the bit line B.sub.1 and the selected word line, without being applied to the selected cell. (Of course, when the bit line B.sub.1 does not contain a written cell, the current outflow along the path does not take place.)

The present invention is based on the above problem involved in the junction breakdown type P-ROM's, and is intended to solve it. FIGS. 6A and 6B show the first embodiment of the present invention. As shown in FIG. 6A, according to the present invention, a high voltage V is applied from an external terminal T to the word lines W.sub.1, W.sub.2 . . . through respective series circuits each of which comprises a resistor Ra and a diode Da. The charging of the capacitor C is performed, and there is no charging current based on the writing voltage applied to the bit line. Accordingly, the P-N-P-N element at Tr.sub.1 and Tr.sub.2 does not turn "on", and data can be written into the memory cell, e.g., M.sub.22 by applying the writing current. FIG. 6B illustrates in detail the first embodiment of the present invention shown in FIG. 6A. Like parts are designated by like references in FIG. 1 and FIG. 6B. The sense amplifier SA functions to read out the contents of the memory cells.

FIGS. 7 and 8 show the second and third embodiments of the present invention in which the high voltage V is applied to the word line W through the resistor Ra as well as the diode Da on the word driver side, as in FIGS. 2 and 3, respectively.

When the leakage occurs between the word line and another region, the parasitic P-N-P transistor, which is inherent in a P-N junction and whose collector is the substrate, turns "on". The result is a current, corresponding to the collector current i.sub.b .multidot..beta. (i.sub.b being the base current of the parasitic transistor), which flows out to the substrate. This phenomenon will be described with reference to FIGS. 9 and 10. The parasitic P-N-P transistor is a vertical transistor Tr.sub.3 whose emitter is the P-type base region of a memory cell M, whose base is the N-type collector region of the memory cell M and whose collector is a P-type substrate 10. When a leakage resistance r exists between the substrate 10 and an N-type layer 12 serving as the word line, the base current i.sub.b of the parasitic transistor Tr.sub.3 flows in the written cell as illustrated in FIG. 10, so that the transistor Tr.sub.3 turns "on", and the collector current i.sub.c is equal to i.sub.b .multidot..beta.. In the case of the P-ROM, only the selected word line becomes the L level with all the other non-selected word lines kept at the H level, and the selected bit line becomes an HH level (the high voltage level during the writing operation) in the programming mode. Accordingly, even when the selected bit line has the written cell connected thereto and the word line of this cell is not selected and is therefore at the H level, the selected bit line is at the HH level. Therefore, the current i.sub.b flows and the current of the selected bit line flows out to the substrate through the written cell. In contrast, when the HH voltage is applied to the word line W or N-type layer 12 as in the present invention, the base current i.sub.b does not flow and the current outflow is avoided. In FIG. 9, numeral 20 indicates a P.sup.+ -type isolation region.

FIG. 11 shows the fourth embodiment of the present invention. The output stage of each of the word drivers comprises a transistor Q.sub.2 and a resistor R.sub.3. The transistor Q.sub.2 has its emitter grounded its collector connected to one end of the resistor R.sub.3. The other end of the resistor R.sub.3 is connected to the cathode of a diode D. Further, the cathode of the diode Da is connected to that of the diode D. The anode of the diode D is connected to a voltage source V.sub.cc, and that of the diode Da to a voltage source V.

In the first to third embodiments of the present invention, the number of pairs of the resistors Ra and the diodes Da is equal to the number of word lines required. The fourth embodiment of the present invention (shown in FIG. 11) requires only one diode Da for all the word lines. Further, in the second and third embodiments, a diode D is required for each of the respective word drivers, whereas in the fourth embodiment, only one diode D suffices for all the word drivers.

As is apparent from the above description, the voltage V applied to the word line is made a fixed voltage which is at least 0.8 V higher than the writing voltage applied to the bit line. The voltage V is also applied to all the word lines in common. In the selected word line, according to the second and third embodiments of the invention, current flows through a path comprising a resistor Ra, a diode Da and an output transistor Q.sub.2. Current flows through a path comprising the diode Da, the resistor R.sub.3 and the output transistor Q.sub.2 in the case of the fourth embodiment. The current is limited by the resistor Ra or the resistor R.sub.3. As the power source voltage V is applied to the word lines, the constant current of the writing source is supplied to the programming terminals. In this case, however, the constant-current source needs to include a component which corresponds to the current flowing through the path of the parts Ra, Da and Q.sub.2 or the path of the parts R.sub.3, Da and Q.sub.2. The problems stated before arise, not only in the junction-shorting type memory cells referred to above, but also in fuse type memory cells, diode type memory cells etc., as long as the P-N junctions are arrayed in an identical manner as the epitaxial layer 12. The present invention is also effective when applied to programmable devices employing such memory cells. Furthermore, Schottky diodes may be used as the abovementioned diodes Da and D.

As set forth above, the present invention is very effective in that the turn-on of a parasitic P-N-P-N element and the outflow of a writing current to a substrate ascribable to a parasitic P-N-P transistor can be hindered in the programming mode of a programmable device by the simple expedient of applying a high voltage to the word lines.