Snubber Circuit for Use in an Uninterruptible Power Supply

Phase Synchronization Circuit, co-pending application, Ser. No. 06/525,369, filed on Aug. 22, 1983, invented by Paul M. Rhoads and Harold H. Cheffer, assigned to the NCR Corporation.

Power MOSFET Transfer Switch, co-pending application, Ser. No. 06/525,209, filed on Aug. 22, 1983, invented by Harold H. Cheffer, assigned to the NCR Corporation.

High Frequency Inverter, co-pending application, Ser. No. 06/525,371, filed on Aug. 22, 1983, invented by Harold H. Cheffer, assigned to the NCR Corporation.

1. Field of the Invention

The present invention is directed to uninterruptible power supplies and more particularly to a high speed reactive load power snubber circuit for dissipating current transients upon switching of an inverter to transfer alternating current from a load to a storage device of direct current upon the failure of the normal alternating current power line feeding such load.

2. Description of the Prior Art

In today's wide use of computers, data processors, controllers, etc. in data processing systems, it is extremely critical that the system be supplied with continuous power during its operation. Due to inadequate capacity and increasing load demands, commercially-supplied power is often subject to complete failure of the power signals or a reduction in the magnitude of the available voltage during peak demand periods. In cases where various customers subject the power system to sudden electrical loads, transients are generated in the system affecting the magnitude and phase of the supplied power signal.

Since the storage of data in a computer system is predicated on the continuous operation of the computer, power interruptions can adversely affect the integrity of the stored data. When the power drops abruptly, the computer will terminate operation probably with a high possibility of component damage. In order to overcome this situation, computers operating in a data processing system environment have been supplied with uninterruptible power supplies where the primary commercial power source and the reserve power source are connected in parallel. The power supply includes a commercial A.C. line power source and a D.C. voltage energized inverter power source connected in parallel to a switching mechanism which alternately couples one or the other of the two power supplies to the load to be energized. This power supply design provides a substantially uninterruptible power to the load. However, when an inductor load such as a motor is on the line, large current transients are developed upon the starting of the motor. Unless these current transients are dissipated quickly, they can reach a level which can destroy the solid state elements in the power supply. Where the inverter power source is supplying the power, prior power supplies have used silicon controlled rectifiers and large resistor loads to dissipate these current transients. The disadvantage of this type of arrangement is the slow response time of the rectifier in addition to the high cost of the resistor elements.

It is therefore a principal object of this invention to provide a circuit for use in an uninterruptible power supply which will dissipate current transients occurring in an A.C. power signal.

It is another object of this invention to provide a circuit for dissipating a current transient occurring in an A.C. power signal at a high rate of speed.

It is a further object of this invention to provide a circuit for dissipating a current surge in an A.C. power signal for use in an uninterruptible power circuit which is simple in construction and low in cost.

These and other objects of the invention are accomplished by providing a circuit associated with an inverter of an uninterruptible power supply for supplying an A.C. power signal from a D.C. source which includes a metal-oxide semiconductor field-effect transistor (MOSFET) whose gate electrode is connected through a transformer to a control circuit which receives a plurality of control signals including high frequency clock signals, a power failure signal, a signal indicating the presence of a current transient in the output of the inverter and a signal indicating the operating condition of the inverter. Upon sensing the occurrence of a power failure and the presence of a current transition, the control circuit will enable the high frequency clock signals to switch the transistor at a high rate of speed to apply the A.C. output of the inverter through the load until the current transient is dissipated.

FIG. 1 is a block diagram of the uninterruptible power supply in which the snubber circuit of the present invention is utilized;

FIG. 2 is a schematic representation of the snubber circuit of the present invention;

FIGS. 3A-3E inclusive disclose waveforms of the output signals associated with the operation of the snubber circuit.

Referring now to FIG. 1, there is shown a block diagram of the uninterruptible power supply in which the snubber circuit of the present invention is found. Included in the power supply is the A.C. line input circuit 20 over which appears the A.C. power signals supplied from a commercial power source and which are transmitted through an A.C. circuit breaker 22 and over lines 24, 26 to a line transfer logic circuit 28 which controls the switching of the power source between an inverter and the commercial power source. The line transfer logic circuit 28 will output over lines 30, 32 to the load 34 an A.C. signal received over lines 24, 26 from the A.C. line input circuit 20. The load 34 also receives an A.C. signal transmitted over lines 36, 38 from a D.C. to A.C. inverter logic circuit 40 which, when enabled, will convert the D.C. signal output of a 60 volt battery 42 received over the common ground line 44 and line 46 to an A.C. signal. The inverter logic circuit is enabled by signals appearing on bus 48 when generated by a transfer logic circuit 50 which receives signals over lines 52, 54 from an A.C. sensing circuit 56 representing the signal level of the A.C. signals being outputted from the A.C. circuit breaker 22. The transfer logic circuit 50, upon sensing a drop in the signal level of the A.C. signal, will output control signals over bus 48 to the inverter logic circuit 40 and bus 58 to the line transfer logic circuit 28 enabling the inverter logic circuit 40 to output A.C. power signals over lines 36, 38 to the load 34 through lines 30 and 32. When the A.C. line input 20 returns to its normal power level, the transfer logic circuit 50 will enable the line transfer logic circuit 28 to switch back to the input lines 24, 26 allowing the A.C. line input circuit 20 to supply the power over lines 36 and 38 to the load 34. This switching of the line input circuit 20 occurs in phase with the original line frequency of the signals appearing at the line input circuit 20. The transfer logic circuit 50 outputs over lines 51, 53 signals for disabling the A.C. circuit breaker circuit 22 when a system overload occurs. The circuit 50 also outputs signals over line 96 to an interface circuit 98 indicating the operating condition of the power supply.

Further included in the power supply is a 12 volt D.C. power supply 60 which receives the A.C. power signals over lines 62 and 64 and converts them to a 12 volt D.C. signal which is supplied over line 66 to power the various logic circuits in the power supply. Also included in the power supply is the snubber logic circuit 68 of the present invention which eliminates any abnormal current spikes which occur during the switching of the transfer logic circuit 28 between the A.C. line input circuit and the inverter logic circuit 40 in a manner that will be described more fully hereinafter. The circuit 68 receives control signals over bus 58 from the transfer logic circuit 50 and from the inverter logic circuit 40. Associated with the 60 volt battery 42 is a D.C. circuit breaker 70 connected to the battery 42 over line 71 and providing a current overload protection for the battery, a battery charging circuit 72 which converts the A.C. line signals appearing on lines 74, 76 to a charging current which is then supplied to the battery 42 over line 78 during the time the A.C. line power signals are available and a 12 volt auxiliary down switch 80 which supplies a 12 volt D.C. signal to power the logic circuits upon the failure of the A.C. line input. The switch 80 drops the 60 volt signal supplied over line 82 from the battery 42 through the circuit breaker 70 and outputs the 12 volt D.C. signal over lines 84 and 66 to the required logic circuits of the power supply.

Associated with the inverter logic circuit 40 is an A.C. sensing circuit 86 receiving over lines 88, 90 the A.C. signal output of the inverter logic circuit 40, the amplitude of such signals being used to regulate the amplitude and shape of the A.C. signals outputted by the logic circuit 40. The sensing circuit 86 drops the A.C. output signal level appearing on lines 92, 94 to 5 volts, allowing the signal to be compared with the signals being outputted by the logic circuit 40.

Referring now to FIG. 2, there is shown details of the snubber logic circuit 68 (FIG. 1) which includes a NAND gate 100 receiving over lines 102 of the bus 48 (FIG. 1) signals representing the condition of a pair of power MOSFETS (not shown) located in the inverter logic circuit 40. The MOSFETS are cycled to chop a D.C. current supplied from the 60 volt battery 42 (FIG. 1) to provide the A.C. power signals outputted by the inverter logic circuit 40. In the circuit disclosed in FIG. 2, that portion of the circuit to the right of the dotted line 104 is located in the snubber logic circuit 68 (FIG. 1) with the remaining portion of the circuit left of the dotted line being located in the transfer logic circuit 50. For a complete description of the inverter logic circuit 40, reference should be made to the previously cited co-pending application of Cheffer, Ser. No. 525,331, which application is fully incorporated herein by reference. For a complete description of the transfer logic circuit, reference should be made to the previously cited co-pending application of Rhoads et al., Ser. No. 525,369, which application is fully incorporated herein by reference.

The signals appearing on lines 102 which are part of bus 48 (FIG. 1) indicate the operating condition of the inverter logic circuit 40. The snubber circuit of FIG. 2 is enabled for operation only when the MOSFETS of the inverter logic circuit 40 are off during their operating cycle. This sequence ensures that the snubber circuit will not short out the inverter logic circuit at the time the inverter is supplying current to the load 34 (FIG. 1). The output signal of gate 100 is transmitted over line 106 to a NAND gate 108 whose output signal is transmitted over line 110 to a NAND gate 112.

The NAND gate 112 also receives a signal over line 114 from a comparator circuit comprising a 2902 operational amplifier 116 which compares a signal SIG representing the amplitude of the A.C. power signal 117 (FIG. 3B) being outputted by the A.C. sensing circuit 86 (FIG. 1) and which is received from the inverter logic circuit 40 over line 118 of the bus 48. As shown in FIG. 3B, when an A.C. power signal is supplied to an inductive load such as a motor, the current waveform 119 lags the voltage waveform 117. When the voltage waveform is switching from a positive to the negative portion of the waveform or vice versa, the current is still positive and in an inverter circuit will produce a spike 121 in the voltage waveform. The snubber circuit 68 is operated to dissipate the current to eliminate the spike whenever it occurs. As part of this operation, the amplifier 116 compares the signal level of the signal SIG received over line 118 with a reference signal 123 (FIG. 3A) designated as REF (FIG. 2) representing the required amplitude for the A.C. power signal being outputted by the inverter logic circuit 40 (FIG. 1). This signal is received over line 120. Whenever the amplitude of the signal SIG exceeds the signal REF, the amplifier 116 will output a high signal to the NAND gates 112 and 126. For a complete description of the circuits for generating the signals SIG, REF, reference should be made to the previously-cited co-pending application, Ser. No. 525,331.

The NAND gates 112 and 126 further receive 50 KHz. timing signals 123 (FIG. 3C) over lines 128 and 130 generated by an oscillator (not shown) located in the transfer logic circuit 50 (FIG. 1). The output signals of the NAND gates 112 and 126 are outputted over line 140 and 148 to inverter driver circuits 144 and 146 which are controlled by the output signal of a line driver enable circuit 142. The output signals of the driver circuits 144 and 146 are transmitted over lines 150 and 134 of bus 58 (FIG. 1) to one side of the primary windings 152 of a transformer generally indicated by the numeral 154. The transformer 154 also includes secondary windings 158 connected through rectifying diodes 151, 153 and resistor 162 over line 160 to the gate terminal 164 of a metal-oxide semiconductor field-effect transistor (MOSFET) generally indicated by the numeral 161. The MOSFET 161 further includes a drain terminal 168 connected over line 170 through a dropping resistor 172 to the cathode end of a diode 174 whose anode is connected to the output line 36 of the inverter logic circuit 40 (FIG. 1) over which the A.C. power signals are transmitted to the load 34.

A center tap of the secondary windings 158 of the transformer 154 is connected through line 176 to the source terminal 180 of MOSFET 161. The MOSFET 161 further includes a source terminal 180 connected over line 181 to the anode end of a diode 182 whose cathode end is connected to the output line 38 (FIG. 1) of the inverter logic circuit 40. The line 38 is also connected to the drain terminal 168 of the MOSFET 161 through a diode 184, line 186, node 188, line and the resistor 172. A resistor 190 shunted across the center tap portion of the secondary windings 158 of the transformer 154 forms a voltage divider circuit with resistor 162. Also shunted across the windings 158 is a back-to-back zener diode 192 for limiting the voltage applied to the gate terminal 164 of the MOSFET 161.

In the operation of the circuit shown in FIG. 2, upon an occurrence of a power failure in the A.C. supply, the line transfer logic circuit 28 (FIG. 1) is turned off disabling the A.C. line input circuit 20 and enabling the inverter logic circuit 40 to supply the A.C. power signals over lines 36, 38 to the load 34. At this time, the line driver enable circuit 142 (FIG. 2) receives over line 132 the signal POWER FAIL which goes low upon the amplitude of the A.C. signal appearing at the A.C. line input circuit 20 (FIG. 1) going below a predetermined level. In response to receiving the low signal, the driver 142 will output a high signal enabling the operation of the driver circuits 144 and 146. This sensing of the A.C. line input circuit 20 is accomplished by the A.C. sensing circuit 56 (FIG. 1) comprising a transformer (not shown) and whose output signals are transmitted over lines 52, 54 to the transfer logic circuit 50 (FIG. 1). Reference should be made to the previously-cited co-pending application of Rhoads et al., Ser. No. 525,369, for a description of the comparator circuits which generate the signal POWER FAIL.

The output signal of the NAND gate 108 will cycle between a high and low signal corresponding to the cycling of the power MOSFETS in the inverter logic circuit 40 (FIG. 1). If at this time the amplitude of the A.C. output signal 117 (FIG. 3B) of the inverter logic circuit 40 exceeds the reference signal 123 (FIG. 3A), the amplifier 116 will output a high signal over line 114 to the NAND gates 112 and 126. As the 50 KHz. clock signals appearing on lines 128 and 131 go high, the NAND gates 112 and 126 will output a corresponding high signal over lines 140 and 148 allowing the drivers 144 and 146 to output the corresponding clock signals which drive the transformer 154 to output corresponding control pulses over line 160 to the gate terminal 164 of the transistor 161, thereby cycling the transistor at a 50 KHz. rate. When the transistor 161 is turned on, the current path during the positive-going portion of the A.C. waveform is from line 38, through diode 182, the MOSFET 161, resistor 172, diode 174 and line 36 through the load 34 (FIG. 1) and back through line 38. During the negative-going portion of the A.C. waveform, the current path is from line 36, through diodes 178, resistor 172, MOSFET 161, diode 184 to line 38, load 34 (FIG. 1) and back through line 36. It will thus be seen that the MOSFET 161 is cycled at a very high frequency rate during which time the current transients of the A.C. signal will be dissipated through the resistor 172 and the MOSFET 161. Once the amplitude of the A.C. signal falls below the amplitude of the signal REF, the amplifier 116 will output a low signal, thereby disabling the NAND gate 112 which in turn shuts off the operation of the transformer 154 and the MOSFET 161 enabling the A.C. output signal of the inverter logic circuit 40 (FIG. 1) to be transmitted over lines 36, 38 to the load 34.

The integrated circuit elements disclosed herein are commercially available from the National Semiconductor Corporation of Mountain View, Calif.

Numerous modifications and adaptations of the system of the present invention will be apparent to those skilled in the art, and thus it is intended by the appended claims to cover all such modifications and adaptations which fall within the true spirit and scope of this invention.