US 4,486,715 AGrant

Frequency Shift Key Demodulator

Issue Date:1984-12-04

•16 Claims

•3 Drawing Sheets

Abstract

A frequency shift key demodulator produces an output data stream based upon whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a reference (REF) signal. The demodulator includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The demodulator also includes first and second sequence detectors, first and second integrating shift registers, and a decision circuit. The first sequence detector provides an output signal to the first shift register indicating that the FSK signal has a frequency less than the REF signal based upon detection of a first predetermined sequence of the code from the sequence generator. Similarly, the second sequence detector senses a second predetermined sequence of the code indicating that the FSK signal has a frequency greater than the REF signal and provides an output signal to the second shift register. At the end of a predetermined time period, the decision circuit compares the content of the first and second shift registers and produces an output bit of the data stream.

Metadata

Assignee

Honeywell Inc.

Inventors

Michael F. Maas
Max S. Hendrickson

Application Information

Application Number:US 4049551

Filing Date:1982-08-04

Priority Date:1982-08-04

Art Unit:252

Classifications

IPC:

H03D 1300H04L 2714H03K 906

Field of Search:

32937530732850;107;11088;94525;526133;134

Patent Drawings (3 sheets)

Description

BACKGROUND OF THE INVENTION

Reference To Copending Application

Reference is hereby made to a copending application by Michael F. Maas, Ser. No. 404,959, entitled "Phase Velocity Sign Detector For Frequency Shift Key Demodulation" which was filed on even date with the present application and is assigned to the same assignee.

1. Field of the Invention

The present invention relates to circuitry for detecting deviation in frequency of an input signal with respect to a reference signal. In particular, the present invention relates to digital circuitry for demodulating frequency shift key data transmissions.

2. Description of the Prior Art

With the ever-increasing use of digital computers and other digital electronic circuitry, the transmission of digital data has become extremely important. One digital data transmission format which has been utilized is frequency shift key (FSK) transmission. An FSK transmitter modulates a reference frequency signal based upon the data to be transmitted so that the transmitted signal has a frequency (f.sub.FSK) which is either slightly greater than or slightly less than the frequency (f.sub.0) of the reference signal (i.e. f.sub.FSK =f.sub.0 .+-..DELTA.f). The frequency of the transmitted FSK signal, therefore, represents either a digital "1" or a digital "0". An FSK receiver receives and demodulates the transmitted FSK signal to produce a serial data stream based upon the frequency of the FSK signal representing each bit of the data stream.

Narrow band FSK transmission, in which the frequency deviation of the FSK modulated signal from the reference or center frequency is very small, offers significant advantages. Because the FSK modulated signal is present only within a narrow frequency band, the narrow band FSK receiver can use a very high Q filter to remove all noise contained in the frequency spectrum except for the narrow band containing the FSK signal. High noise immunity, therefore, can be achieved by using narrow band FSK transmission.

There is a continuing need for improved FSK receiver circuitry which is capable of detecting narrow deviation in frequencies of the input signal with respect to a reference frequency, which requires short operating times, and which has good noise immunity. In addition, due to the ever increasing use of integrated circuits, there is need for FSK receiver circuitry which utilizes a minimum of components and which is completely integrable on a monolithic integrated circuit chip.

SUMMARY OF THE INVENTION

The present invention is a circuit for detecting differences in frequency between an input signal (FSK) and a reference signal (REF). The circuit includes sequence generator means for producing a digital code representative of a phase angle between the FSK and REF signals. The digital code (which is preferably a two bit binary code) changes in a first predetermined sequence when the frequency of the FSK signal is less than the frequency of the REF signal, and changes in a second predetermined sequence when the frequency of the FSK signal is greater than the frequency of the REF signal.

The circuit includes first sequence detector means for detecting the occurrence of the first predetermined sequence, and second sequence detector means for detecting the occurrence of the second predetermined sequence. Each time one of the sequence detector means provides an output indicating that its selected sequence has been detected, it is reset to begin another sequence detection cycle. The outputs from the first and second sequence detector means during a predetermined period are loaded into first and second integrating shift register means. At the end of the predetermined period, decision means compares the contents of the first and second integrating shift register means, and provides a data output based upon the contents of the first and second integrating shift register means. In this way, the sequence which was detected the most times during the period determines the data output from the decision means.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the FSK demodulator circuit of the present invention.

FIG. 2A shows the phase relationship between the REF and FSK signals, and the two bit binary code produced when the frequency of FSK is less than the frequency of REF.

FIG. 2B shows the phase relationship between the REF and FSK signals, and the two bit binary code generated when the frequency of FSK is greater than the frequency of REF.

FIG. 3A is a phase diagram showing the phase angle between REF and FSK when the frequency of FSK is less than the frequency of REF.

FIG. 3B is a phase diagram showing a phase relationship between FSK and REF when the frequency of FSK is greater than the frequency of REF.

FIG. 4 is an electrical block diagram showing a preferred embodiment of the sequence generator and sequence detectors of the circuit of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a frequency shift key receiver/demodulator which converts an FSK input signal to a digital data stream. The FSK signal is a squarewave signal having a frequency which represents the state of one bit of transmitted data. When f.sub.FSK =f.sub.0 +.DELTA.f, where f.sub.0 is a reference frequency, the data bit is a "1". When, on the other hand, f.sub.FSK =f.sub.0 -.DELTA.f, the FSK signal represents a digital "0".

The FSK signal is received at one input of sequence generator 10. Reference signal source 12 provides a REF signal which has the reference frequency f.sub.0. In a preferred embodiment of the present invention, the FSK signal has a fifty percent duty cycle, while the REF signal is a squarewave signal having a twenty-five percent duty cycle.

Sequence generator 10 latches the state of the FSK signal on the rising and falling edges of the REF signal to produce a two bit binary code. The first bit (Q1) corresponds to the state of the FSK signal on the rising edge of the REF signal, while the second bit (Q2) corresponds to the state of the FSK signal when the falling edge of the REF signal occurs. The two bit binary code generated by sequence generator 10 is a function of the phase angle between the FSK and REF signals. Because the frequencies of the FSK and REF signals are different, the phase angle between the FSK and REF signals will change with time. As a result, the two bit binary code will change in one of two known sequences, depending upon whether f.sub.FSK is greater than or less than f.sub.0. These sequences indicate the sign of the phase velocity between the FSK and REF signals. By detecting the sequence, it is possible to determine the sign of the phase velocity, and thus provide an indication of whether the FSK signal represents a "1" or a "0".

In the embodiment shown in FIG. 1, a pair of sequence detectors 14 and 16 each receive the two bit binary code. Sequence detector 14 detects the sequence which indicates that f.sub.FSK is less than f.sub.0, while sequence detector 16 detects the sequence which indicates that f.sub.FSK is greater than f.sub.0. Both sequence detectors 14 and 16 receive the Q1 and Q2 signals, together with their respective complementary signals (Q1 and Q2).

When sequence detector 14 detects its predetermined sequence, its output goes high. The output of sequence detector 14 is supplied to the D input of flipflop 18. Flipflop 18 receives the CLK signal at its clock (C) input. The CLK signal has the same frequency as the REF signal, but is shifted in phase. The Q output of flipflop 18 is supplied through OR gate 20 to the reset (R) input of sequence detector 14, thus causing sequence detector 14 to be reset each time that it detects a sequence. The output of flipflop 18 is also supplied to integrating shift register 22. Each time a sequence is detected by sequence detector 14, the output of flipflop 18 goes high for one pulse of the CLK signal (until sequence detector 14 is reset). Integrating shift register 22 accumulates the number of times that sequence detector 14 detects the presence of a sequence.

Similarly, the output of sequence detector 16 goes high when it detects its predetermined sequence. The output of sequence detector 16 is supplied to the D input of flipflop 24. The CLK signal is supplied to the clock (C) input of flipflop 24, and the Q output of flipflop 24 is supplied to OR gate 26 and integrating shift register 28. When sequence detector 16 detects a sequence, it is reset through flipflop 24 and OR gate 26. The number of times that sequence detector 16 detects a sequence is accumulated by integrating shift register 28.

The FSK signal has a predetermined baud rate, which determines the time period during which integrating shift registers 22 and 28 accumulate output signals from sequence detectors 14 and 16. For example, in one embodiment in which the baud rate is 360 Hz, the time period for detecting sequences and accumulating them in shift registers 22 and 28 is 1/360th of a second. Auto zero circuit 30 provides signals to sequence generator 10, sequence detector 14 (through OR gate 20), sequence detector 16 (through OR gate 26), integrating shift registers 22 and 28, and decision circuit 32 at the end of each time period. These signals from auto zero circuit 30 cause decision circuit 32 to provide an output data bit which is a "1" if integrating shift register 28 contains the larger count, and which is a "0" if integrating shift register 22 contains the larger count. The signal from the auto zero circuit 30 resets sequence generator 10, sequence detectors 14 and 16, and integrating shift registers 22 and 28 so that the next bit represented by the FSK signal can be detected.

The use of two sequence detectors 14 and 16 and two parallel integrating shift registers 22 and 28 permits an accurate demodulation of the FSK signal into the digital data stream without requiring auto zero circuit 30 to be precisely synchronized to the FSK signal.

FIGS. 2A, 2B, 3A and 3B illustrate the operation of sequence generator 10, which produces a two bit binary code which indicates the phase angle between the FSK and REF signals. The sequential change of the two bit binary code provides an indication of the sign of the phase angle from which it is possible (by means of sequence detectors 14 and 16) to determine whether f.sub.FSK is greater than or less than f .

In FIG. 2A, the REF and FSK signals are shown for the case where f.sub.FSK is less than f.sub.0. Also shown are the values of Q1 and Q2 (i.e. the two bit binary code) generated by sequence generator 10.

As shown in FIG. 2A, the Q1 bit represents the state of the FSK signal at the occurrence of the rising edge of the REF signal. The Q2 bit represents the state of the FSK signal at the occurrence of the trailing edge of the REF signal.

In the example shown in FIG. 2A, the FSK signal is initially high at both the leading and trailing edges of the REF signal, so that both Q1 and Q2 are "1" and the two bit binary code is "11". Because f.sub.FSK is less than f.sub.0, the period of the FSK signal is greater than the period of the REF signal. Thus the leading edge of the FSK signal gradually shifts to the right with respect to the leading edge of the REF signal. As shown in FIG. 2A, the rising edge of the FSK signal eventually shifts to the right of the rising edge of the REF signal and the two bit binary code changes to "01".

As time further progresses, the longer period of the FSK signal causes the binary code to shift from "01" to "00" and then from "00" to "10". As time further progresses, the phase angle between the FSK and REF signals continues to shift until the two bit binary code changes from "10" back to "11". This sequence continues as long as f.sub.FSK is less than f.sub.0.

FIG. 2B illustrates the REF and FSK signals and the two bit binary code generated when f.sub.FSK is greater than f.sub.0. In this latter case, the period of the FSK signal is slightly less than the period of the REF signal, so that the rising edge of the FSK signal shifts gradually to the left with respect to the rising edge of the REF signal. As a result, the two bit binary code changes from "11" to "10", then to "00", then to "01", and finally back to "11".

The time required to complete one cycle of either the sequence shown in FIG. 2A or the sequence shown in FIG. 2B is equal to one period of the difference frequency .DELTA.f, (where f.sub.FSK =f.sub.0 .+-..DELTA.f).

FIGS. 3A and 3B show the phase angle between the FSK and REF signals for the two cases illustrated in FIGS. 2A and 2B, respectively. As shown in FIGS. 3A and 3B, the binary code "11" represents the phase angle from 0.degree. to 90.degree.; the binary code "10" represents the phase angle from 90.degree. to 180.degree.; the binary code "00" represents the phase angle from 180.degree. to 270.degree.; and the binary code "01" represents the phase angle from 270.degree. to 360.degree. (or 0.degree.). The sequence illustrated in FIG. 2A is depicted in FIG. 3A as a clockwise rotation of the phase angle, while the sequence illustrated in FIG. 2B is depicted in FIG. 3B as a counterclockwise rotation of the phase angle.

The use of a fifty percent duty cycle FSK signal and a 25 percent duty cycle REF signal allows the four values of the binary code to each represent 90.degree. of the phase angle. If the duty cycle of the REF signal is greater than 25 percent, the "11" and "00" values of the code represent less than 90.degree., while the "10" and "01" values represent greater than 90.degree.. This means that the correspondence between the two bit binary code sequence and phase angle has become skewed. Although the present invention is still effective even though the sequence is skewed with respect to phase angle, the use of an REF signal which has a duty cycle of 25 percent and an FSK signal with a duty cycle of 50 percent is preferred, since skewing is avoided.

FIG. 4 shows the construction of sequence generator 10 and sequence detectors 14 and 16 in a preferred embodiment of the present invention. As shown in FIG. 4, sequence generator 10 is formed by a pair of flipflops 32 and 34 and inverter 36. The FSK signal is supplied to the D inputs of flipflops 32 and 34. The REF signal is supplied to the clock (C) input of flipflop 32, and is supplied through inverter 36 to the clock (C) input of flipflop 34. Flipflop 32 generates the Q1 and Q1 values, while flipflop 34 generates the Q2 and Q2 output values. The Q1 output of flipflop 32 corresponds to the state of the FSK signal supplied to the D input of flipflop 32 upon the occurrence of the rising edge of the REF signal. The Q2 output of flipflop 34 corresponds to the value of the FSK signal at the D input of flipflop 34 at the trailing edge of the REF signal (due to the inversion of the REF signal by inverter 36.)

Sequence detector 14 detects the sequence illustrated in FIGS. 2A and 3A. As shown in FIG. 4, sequence detector 14 includes flipflops 38, 40, 42, and 44 and NOR gate 46. Sequence detector 14 receives the Q1, Q1, Q2, and Q2 signals, as well as a reset signal from OR gate 20 (FIG. 1), and provides an output to flipflop 18 which is a digital "1" when the sequence illustrated in FIGS. 2A and 3A is detected. Unless the desired sequence occurs, the output of sequence detector 14 remains "0". The Q3, Q4, Q5, and Q6 outputs of flipflops 38, 40, 42 and 44, respectively, are supplied to NOR gate 46. The output of NOR gate 46 goes high ("1"), indicating the detection of a sequence only when all four inputs (Q3-Q6) are low. If any one of the four inputs Q3-Q6 is high, the output of NOR gate 46, and thus the output of sequence detector 14 remains low ("0").

Each one of the flipflops 38, 40, 42 and 44 detects one of the four transitions of the clockwise sequence of the two bit binary code. Flipflop 38 detects the "11" to "01" transition. Flipflop 40 detects the "10" to "11" transition. Flipflop 42 detects the "00" to "10" transition. Flipflop 44 detects the "01" to "00" transition.

Flipflop 38 receives Q2 at its D input and Q1 at its C input. The Q3 output of flipflop 38 is latched "0" when a "11" to "01" transition occurs.

Flipflop 40 receives Q1 at its D input and Q2 at its C input. The Q4 output of flipflop 40 is latched "0" when a "10" to "11" transition occurs.

Flipflop 42 receives Q2 at its D input and Q1 at its C input. The Q5 output of flipflop 42 is latched "0" when a "00" to "10" transition occurs.

Flipflop 44 receives Q1 at its D input and and Q2 at its C input. The Q6 output of flipflop 44 is latched "0" when a "01" to "00" transition occurs.

To illustrate the operation of sequence detector 14, consider the example shown in FIG. 2A when auto zero circuit 30 provides a reset signal which resets sequence generator 10 as well as sequence detectors 14 and 16. The reset signal is supplied to the reset inputs of flipflops 38, 40, 42, and 44, thus causing Q3-Q6 to all be "1". NOR gate 46 is, therefore, "disabled" (i.e. its output is "0") four times over. The auto zero reset signal also resets flipflops 32 and 34 of sequence generator 10, so that Q1 and Q2 are both "0" and the two bit binary code is "00". In this example, as soon as the auto zero reset is removed from sequence generator 10, Q1 changes from 0 to 1, and then Q2 changes from 0 to 1, since the first binary code in the sequence shown in FIG. 2A is "11".

Because Q1 changes to "1" first, while Q2 is still "0", flipflop 42 is initially latched, and Q5 goes low. As soon as Q2 changes to "1", flipflop 40 detects the "10" to "11" transition and Q4 latches to a "0". At this time, NOR gate 46 still remains disabled due to Q3 and Q6 still being "1".

After the binary code remains "11" for a period of time, a transition occurs from "11" to "01". This transition is detected by flipflop 38, and Q3 is latched as "0". NOR gate 46 still remains disabled due to Q6 being "1".

The next transition of the sequence occurs when the binary code changes from "01" to "00". This transition is detected by flipflop 44, which causes Q6 to be "0". At this time, all four inputs Q3-Q6 are "0", and the output of NOR gate 46 switches to "1", indicating that the clockwise sequence has been detected. The "1" output of sequence detector 14 is supplied to flipflop 18 of FIG. 1, which is clocked by the CLK signal to supply a "1" to integrating shift register 22, and to supply a reset signal through OR gate 20 to the reset inputs of flipflops 38, 40, 42 and 44. This causes the output of NOR gate 46 to return to "0", and the sequence detection process is restarted.

It can be seen that sequence detector 14 provides a "1" output whenever the clockwise sequence is present. This occurs regardless of where the sequence starts (i.e. it does not have to start with "11" as in this example in order to be detected). The clockwise sequence will be detected by sequence detector 14 regardless of where the sequence starts within one cycle of the difference frequency .DELTA.f.

Sequence detector 14 will not provide a "1" output when the counterclockwise sequence illustrated in FIGS. 2B and 3B is presented. Assuming once again that auto zero circuit 30 has supplied an auto zero reset to sequence generator 10 and sequence detector 14, the binary code is initially "00" and the output of NOR gate 46 is "0", since Q3-Q6 are all "1".

As soon as the auto zero reset is removed, Q1 changes to "1", which causes Q5 to be latched to "0". Q2 then changes to "1" which is detected by flipflop 40 as a "10" to "11" transition, and Q4 is latched to "0". NOR gate 46 remains disabled, however, due to Q3 and Q6 being "1".

The next transition shown in FIGS. 2B and 3B is from "11" to "10". This transition causes flipflop 44 to be latched, since Q2 switches from "0" to "1". The D input to flipflop 44 is Q1, which is "0". Q6, therefore, is latched "1", which maintains NOR gate 46 disabled.

The next transition of the counterclockwise sequence shown in FIGS. 2B and 3B is from "10" to "0O". This transition causes flipflop 38 to be clocked by the change of Q1 from "0" to "1". Since Q2 is "0", the Q3 output of flipflop 38 is latched "1", which provides a further disable to NOR gate 46.

The next transition in the counterclockwise sequence of FIGS. 2B and 3B is from "00" to "01". This transition causes flipflop 40 to be clocked. Since Q1 supplied to the D input of flipflop 40 is "01", the Q4 output of flipflop 40, (which had been previously latched as "0") is switched to "1". NOR gate 46 is now disabled three times over by Q3, Q4 and Q6 all being "1".

The next transition of the counterclockwise sequence is from "01" to "11". This transition causes flipflop 42 to be clocked. Since Q2 supplied to the D input of flipflop 42 is "0", the Q5 output of flipflop 42 (which had initially been latched "0" immediately after the auto zero reset had been removed) switches to "1". All four inputs to NOR gate 46 are now "1", and NOR gate 46 is disabled four times over. As the counterclockwise sequence continues, flipflops 38, 40, 42, and 44 continue to remain in states which leave Q3-Q6 latched as "1". Thus the output of sequence detector 14 remains "0" as long as the counterclockwise sequence is present.

Sequence detector 16 is similar in construction to sequence detector 14, except that it provides a "1" output when the counterclockwise sequence is present, and provides a "0" output when the clockwise sequence is present. Sequence detector 16 includes flipflops 48, 50, 52, and 54 and NOR gate 56. Flipflop 48 receives Q2 at its D input and Q1 at its C input. The Q7 output of flipflop 48 is latched "0" when a "01" to "11" transition occurs.

Flipflop 50 receives Q1 at its D input and Q2 at its C input. The Q8 output of flipflop 50 is latched "0" when a "11" to "10" transition occurs.

Flipflop 52 receives Q1 at its D input and Q1 at its C input. The Q9 output of flipflop 52 is latched "0" upon the occurrence of a "10" to "00" transition.

Flipflop 54 receives Q1 at its D input and Q2 at its C input. The Q10 output of flipflop 54 is latched "0" upon the occurrence of a "00" to "01" transition.

The Q7-Q10 outputs of flipflops 48, 50, 52 and 54 are supplied to the inputs of NOR gate 56. Only when Q7-Q10 are all "0" will the output of NOR gate 56 (and therefore the output of sequence detector 16) be "1". A reset signal is supplied to the reset inputs of flipflops 48, 50, 52, and 54 through OR gate 26 (FIG. 1). Whenever the output of NOR gate 56 changes to "1", flipflop 24 supplies a "1" to integrating shift register 28, and supplies a reset pulse through OR gate 26 to flipflops 48, 50, 52 and 54. Thus sequence detector 16 is reset each time that it detects the counterclockwise sequence, so that the detection process can start again. Flipflops 48, 50, 52 and 54 are also reset by auto zero circuit 30 through OR gate 26. This initializes the stages of flipflops 48, 50, 52 and 54 at the beginning of each detection.

As has been described in detail with regard to sequence detector 14, the flipflops of sequence detector 16 will all ultimately latch Q7-Q10 to "0" when the counterclockwise sequence shown in FIG. 2B and 3B is present. If, on the other hand, the clockwise sequence of FIGS. 2A and 3A is present, the Q7-Q10 outputs will eventually all be latched "1", and NOR gate 56 will be disabled. Just as is the case with sequence detector 14, the discontinuity created when the auto zero reset is initially removed can cause one or two of the four flipflops of sequence detector 16 to be temporarily latched with a "0" output, but by the end of one period of the difference frequency .DELTA.f, all four outputs of flipflops 48, 50, 52 and 54 will be latched "1" if the clockwise sequence is present, and will be latched "0" if the counterclockwise sequence is present.

The sequence detection provided by the present invention has several important features. First, exactly one period of the difference frequency .DELTA.f will result in a determintion of whether f.sub.FSK is greater than or less than f.sub.0, regardless of where in the sequence the sequence detection begins.

Second, one flipflop is used for each transition of the sequence. Transitions which occur in the correct order cause all four flipflops to latch so that the output of the sequence detector 14 or 16 is switched to "1" to indicate successful detection of the sequence.

Third, by gating data with the appropriate combination of one bit which has changed and the other bit which has not changed, spurious edges in the outputs of sequence generator 10 due to noise cause at least one of the flipflops to be latched with a "1" output. This inhibits a false "1" output of the sequence detectors 14 and 16 from occurring due to noise.

The circuit of the present invention provides high noise immunity. The circuit is useful over a broad range of FSK deviation. Ratios of f.sub.FSK to f.sub.0 of approximately 0.7 to approximately 1.3 are possible with the circuit of the present invention. The limit to the extent of f.sub.FSK deviation is the point at which the phase velocity between the FSK and REF signals is too fast to guarantee that each of the four two bit code values of the sequence will be sampled.

Although the circuit of the present invention is useful over a broad range of FSK deviation, it is particularly useful for narrow band FSK transmission, where the deviation (i.e. .DELTA.f) is very small. With the circuit of the present invention, no minimum deviation is required within the context of the circuit's ability to discriminate between f.sub.FSK greater than or less than f.sub.0. All that is required is that .DELTA.f be greater than zero (i.e. that some deviation exists).

The demodulation of FSK signals with the circuit of the present invention is done totally in the digital domain. No analog integration is required as part of the circuitry which converts the FSK signal to a digital data stream.

The circuit of the present invention uses a minimum of digital circuitry, all of which is completely integrable on a monolithic integrated circuit chip.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims

What is claimed is:

1. A circuit for determining whether an input signal has a frequency greater than or less than a reference signal, the circuit comprising: means for producing a digital code as a function of the input and reference signals, the digital code being representative of a phase angle between the input and reference signals and changing in a first predetermined sequence when the frequency of the input signal is less than the frequency of the reference signal and changing in a second predetermined sequence when the frequency of the input signal is greater than the frequency of the reference signal; first sequence detector means for receiving the digital code and providing a signal when the first predetermined sequence is detected; second sequence detector means for receiving the digital code and providing a signal when the second predetermined sequence is detected; and means for providing an output as a function of signals from the first and second sequence detector means, the output indicating whether the input signal has a frequency greater than or less than the reference signal.

2. The circuit of claim 1 wherein the means for providing an output comprises: first reset means for resetting the first sequence detector means each time the first predetermined sequence is detected; first accumulating means for accumulating the number of times the first predetermined sequence is detected by the first sequence detector means during a predetermined interval; second reset means for resetting the second sequence detector means each time the second predetermined sequence is detected; second accumulating means for accumulating the number of times the second predetermined sequence is detected by the second sequence detector means during the predetermined interval; and decision means for providing the output as a function of the number of sequences detected by the first and second sequence detector means during the predetermined interval.

3. The circuit of claim 2 wherein the first and second accumulating means comprise first and second integrating shift registers, respectively.

4. The circuit of claim 1 wherein the digital code is a multibit binary code.

5. The circuit of claim 4 wherein the digital code is a two bit binary code.

6. The circuit of claim 1 wherein the means for producing a digital code comprises: means for providing a first bit of the digital code as a function of a state of one of the input and reference signals when the other signal changes from a first to a second state; and means for providing a second bit of the digital code as a function of the state of the one signal when the other signal changes from the second state to the first state.

7. The circuit of claim 1 wherein the first sequence detector means comprises means for sensing each of a plurality of predetermined transitions of the digital code indicative of the first predetermined sequence, and means for providing the signal when all of the predetermined transitions indicative of the first predetermined sequence have been sensed; and wherein the second sequence detector means comprises means for sensing each of a plurality of predetermined transitions of the digital code indicative of the second sequence, and means for providing the signal when all of the predetermined transitions indicative of the second predetermined sequence have been sensed.

8. The circuit of claim 7 wherein the digital code is a two bit binary code, wherein the first predetermined sequence is "11" to "01" to "00" to "10" to "11" and so on, and wherein the second predetermined sequence is "11" to "10" to "00" to "01" to "11" and so on.

9. A circuit for converting a frequency shift key (FSK) signal to a digital data stream, the circuit comprising: sequence generator means for producing a digital code as a function of the FSK signal and a reference signal having a predetermined reference frequency, the digital code being representative of a phase angle between the FSK and reference signals and changing in a first predetermined sequence when the FSK signal has a frequency which is less than the reference frequency, and changing in a second predetermined sequence when the frequency of the FSK signal is greater than the reference frequency; first sequence detector means for receiving the digital code and providing a signal when the first predetermined sequence is detected; second sequence detector means for receiving the digital code and providing a signal when the second predetermined sequence is detected; and means for producing the digital data stream as a function of signals from the first and second sequence detectors.

10. The circuit of claim 9 wherein the means for producing the digital data stream comprises: first reset means for resetting the first sequence detector means each time the first predetermined sequence is detected; first accumulating means for accumulating the number of times the first predetermined sequence is detected by the first sequence detector means during a predetermined interval; second reset means for resetting the second sequence detector means each time the second predetermined sequence is detected; second accumulating means for accumulating the number of times the second predetermined sequence is detected by the second sequence detector means during the predetermined interval; and decision means for providing the data stream as a function of the number of sequences detected by the first and second sequence detector means during the predetermined interval.

11. The circuit of claim 10 wherein the first and second accumulating means comprise first and second integrating shift registers, respectively.

12. The circuit of claim 9 wherein the digital code is a multibit binary code.

13. The circuit of claim 12 wherein the digital code is a two bit binary code.

14. The circuit of claim 9 wherein the sequence generator means comprises: means for providing a first bit of the digital code as a function of a state of one of the FSK and reference signals when the other signal changes from a first to a second state; and means for providing a second bit of the digital code as a function of the state of the one signal when the other signal changes from the second state to the first state.

15. The circuit of claim 9 wherein the first sequence detector means comprises means for sensing each of a plurality of predetermined transitions of the digital code indicative of the first predetermined sequence, and means for providing the signal when all of the predetermined transitions indicative of the first predetermined sequence have been sensed; and wherein the second sequence detector means comprises means for sensing each of a plurality of predetermined transitions of the digital code indicative of the second sequence, and means for providing the signal when all of the predetermined transitions indicative of the second predetermined sequence have been sensed.

16. The circuit of claim 15 wherein the digital code is a two bit binary code and wherein the first predetermined sequence is "11" to "01" to "00" to "10" to "11" and so on, and wherein the second predetermined sequence is "11" to "10" to "00" to "01" to "11" and so on.

Patent Citations (3)

Patent	Date	Inventor
US4264866	1981-04-01	Benes
SUX746862	1980-07-01
SUX783972	1980-11-01

Abstract

Description