Signal Processing Network for an Automatic Kinescope Bias Control System

This invention concerns a signal processing arrangement employed in a system for automatically controlling the level of black image representative current conducted by a video signal image display device such as the kinescope of a television receiver.

Television receivers sometimes employ an automatic kinescope bias (AKB) control system for automatically establishing proper black image representative current levels for each electron gun of the kinescope. As a result of this operation, pictures reproduced by the kinescope are prevented from being adversely affected by variations of kinescope operating parameters (e.g., due to aging and temperature effects). One type of AKB system is disclosed in U.S. Pat. No. 4,263,622 of Werner Hinn, titled "Automatic Kinescope Biasing System."

An AKB system typically operates during image blanking intervals, at which time the kinescope conducts a small black level representative blanking current in response to a reference voltage representative of black video signal information. This current is monitored by the AKB system to generate a kinescope bias correction voltage representing the difference between the sensed black current level and a desired black current level. The correction voltage is applied to the kinescope, such as via video signal processing circuits preceding the kinescope, with a sense for reducing the difference. Typically, the correction voltage is applied to a bias control input of a DC coupled kinescope driver amplifier which supplies video output signals of a level suitable for directly driving a cathode intensity control electrode of the kinescope. The correction voltage modifies the output bias voltage of the driver amplifier, thereby modifying the cathode bias voltage, such that the desired cathode black current level results.

In an AKB system of the type described in the aforementioned Hinn patent, control circuits respond to a periodically developed voltage pulse with a magnitude representative of the cathode black current level. The voltage pulse exhibits a prescribed level other than zero when the black current level is correct, and different levels (e.g., more or less positive) when the black current level is too high or too low. The voltage pulse is sampled by a sampling amplifier which charges or discharges a storage capacitor in accordance with the level of the voltage pulse. The kinescope bias correction voltage is derived from the charge stored by the storage capacitor, which increases or decreases as required to maintain a correct black current level.

The bias correction voltage derived from the storage capacitor should remain unchanged when the level of the voltage pulse represents a correct black current level. This requires that the storage capacitor be neither charged nor discharged by output current from the sampling amplifier when the level of the voltage pulse represents a correct black current level. More specifically, in an AKB system of the type described in the Hinn patent, this requires that the sampling amplifier supply no current to the storage capacitor when correct kinescope black level current is indicated by a representative voltage pulse with a predetermined magnitude other than zero. This result can be accomplished by offsetting the bias of the sampling amplifier such as by means of a pre-set, manually adjustable potentiometer coupled to an.appropriate bias control point of the amplifier.

It is herein recognized that such manual pre-set adjustments are undesirable in an otherwise automatic signal control system. Furthermore, such manual adjustments are undesirably time consuming, and the associated potentiometers add unwanted cost to the system.

It is also noted that the signal processing techniques employed by some AKB systems can produce an offset error if the cut-off voltages and signal gains of the individual kinescope electron guns are not identical, due to kinescope manufacturing tolerances, for example. In such case the black current level established by the AKB system can exhibit an error which can be compensated for by means of pre-set manually adjustable potentiometers. The disclosed arrangement advantageously facilitiates the design of AKB signal processing circuits which do not require manually adjustable controls for the purpose of compensating for such offset errors.

The present invention concerns a video signal processing system wherein a derived signal representative of the black current level conducted by an image display device has a given amplitude other than zero when the black current level is correct. The derived representative signal is applied via an input signal coupling path to a sampling amplifier which supplies an output current for charging and discharging a charge storage device in accordance with the amplitude of the derived signal. In accordance with a principle of the present invention, an auxiliary signal is applied to the input signal coupling path with a magnitude and sense for negating the amplitude of the derived signal at the amplifier input when the amplitude of the derived signal is representative of a correct black current level. Accordingly, the conduction of the sampling amplifier remains unchanged when the derived pulse amplitude corresponds to the correct black current level, and the voltage on the storage device remains unchanged.

In accordance with a feature.of the invention, the magnitude of the auxiliary signal is proportional to the magnitude of the cut-off potential of the kinescope cathode developed during the AKB interval.

In accordance with another feature of the invention, the input of the sampling amplifier is clamped to a reference voltage during a clamping interval preceding the signal sampling interval. The black level representative derived signal is developed during the clamping interval so that the reference voltage to which the amplifier input is clamped during the clamping interval is a function of the magnitude of the derived signal, and the auxiliary signal is developed during the following sampling interval. The auxiliary signal exhibits a magnitude and sense for maintaining the amplifier input voltage substantially unchanged when the magnitude of the derived signal corresponds to the correct black current level.

In accordance with a further feature of the invention, the amplifier input is clamped to a reference voltage during the clamping interval, and the derived signal and the auxiliary signal are both developed during the sampling interval.

In the drawing:

FIG. 1 shows a portion of a color television receiver including an AKB system and an associated signal sampling network incorporating the principles of the present invention;

FIG. 2 illustrates signal waveforms associated with the operation of the system in FIG. 1;

FIG. 3 depicts an alternative version of signal waveforms shown in FIG. 2;

FIG. 4 shows circuit details of the sampling network in FIG. 1; and

FIG. 5 shows circuit details of a timing signal generator associated with the system of FIG. 1.

In FIG. 1, television signal processing circuits 10 provide separated luminance (Y) and chrominance (C) components of a composite color television signal to a luminance-chrominance signal processing network 12. Processor 12 includes luminance and chrominance gain control circuits, DC level setting circuits (e.g., comprising keyed black level clamping circuits), color demodulators for developing r-y, g-y and b-y color difference signals, and matrix amplifiers for combining the latter signals with processed luminance signals to provide low level color image representative signals r, g and b. These signals are amplified and otherwise processed by circuits within video output signal processing networks 14a, 14b and 14c, respectively, which supply high level amplified color image signals R, G and B to respective cathode intensity control electrodes 16a, 16b and 16c of a color kinescope 15. Networks 14a, 14b and 14c also perform functions related to the AKB operation, as will be discussed. Kinescope 15 is of the self-converging in-line gun type with a commonly energized grid 18 associated with each of the electron guns comprising cathode electrodes 16a, 16b and 16c.

Since output signal processors 14a, 14b and 14c are similar in this embodiment, the following discussion of the operation of processor 14a also applies to processors 14b and 14c.

Processor 14a includes a kinescope driver stage comprising an input common emitter transistor 20 which receives video signal r from processor 12 via an input resistor 21, and an output high voltage common base transistor 22 which together with transistor 20 forms a cascode video driver amplifier. High level video signal R, suitable for driving kinescope cathode 16a, is developed across a load resistor 24 in the collector output circuit of transistor 22. An operating supply voltage for amplifier 20, 22 is provided by a source of high DC voltage, B+ (e.g., +230 volts). Direct current negative feedback for driver 20, 22 is provided by means of a resistor 25. The signal gain of cascode amplifier 20, 22 is primarily determined by the ratio of the value of feedback resistor 25 to the value of input resistor 21. The feedback network provides a suitably low amplifier output impedance, and assists to stabilize the DC operating level at the amplifier output.

A sensing resistor 30 DC coupled in series with and between the collector-emitter paths of transistors 20, 22 serves to develop a voltage at a relatively low voltage node A representing the level of kinescope cathode black current conducted during kinescope blanking intervals. Resistor 30 functions in conjunction with the AKB system of the receiver, which will now be described.

A timing signal generator 40 containing logic control circuits responds to periodic horizontal synchronizing rate signals (H) and to periodic vertical synchronizing rate signals (V), both derived from deflection circuits of the receiver, for generating timing signals V.sub.B, V.sub.S, V.sub.C, V.sub.P and V.sub.G which control the operation of the AKB function during periodic AKB intervals. Each AKB interval begins shortly after the end of the vertical retrace interval within the vertical blanking interval, and encompasses several horizontal line intervals also within the vertical blanking interval and during which video signal image information is absent. These timing signals are illustrated by the waveforms in FIG. 2.

Referring to FIG. 2 for the moment, timing signal V.sub.B, a video blanking signal, comprises a positive pulse generated soon after the vertical retrace interval ends at time T.sub.1, as indicated by reference to signal waveform V. Blanking signal V.sub.B exists for the duration of the AKB interval and is applied to a blanking control input terminal of luminance-chrominance processor 12 for causing the r, g and b outputs of processor 12 to exhibit a black image representative DC reference level corresponding to the absence of video signals. This can be accomplished by reducing the signal gain of processor 12 to substantially zero via the gain control circuits of processor 12 in response to signal V.sub.B, and by modifying the DC level of the video signal processing path via the DC level control circuits of processor12 to produce a black image representative reference level at the signal outputs of processor 12. Timing signal V.sub.G, a positive grid drive pulse, encompasses three horizontal line intervals within the vertical blanking interval. Timing signal V.sub.C controls the operation of a clamping circuit associated with the signal sampling function of the AKB system. Timing signal V.sub.S, a sampling control signal, occurs after signal V.sub.C and serves to time the operation of a sample and hold circuit which develops a DC bias control signal for controlling the kinescope cathode black current level. Signal V.sub.S encompasses a sampling interval the beginning of which is slightly delayed relative to the end of the clamping interval encompassed by signal V.sub.C, and the end of which substantially coincides with the end of the AKB interval. A negative-going auxiliary pulse V.sub.P, the function of which will be described in greater detail subsequently, coincides with the sampling interval. Signal timing delays T.sub.D indicated in FIG. 2 are on the order of 200 nanoseconds.

Referring again to FIG. 1, during the AKB interval positive pulse V.sub.G (e.g., on the order of +10 volts) forward biases grid 18 of the kinescope, thereby causing the electron gun comprising cathode 16a and grid 18 to increase conduction. At times other than the AKB intervals, signal V.sub.G provides the normal, less positive, bias for grid 18. In response to positive grid pulse V.sub.G, a similarly phased, positive current pulse appears at cathode 16a during the grid pulse interval. The amplitude of the cathode output current pulse so developed is proportional to the level of cathode black current conduction (typically a few microamperes).

The induced positive cathode output pulse appears at the collector of transistor 22, and is coupled to the base input of transistor 20 via resistor 25, causing the current conduction of transistor 20 to increase proportionally while the cathode pulse is present. The increased current conducted by transistor 20 causes a voltage to be developed across sensing resistor 30. This voltage is in the form of a negative-going voltage change which appears at sensing node A and which is proportional in magnitude to the magnitude of the black current representative cathode output pulse. The magnitude of the voltage change at node A is determined by the product of the value of resistor 30 times the magnitude of the current flowing through resistor 30.

The voltage change at node A is coupled via a small resistor 31 to a node B at which a voltage change V.sub.1, essentially corresponding to the voltage change at node A, is developed. Node B is coupled to a bias control voltage processing network 50. Network 50 includes an input coupling capacitor 51, an input clamping and sampling operational amplifier 52 (e.g., an operational transconductance amplifier) with an associated feedback switch 54 responsive to clamping timing signal V.sub.C, and a charge storage capacitor 56 with an associated switch 55 responsive to sampling timing signal V.sub.S. The voltage developed on capacitor 56 is used to supply a kinescope bias correction signal via network 58 and resistor network 60, 62, 64 to the kinescope driver via a bias control input at the base of transistor 20. Network 58 includes signal translating and buffer circuits for supplying the bias control voltage at a suitable level and low impedance in accordance with the bias control input requirements of transistor 20.

The operation of the system of FIG. 1 will now be discussed with specific reference to the waveforms of FIG. 2. Auxiliary signal V.sub.P is applied to circuit node B in FIG. 1 via a diode 35 and a voltage translating impedance network comprising resistors 32 and 34, e.g., with values of 220 kilohms and 270 kilohms, respectively. Signal V.sub.P exhibits a positive DC level of approximately +8.0 volts at all times except during the AKB sampling interval, for maintaining diode 35 conductive so that a normal DC bias voltage is developed at node B. When the positive DC component of signal V.sub.P is present, the junction of resistors 32 and 34 is clamped to a voltage equal to the positive DC component of signal V.sub.P, minus the voltage drop across diode 35. Signal V.sub.P manifests a negative-going, less positive fixed amplitude pulse component during the AKB sampling interval. Diode 35 is rendered non-conductive in response to negative pulse V.sub.P, causing both resistors 32 and 34 to be coupled between node B and ground. Resistor 31 causes insignificant attenuation of the voltage change developed at node A relative to the corresponding voltage change developed at node B since the value of resistor 31 (on the order of 200.OMEGA.) is small relative to the values of resistors 32 and 34.

Prior to the clamping interval, but during the AKB interval, the pre-existing nominal DC voltage (V.sub.NOM) appearing at node B charges the positive terminal of capacitor 51. During the clamping interval when grid drive pulse V.sub.G is developed, the voltage at node A decreases in response to pulse V.sub.G by an amount representative of the black current level. This causes the voltage at node B to decrease to a level substantially equal to V.sub.NOM -V.sub.1. Also during the clamping interval, timing signal V.sub.C causes clamping switch 54 to close (i.e., conduct) whereby the inverting (-) signal input of amplifier 52 is coupled to its output, thereby configuring amplifier 52 as a unity gain follower amplifier. As a result, a source of fixed DC reference voltage V.sub.REF (e.g., +5 volts) applied to a non-inverting input (+) of amplifier 52 is coupled by feedback action to the inverting signal input of amplifier 52 via the output of amplifier 52 and conductive switch 54. Thus during the clamping interval the voltage V.sub.3 across capacitor 51 is a function of a reference set-up voltage determined by voltage V.sub.REF at the negative terminal of capacitor 51, and a voltage at the positive terminal of capacitor 51 corresponding to the difference between the described pre-existing nominal DC level (V.sub.NOM) at node B and voltage change V.sub.1 developed at node B during the clamping interval. Thus voltage V.sub.3 across capacitor 51 during the clamping reference interval is a function of the level of black current representative voltage change V.sub.1, which may vary. Voltage V.sub.3 can be expressed as (V.sub.NOM -V.sub.1)-V.sub.REF.

During the immediately following sampling interval, positive grid drive pulse V.sub.G is absent, causing the voltage at node B to increase positively to the pre-existing nominal DC level V.sub.NOM that appeared prior to the clamping interval. Simultaneously, negative pulse V.sub.P appears, reverse biasing diode 35 and perturbing (i.e., momentarily changing) the normal voltage translating and coupling action of resistors 32, 34 such that the voltage at node B is reduced by an amount V.sub.2 as indicated in FIG. 2. At the same time, clamping switch 54 is rendered non-conductive and sampling switch 55 closes (conducts) in response to signal V.sub.S whereby charge storage capacitor 56 is coupled to the output of amplifier 52.

Thus during the sampling interval the input voltage applied to the inverting signal input (-) of amplifier 52 is equal to the difference between the voltage at node B, and voltage V.sub.3 across input capacitor 51. The input voltage applied to amplifier 52 is a function of the magnitude of voltage change V.sub.1, which can vary with changes in the kinescope black current level.

The voltage on output storage capacitor 56 remains unchanged during the sampling interval when the magnitude of voltage change V.sub.1 developed during the clamping interval equals the magnitude of voltage change V.sub.2 developed during the sampling interval, indicating a correct kinescope black current level. This results because during the sampling interval, voltage change V.sub.1 at node B increases in a positive direction (from the clamping set-up reference level) when the grid drive pulse is removed, and voltage change V.sub.2 causes a simultaneous negative-going voltage perturbation at node B. When kinescope bias is correct, positive-going voltage change V.sub.1 and negative-going voltage change V.sub.2 exhibit equal magnitudes whereby these voltage changes mutually cancel during the sampling interval, leaving the voltage at node B unchanged.

When the magnitude of voltage change V.sub.1 is less than the magnitude of voltage change V.sub.2, amplifier 52 proportionally charges storage capacitor 56 in a direction for increasing cathode black current conduction. Conversely, amplifier 52 proportionally discharges storage capacitor 56 for causing decreased cathode black current conduction when the magnitude of voltage change V.sub.1 is greater than the magnitude of voltage change V.sub.2.

As more specifically shown by the waveforms of FIG. 2, the amplitude "A" of voltage change V.sub.1 is assumed to be approximately three millivolts when the cathode black current level is correct, and varies over a range of a few millivolts (.+-..DELTA.) as the cathode black current level increases and decreases relative to the correct level as the operating parameters of the kinescope change. Thus the clamping interval set-up reference voltage across capacitor V.sub.3 varies with changes in the magnitude of voltage V.sub.1 as the cathode black current level changes. Voltage change V.sub.2 at node B exhibits an amplitude "A" of approximately three millivolts, which corresponds to amplitude "A" associated with voltage change V.sub.1 when the black current level is correct.

As indicated by waveform V.sub.COR in FIG. 2, the voltage at the inverting input of amplifier 52 remains unchanged during the sampling interval when voltages V.sub.1 and V.sub.2 are both of amplitude "A". However, as indicated by waveform V.sub.H, the input voltage of amplifier 52 increases by an amount .DELTA. when voltage change V.sub.1 exhibits amplitude "A+.DELTA.", corresponding to a high black current level. In this event amplifier 52 discharges output storage capacitor 56, so that the bias control voltage applied to the base of transistor 20 causes the collector voltage of transistor 22 to increase, whereby the cathode black current decreases towards the correct level.

Conversely, and as indicated by waveform V.sub.L, the input voltage of amplifier 52 decreases by an amount .DELTA. during the sampling interval when voltage change V.sub.1 exhibits amplitude "A-.DELTA.", corresponding to a low black current level. In this case amplifier 52 charges output storage capacitor 56, causing the collector voltage of transistor 22 to decrease whereby the cathode black current increases toward the correct level. In either case, several sampling intervals may be required to achieve the correct black current level.

The voltage developed at node B during the AKB clamping and sampling intervals is a function of the values of resistors 31, 32 and 34, and the value of an output impedance, Z.sub.o, appearing at node A. When signal V.sub.P manifests the positive DC level (+8 volts) during the clamping interval, the junction of resistors 32 and 34 is voltage clamped and a current conducted by resistor 31 from node A to node B is a function of the values of Z.sub.o, resistor 31 and resistor 34. During the subsequent sampling interval when the negative-going pulse component of signal V.sub.P is present, diode 35 is non-conductive and the junction of resistors 32 and 34 is unclamped. At this time a different current is conducted by resistor 31 from node A to node B as a function of the value of resistor 32, in addition to the values of Z.sub.o and resistors 31, 34. Voltage change V.sub.2 developed at node B in response to the negative-going pulse component of signal V.sub.P is proportional to the difference between these currents.

Impedance Z.sub.o at node A may vary undesirably as a function of the kinescope cathode bias level (i.e., cathode cut-off voltage level) associated with the expected correct cathode black current level. Resistor 31 compensates for variations in the value of impedance Z.sub.o, and also serves to increase the immunity of the clamping and sampling circuits of network 50 to locally generated spurious signals such as horizontal rate interference. These functional aspects of resistor 31 are discussed in a concurrently filed copending U.S. patent application (RCA Ser. No. 78,456) of J. C. Tallant, II, et al. titled "Automatic Kinescope Bias Control System Compensated for Sense Point Impedance Variations."

The disclosed system automatically produces a zero amplifier output current to storage capacitor 56 when the non-zero amplitude of voltage change V.sub.1 corresponds to the correct black current level. Accordingly, manual pre-set bias controls are not required for offsetting the sampling amplifier conduction response to produce a zero amplifier output current flow to the storage capacitor when the sampled signal exhibits a magnitude other than zero for correct bias conditions.

The described sampling amplifier input signal coupling arrangement employing auxiliary pulse V.sub.P is advantageous in a system wherein sampling amplifier 52 comprises a differential input amplifier, such as an emitter coupled differential amplifier as will be described subsequently in connection with FIG. 4. A differential amplifier of this type exhibits a symmetrical input-verus-output signal transfer response which is non-linear over much of its operating range. The otherwise symmetrical operating range of the differential amplifier can be rendered asymmetrical if the bias of the amplifier is offset by means of a manually adjustable pre-set bias control, for example. In such case the amplifier would be more likely to produce an output which is contaminated by the effects of noise and similar spurious signals, since the offset asymmetrical amplifier response can lead to rectification of the noise in the non-linear operating region of the amplifier. As a result, the output signal sample and the corresponding voltage developed on the output charge storage device would be distorted or obscured by the effects of rectified noise.

The described combined-pulse sampling arrangement also advantageously provides a convenient mechanism for compensating for mutually different conduction (gain) characteristics and correspondingly different cut-off voltages of the kinescope electron guns, due to kinescope manufacturing tolerances, for example. This aspect of the disclosed arrangement is discussed in detail in my copending concurrently filed U.S. patent application Ser. No. (RCA 78,859) titled "Automatic Kinescope Bias Control System Compensated for Kinescope Electron Gun Conduction Dissimilarities", and is discussed briefly below.

When the kinescope electron guns are identical and thereby exhibit the same conduction characteristics, they will conduct equal black level currents and exhibit equal cut-off voltages (i.e., grid-to-cathode voltage). In practice, however, the electron guns exhibit mutually different conduction characteristics. In the latter case the different currents conducted by the electron guns are considered to be the correct black level currents, whereby the AKB system should remain quiescent and should not alter the kinescope bias even though the electron guns exhibit mutually different black current levels and mutually different associated cut-off voltages.

This result is achieved by the disclosed arrangement since the magnitude of voltage change V.sub.2 developed at node B is linearly proportional to the DC voltage component appearing at node A. This DC voltage component is proportional to the cathode cut-off voltage as manifested by the DC voltage component at the output of driver transistor 22, corresponding to the cathode voltage, during the AKB interval (neglecting the effect of the induced cathode output current pulse developed in response to positive grid drive pulse V.sub.G). Thus if the three kinescope electron guns exhibit mutually different currents and cut-off voltages corresponding to initial black level set-up conditions, voltage change V.sub.2 respectively associated with signal processors 14a, 14b and 14c each exhibit different magnitudes, even though each is derived from a common signal V.sub.P. The different magnitudes of voltage changes V.sub.2 are a function of the different cut-off voltages as manifested by the DC components of different magnitudes developed at nodes A. The different magnitudes of voltage changes V.sub.2 are such that, for the associated AKB control loop, the voltage developed at node B does not change when voltage changes V.sub.1 and V.sub.2 are combined, so that each AKB control loop remains quiescent. The AKB control loops will remain quiescent until the initially established black level electron gun currents change due to a change in the operating parameters of the kinescope because of kinescope aging or temperature effects.

In some AKB systems it may be desirable to develop black current representative voltage change V.sub.1 during the sampling interval, rather than during the preceding clamping interval as described previously. In such an alternative system grid drive pulse V.sub.G would be timed to occur during the sampling interval, and signal timing relationships as shown by the waveforms of FIG. 3 can be employed. In such a system the timing of signals V, H, V.sub.B, V.sub.S and V.sub.C would remain unchanged.

Waveforms for the alternative system are shown in FIG. 3. A positive grid drive pulse V.sub.G and a positive auxiliary pulse V.sub.P are coincident during the sampling interval. During the initial clamping interval, the "set-up reference level" is a function of the DC voltage then appearing at nodes A and B. During the subsequent sampling interval, voltage change V.sub.1 exhibits an amplitude "A" when the black current level is correct, amplitude A+.DELTA. when the black current level is low, and amplitude A-.DELTA. when the black current level is high. Voltage change V.sub.1 is summed during the sampling interval with voltage change V.sub.2, of amplitude "A". Thus when the black current level is correct, voltage change V.sub.1 cancels with voltage change V.sub.2 since both then exhibit the same amplitude "A" but with opposite polarity. The voltage then applied to clamp capacitor 51 from node B is therefore the same as the reference level applied from node B during the prior clamping interval, whereby the input voltage of amplifier 52 does not change during the sampling interval, as indicated by signal waveform VCOR for the correct current condition. Thus storage capacitor 56 is neither charged nor discharged by output current from amplifier 52. For this alternative system, voltage change V.sub.2 can be developed at node B by selectively gating a voltage divided version of positive pulse V.sub.P to node B during the sampling intervals.

The clamping reference level developed during the clamping interval for conditions of low and high black current is the same as the clamping reference level developed when the black current level is correct. However, in the case of high black current, voltage changes V.sub.1 and V.sub.2 do not cancel completely during the sampling interval, and the input voltage of amplifier 52 increases by an amount .DELTA. during the sampling interval (waveform V.sub.H). Conversely, a condition of black current results in incomplete cancellation whereby the input voltage to amplifier 52 decreases by an amount A during the sampling interval (waveform V.sub.L).

FIG. 4 shows circuit details of signal clamping and sampling network 50 of FIG. 1, wherein corresponding elements are identified by the same reference number.

In FIG. 4, amplifier 52 is shown as comprising an operational transconductance amplifier wherein an output current is produced as a function of the product of the amplifier input voltage and the amplifier transconductance (g.sub.m) Amplifier 52 includes emitter coupled transistors 66, 68 arranged in an input differential amplifier configuration, and a current repeater ("mirror") network, including a diode connected transistor 71 and a transistor 74, arranged in the collector circuit of transistor 68 as shown. A first constant current source including a forward biased transistor 69 and a resistor R provides an operating current I for transistors 66 and 68. A second constant current source including a forward-biased transistor 75 and a resistor 2R provides an operating current I/2 for transistor 74. DC reference voltage source V.sub.REF is applied to the non-inverting input of amplifier 52 at the base of transistor 68. The input signal to be sampled (as derived from node B in FIG. 1) is applied via input capacitor 51 to the inverting input of amplifier 52 at the base of transistor 66.

During the AKB clamping interval, the collector of transistor 68 is coupled to input capacitor 51 via diode connected transistor 71, transistor 74, and conductive switch 54 to form a negative feedback current path. At this time, storage capacitor 56 is decoupled from amplifier 52 via non-conductive switch 55. Input capacitor 51 charges via currents conducted by transistors 68, 71 and 74, as a function of V.sub.REF and the potential then applied to the input of capacitor 51 from node B of FIG. 1, until the base voltages of transistors 66 and 68 are substantially equal (i.e., the differential input voltage of amplifier 52 is substantially zero). Current I sourced by transistor 69 then divides equally between transistors 66 and 68, whereby the collector currents of transistors 68 and 74 equal the collector current (I/2) conducted by transistor 75. Therefore all of the collector current conducted by transistor 74 flows as collector current in transistor 75. The described current feedback path settles to a zero current condition prior to the end of the clamping interval, at which time transistor 75 "sinks" all of the collector current of transistor 74 and zero feedback current flows to the base of input transistor 66.

During the subsequent AKB sampling interval when switch 54 is rendered non-conductive and switch 55 conducts to couple storage capacitor 56 to the output of amplifier 52, the pre-existing charge on capacitor 56 remains unchanged unless the input signal applied to capacitor 51 is sufficient to alter the balanced base bias of transistors 66, 68 as established during the preceding clamping interval. Thus when voltage change V.sub.1 exhibits amplitude "A", corresponding to a correct black level current condition, the voltage input to transistor 66 will remain unchanged as indicated by waveform V.sub.COR of FIG. 2. Accordingly, the balanced input bias of transistors 66, 68 and the charge on output storage capacitor 56 remain unchanged. When the black current level is incorrect such that the voltage input to transistor 66 is caused to increase as shown by waveform V.sub.H of FIG. 2, the currents conducted by transistors 68, 71 and 74 decrease whereby storage capacitor 56 is discharged via transistor 75 by an amount proportional to the decreased conduction of transistor 74 in response to the increased input voltage. In this case transistor 75 acts as a current sink with respect to discharging storage capacitor 56. Similarly, a decrease in the input voltage applied to transistor 66 (as indicated by waveform V.sub.L of FIG. 2) causes a corresponding increase in the collector current of output transistor 74. Storage capacitor 56 charges via transistor 74 in response to this increased current conduction, whereby the voltage on capacitor 56 increases. In this case transistor 74 acts as a current source for charging capacitor 56.

FIG. 5 shows a block diagram of a logic arrangement for timing signal generator 40 in FIG. 1. A binary counter 90 includes CLOCK and RESET inputs respectively responsive to horizontal signal H and vertical signal V, a DISABLE input, and binary outputs Q.sub.1 -Q.sub.4. Counter 90 is reset in response to the positive pulse portion of signal V which occurs during the vertical retrace interval, so that outputs Q.sub.1 -Q.sub.4 all exhibit a low logic level (0000) while the RESET input is positive during the vertical retrace interval. During this time counter 90 does not respond to horizontal rate clock pulses H.

A combinational logic array 92 (e.g., including a plurality of logic gates) monitors the binary states of the Q.sub.1 -Q.sub.4 outputs of counter 90 via inputs A-D. At the end of the vertical retrace interval at time T.sub.1, counter 90 is enabled to operate whereby the logic states of the outputs of counter 90 change to indicate a binary number corresponding to the number of clock pulses H occurring since the end of the vertical retrace interval.

A logic output F of array 92 produces a high ("1") logic level during the interval encompassing the second through eighth clock pulses H, by sensing the expected condition of counter outputs Q.sub.1 -Q.sub.4 during this interval. This signal is delayed by a delay network 93 to produce delay T.sub.D whereby AKB timing signal V.sub.B is developed at the output of delay network 93. The delay produced by network 93 can be produced, for example, by a plurality of series coupled logic gates, each providing a given delay.

Timing signal V.sub.C is developed at output G of array 92 during the interval including the third through the fifth clock pulses H. This signal is delayed by an amount T.sub.D via a network 94 and level shifted via a network 95 to produce grid drive pulse V.sub.G. Level shifting network 95 (e.g., a voltage translator) serves to produce signal V.sub.G with an amplitude suitable for driving the kinescope grid electrode.

A logic output H of array 92 produces a high ("1") logic level during the interval encompassing the sixth through the eighth clock pulses H from the end of the vertical retrace interval. Network 96 delays this signal by amount T.sub.D to develop timing signal V.sub.S. Auxiliary pulse V.sub.P is derived from signal V.sub.S by means of a signal inverter 98 and a level shifter 99, the latter serving to produce a pulse amplitude suitable for application to resistor network 32, 34 of FIG. 1. Output E of array 92 provides a control signal to the DISABLE input of counter 90 after the AKB interval ends (i.e., at the beginning of the ninth clock pulse H) to inhibit the counting process.