TTL Circuit Having Delay Means for Delaying the Operation Until the Supply Voltage Reaches a Certain Threshold

This invention relates to a TTL (Transistor Transistor Logic) circuit in which the output level is maintained at the "H" level immediately after the power supply is turned on.

In a facsimile machine of a thermosensitive printer type, the enable period of the thermal heads of the printer is usually controlled by the output of a gate circuit called a "set gate", etc. A driving circuit for the thermal heads is illustrated in FIG. 1. In FIG. 1, SG indicates a set gate circuit, INV indicates an inverter circuit, DA1 through DAm indicate data latch circuits, OG1 through OGm indicate output gate circuits with NAND logic, TH1 through THm indicate thermal heads, and RL1 through RLm indicate resistors for current limiting. The set gate circuit SG is a TTL logic circuit which receives an external set input SET indicating whether the operation can be effected, and generates an output signal having the same logic level as the set signal. The inverter circuit INV inverts the output of the set gate circuit SG, and the output of the inverter is supplied to all of the output gate circuits OG1 through OGm.

When the set input SET is "H", the output of the inverter circuit INV is "L", all of the outputs of the output gate circuits OG1 through OGm are "H" and no current flows through any of the thermal heads TH1 through THm. On the other hand, when the set input SET is "L", the output of the inverter circuit INV is "H" and, when the output of the corresponding data latch circuit is "L", the output of each of the output gate circuits OG1 through OGm is "H". When the output of the corresponding data latch circuit is "H", the output of each of the output gate circuits OG1 through OGm is "L". When the output of an output gate circuit OGi is "L", current flows through a thermal head THi and a character corresponding to the output data of the latch circuit is printed.

In the driver circuit of FIG. 1, there may be the following problem immediately after the power supply is turned on. The set input SET should be kept at "H" until the printed data is input into the latch circuits DA1 through DAm and the printing operation is instructed. However, in a transition condition, such as when turning on the power supply, the set input SET does not settle into either a "H" or "L" state. Thus, it is not certain if the output of the set gate circuit SG will become "H" or "L" i.e., it may become "H" or "L" randomly. If the output of the set gate SG becomes "L", then the output of the inverter circuit INV becomes "H". In this condition, if any one of the data outputs of the latch circuits DA1 through DAm is "H", then the output of the corresponding output gate circuit becomes "L" and a current flows through the corresponding thermal head. Since the current flowing through the terminal head is considerably large, even several milliseconds of current may result in printing. Thus, undesirable stain-like printing may take place on the paper in the transition period when turning on the power supply.

An object of the present invention is to provide a TTL circuit whose output is maintained at the "H" level immediately after the power supply is turned on. The TTL circuit can be used as the above-mentioned set gate circuit and can prevent the paper from being stained during the transition period.

In accordance with the present invention, there is provided a TTL circuit including an input circuit and an output circuit there is also provided means for controlling the output circuit and means for delaying the operation of the controlling means until the voltage supply rises up to a predetermined level after the voltage supply is turned on, whereby the output of the TTL circuit is forced to be "H" level until the voltage supply rises up to the predetermined level.

FIG. 1 is a block circuit diagram of a driver circuit of a thermal head;

FIG. 2 is a circuit diagram of a TTL circuit in accordance with one embodiment of the present invention; and

FIG. 3 is a waveform diagram of the voltage waveforms in the TTL circuit of FIG. 2 at the time the voltage supply is turned on.

A TTL circuit according to the present invention will be described in detail reference to the accompanying drawings.

FIG. 2 is a circuit diagram of a TTL circuit in accordance with one embodiment of the present inveniton. The TTL circuit of FIG. 2 can be used a the set gate circuit SG of FIG. 1. The TTL circuit of FIG. 2 comprises an input circuit 11, an output circuit 12, and a control circuit 13. The input circuit 11 has transistors Q1 and Q2, diodes D1, D2, and D3, and resistors R1, R2, and R3. The output circuit 12 has transistors Q5, Q6 and Q7 and a resistor R6. The control circuit 13 has transistors Q3 and Q4, diodes DS1 through DSn, and resistors RS, R4, and R5.

The set input SET is supplied to the base of the transistor Q1. When the set input SET is "L", the current flowing from the voltage supply Vcc through the resistor R1 flows from the emitter of the npn transistor Q1 to its base and the base potential of the transistor Q2 becomes low. Therefore, the transistors Q2 and Q3 become off. Accordingly, the current flowing from the voltage supply Vcc through the diodes DS1, . . . , DSn and resistor RS flows into the base of the transistor Q4, which is usually called a phase splitter transistor. Thus, the transistor Q4 turns on, and the output transistor Q7, whose base is connected to the emitter of the transistor Q4 and whose emitter is connected to the ground, turns on. On the other hand, the transistors Q5, whose base is connected to the collector of the transistor Q4, and Q6, having a Darlington type connection, are turned off. Thus, the output OUT becomes "L".

When the set input SET is "H", the transistor Q1 becomes off and the current flowing from the voltage supply Vcc through the resistor R1 flows through the diode D2 into the base of the transistor Q2. Thus, the transistor Q2 turns on and the transistor Q3 turns on. Therefore, the base potential of the transistor Q4 becomes low. Accordingly, the transistor Q4 turns off, and the output transistor Q7 turns off. On the other hand, the Darlington connection transistors Q5 and Q6 turn on, and the output OUT becomes "H".

In the above-mentioned operation of the TTL circuit of FIG. 2, in order to turn on the output transistor Q7, it is necessary for the base potential of the transistor Q4 to be increased by at least twice the base-emitter voltage V.sub.BE, i.e., 2 V.sub.BE. In the prior art TTL circuit, the base of the transistor Q4 is connected to the voltage supply Vcc only through the resistor RS. Accordingly, the transistor Q4 may be turned on after the voltage supply Vcc turns on and rises up to Vcc>2 V.sub.BE. Thus, in the prior art TTL circuit, as described before, the output OUT may be "L" transiently after the voltage supply turns on.

In the TTL circuit of FIG. 2, the base of the transistor Q4 is connected to the voltage supply Vcc through the diodes DS1 through DSn and the resistor RS, so that the base potential of the transistor Q4 cannot rise above 2 V.sub.BE until the voltage supply Vcc rises up to a sufficiently high level after turning on. The waveform of the voltage supply Vcc at the turning-on time is illustrated in FIG. 3 by the continuous line. As seen from FIG. 3, the voltage supply Vcc is turned on at the time t.sub.0 and rises up to 5 V in 2 to 5 milliseconds. The broken line of FIG. 3 illustrates the upper limit of the base potential V.sub.A of the transistor Q4. The voltage supply Vcc becomes 2 V.sub.BE at the time t.sub.1, and the upper limit of the voltage V.sub.A becomes 2 V.sub.BE at the time t.sub.2. The final upper limit of the voltage V.sub.A is lower than the voltage supply Vcc by n.V.sub.BE (n being the number of the diodes DS1 through DSn, and V.sub.BE being the forward bias voltage of each diode).

During the period from t.sub.0 to t.sub.1, all the output transistors Q5, Q6, and Q7 are off, and the output OUT is in a high impedance state. During the period from t.sub.1 to t.sub.2, the base voltage of the transistor Q4 is lower than 2 V.sub.BE. Therefore, the output transistor Q7 is off without regard to the set input SET and the output OUT is forced to be "H". The set input SET, which is produced by an external TTL circuit, can settle to "H" from a time t.sub.x after the time t.sub.1. Accordingly, by selecting the time t.sub.2 to be after t.sub.x, the output OUT is kept at "H" from the time of turning on to the time the set input SET is changed to "L". Thus, even if the set input SET may become "L" unexpectedly in the transition time from t.sub.0 to t.sub.x, this "L" level does not appear in the output OUT.

The number n of the diodes DS1 through DSn can be determined by the following equation;

Assuming V.sub.BE =0.8 V, Vcc=5 V, then n.ltoreq.4. In the case of n=4, the output OUT is forced to be "L" until the voltage supply Vcc rises up to 4.8 V. In the case of n=3, the output OUT is forced to be "H" until the voltage supply Vcc rises up to 4.0 V.

If the TTL circuit of FIG. 2 is used as the set gate circuit SG of FIG. 1, the outputs of the output gate circuits OG1 through OGn are kept at "H" immediately after the turning-on of the voltage source, so that current is prevented from following through the thermal heads TH1 through THm. The TTL circuit according to the present invention, however, can be used for many purposes other than the thermal head driver.

According to the present invention, the output of the TTL circuit can be securely kept at "H" immediately after the voltage supply is turned on.