US 4,480,306 AGrant
Digital Data Processing System Using Unique ALU Register Files and Micro-Instruction Stacks
Issue Date:1984-10-30
•9 Claims
•1 Drawing Sheets
Abstract
A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described with reference to the invention herein, identify locations of object information to be accessed by utlizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Such ALU means further include an ALU microinstruction stack means having at least one microinstruction stack frame for storing the state of execution of a microinstruction. A memory microinstruction stack is provided to store a plurality of microinstruction stack frames so that microinstruction stack frames can be transferred between the ALU and the memory microinstruction stacks. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.
Metadata
Assignee
- Data General Corporation
Inventors
- Brett L. Bachman
- Richard A. Belgard
- David H. Bernstein
- Richard G. Bratt
- Gerald F. Clancy
- Edward S. Gavrin
- Thomas M. Jones
- Lawrence H. Katz
- Craig J. Mundie
- John F. Pilat
- Stephen I. Schleimer
- Steven J. Wallach
- Walter A. Wallach, Jr.
- Douglas M. Wells
Application Information
Application Number:US 2664259
Filing Date:1981-05-22
Priority Date:1981-05-22
Art Unit:236
Classifications
IPC:
G06F 922
Field of Search:
364200;900
Patent Drawings (1 sheets)
Description
Cross Reference to Related Applications
The present patent application is related to other patent applications assigned to the assignee of the present application.
Background of the Invention
1. Field of the Invention
The present invention relates to a digital data processing system and, more particularly, to a multiprocess digital data processing system suitable for use in a data processing network and having a simplified flexible user interface and flexible, multileveled internal mechanisms.
2. Description of Prior Art
A general trend in the development of data processing systems has been towards systems suitable for use in interconnected data processing networks. Another trend has been towards data processing systems wherein the internal structure of the system is flexible, protected from users, and effectively invisible to the user and wherein the user is presented with a flexible and simplified interface to the system.
Certain problems and shortcomings affecting the realization of such a data processing system have appeared repeatedly in the prior art and must be overcome to create a data processing system having the above attributes. These prior art problems and limitations include the following topics.
First, the data processing systems of the prior art have not provided a system wide addressing system suitable for use in common by a large number of data processing systems interconnected into a network. Addressing systems of the prior art have not provided sufficiently large address spaces and have not allowed information to be permanently and uniquely identified. Prior addressing systems have not made provisions for information to be located and identified as to type or format, and have not provided sufficient granularity. In addition, prior addressing systems have reflected the physical structure of particular data processing systems. That is, the addressing systems have been dependent upon whether a particular computer was, for example, an 8, 16, 32, 64 or 128 bit machine. Since prior data processing systems have incorporated addressing mechanisms wherein the actual physical structure of the processing system is apparent to the user, the operations a user could perform have been limited by the addressing mechanisms. In addition, prior processor systems have operated as fixed word length machines, further limiting user operations.
Prior data processing systems have not provided effective protection mechanisms preventing one user from effecting another user's data and programs without permission. Such protection mechanisms have not allowed unique, positive identification of users requesting access to information, or of information, nor have such mechanisms been sufficiently flexible in operation. In addition, access rights have pertained to the users rather than to the information, so that control of access rights has been difficult. Finally, prior art protection mechanisms have allowed the use of "Trojan Horse arguments". That is, users not having access rights to certain information have been able to gain access to that information through another user or procedure having such access rights.
Yet another problem of the prior art is that of providing a simple and flexible interface user interface to a data processing system. The character of user's interface to a data processing system is determined, in part, by means by which a user refers to and identifies operands and procedures of the user's programs and by the instruction structure of the system. Operands and procedures are customarily referred to and identified by some form of logical address having points of reference, and validity, only within a user's program. These addresses must be translated into logical and physical addresses within a data processing system each time a program is executed, and must then be frequently retranslated or generated during execution of a program. In addition, a user must provide specific instructions as to data format and handling. As such reference to operands or procedures typically comprise a major portion of the instruction stream of the user's program and requires numerous machine translations and operations to implement. A user's interface to a conventional system is thereby complicated, and the speed of execution of programs reduced, because of the complexity of the program references to operands and procedures.
A data processing system's instruction structure includes both the instructions for controlling system operations and the means by which these instructions are executed. Conventional data processing systems are designed to efficiently execute instructions in one or two user languages, for example, FORTRAN or COBOL. Programs written in any other language are not efficiently executable. In addition, a user is often faced with difficult programming problems when using any high level language other than the particular one or two languages that a particular conventional system is designed to utilize.
Yet another problem in conventional data processing systems is that of protecting the system's internal mechanisms, for example, stack mechanisms and internal control mechanisms, from accidental or malicious interference by a user.
Finally, the internal structure and operation of prior art data processing systems have not been flexible, or adaptive, in structure and operation. That is, the internal structure structure and operation of prior systems have not allowed the systems to be easily modified or adapted to meet particular data processing requirements. Such modifications may include changes in internal memory capacity, such as the addition or deletion of special purpose subsystems, for example, floating point or array processors. In addition, such modifications have significantly effected the users interface with the system. Ideally, the actual physical structure and operation of the data processing system should not be apparent at the user interface.
The present invention provides data processing system improvements and features which solve the above-described problems and limitations.
Summary of the Invention
The present invention relates to structure and operation of a data processing system for use in interconnected data processing networks, which internal structure is flexible, protected from users, effectively invisible to users, and provides a flexible and simplified interface to users. The data processing system provides an addressing mechanism allowing permanent and unique identification of all information as objects generated for use in or by operation of the system, and an extremely large address space which is accessible to and common to all such data processing systems. The addressing mechanism provides addresses which, as particularly described with reference to the invention claimed herein, are independent of the physical configuration of the system and allow information to be completely identified, with a single address having an object field for identifying the location of an object, together with an offset field and a length field specifying, respectively, the start of, and the number of bits in, the object to be accessed. Accordingly, the information is completely identified by such address, to the bit granular level and with regard to information type or format. As further particularly described with reference to the invention claimed herein, an arithmetic logic unit (ALU) means includes general register means having three vertically oriented parts for storing such respective fields. The present invention can be used in a system which further provides a protection mechanism wherein variable access rights are associated with individual bodies of information. Information, and users requesting access to information, are uniquely identified through the system addressing mechanism. The protection mechanism also prevents use of Trojan Horse arguments. And, the present invention can be used in a system which provides an instruction structure wherein high level user language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for a plurality of user languages. Another feature of such a system is the provision of an operand reference mechanism wherein operands are referred to in user's programs by uniform format names which are transformed, by an internal mechanism transparent to the user, into addresses. As further particularly described with reference to the invention claimed herein, the present invention additionally provides multilevel control and stack mechanisms protecting the system's internal mechanism from interference by users. Thus, microinstruction stack means are provided for storing the state of execution of one or more microinstructions. An ALU microinstruction stack means contains at least one microinstruction stack frame while a memory microinstruction stack means contains a plurality or microinstruction stack frames, such stack frammes being transferrable between the ALU and memory microinstruction stack means. Yet another feature of such a system is a data processing system having a flexible internal structure capable of performing multiple, concurrent operations and comprised of a plurality of separate, independent processors. Each such independent processor has a separate microinstruction control and at least one separate and independent port to a central communications and memory node. The communications and memory node is also an independent processor having separate and independent microinstruction control. The memory processor is internally comprised of a plurality of independently operation, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. The present invention also provides further data processing system structural and operational features for implementing the above features.
It is thus advantageous to incorporate the present invention into a data processing system because the present invention provides addressing mechanisms suitable for use in large interconnected data processing networks. Additionally, the present invention can be used in a system which is advantageous in that it provides an information protection mechanism suitable for use in large, interconnected data processing networks. The present invention can be used in a system which is further advantageous in that it provides a simplified, flexible, and more efficient interface to a data processing system. The present invention can be used in a system which is yet further advantageous in that it provides a data processing system which is equally efficient with any user level language by providing a mechanism for referring to operands in user programs by uniform format names and instruction structure incorporating dialect coded, uniform format intermediate level instructions. Such a system protects data processing system internal mechanisms from user interference by providing multilevel control and stack mechanisms. The present invention is yet further advantageous in providing a flexible internal system structure capable of performing multiple, concurrent operations, comprising a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate and independent port to a central, independent communications and memory processor comprised of a plurality of independent processors capable of performing multiple, concurrent memory and communications operations.
It is thus an object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide a data processing system capable of use in large, interconnected data processing networks.
It is yet another object of the present invention to provide an improved addressing mechanism suitable for use in large, interconnected data processing networks.
It is a further object of the present invention to be capable of use in a system which provides an improved information protection mechanism.
It is still another object of the present invention to provide a simplified and flexible user interface to a data processing system.
It is yet a further object of the present invention to be capable of use in a system which provides an improved mechanism for referring to operands.
It is a still further object of the present invention to be capable of use in a system which provides an instruction structure allowing efficient data processing system operation with a plurality of high level user languages.
It is a further object of the present invention to be capable of use in a system which provides data processing internal mechanisms protected from user interference.
It is yet another object of the present invention to be capable of use in a system which provides a data processing system having a flexible internal structure capable of multiple, concurrent operations.
Other objects, advantages and features of the present invention will be understood by those of ordinary skill in the art, after referring to the following detailed description of the preferred embodiments and drawings wherein:
Brief Description of Drawings
FIG. 1 is a partial block diagram of a computer system incorporating the present invention.
This application incorporates by reference the entire application, Ser. No. 266,402, filed on May 22, 1981, of Baxter, II, et al.
More particularly, attention is directed to FIGS. 4, 4A, 5, 103-105, 106, 106A, 106B, 106C, 253 and 270-274 of the drawings in application Ser. No. 266,402, and to that part of the descriptive portion of the specification, particularly at pages 47-49, 55-59, 111-113, 124-137, 376-379 and 669-670 thereof, which relate to subject matter of the claims herein.
Claims
We claim:
1. In a digital computer system including processor means for performing operations upon operands, memory means for storing said operands and instructions for directing said operations, said operands and said instructions being uniquely identified as objects, bus means for conducting operands and instructions between said memory means and said processor means, and I/O means for conducting operands between said digital computer system and devices external to said digital computer system, said processor means comprising: ALU means connected from said bus means for performing operations in accordance with instructions, addressing means connected to said bus means for providing addresses for controlling the transfer of operands and instructions between said memory means and said processor means, each one of said addresses comprising an object field for identifying a corresponding one of said objects, an offset field for specifying a first number of information bits of offset relative to the start of said corresponding one of said objects, and a length field for specifying a second number of information bits of said corresponding one of said objects following said first number of information bits to be transferred between said memory means and said processor means, and microcode control means for storing sequences of microinstructions for controlling said processor means and responsive to instructions for providing said sequences of microinstructions to said processor means, said ALU means including general register file means connected from said bus means for storing selected operands and selected addresses, said general register file means comprising a plurality of vertically ordered registers vertically divided into three parallel-operating and addressed parts, a first part of said general register file means comprising first register file means for storing object fields of said addresses, a second part of said general register file means comprising second register file means for storing offset fields of said addresses, and a third part of said general register file means comprising third register file means for storing length fields of said addresses, and address ALU means connected to said general register file means and to said bus means and responsive to first sequences of microinstructions for performing operations on said selected addresses, said microcode control means responsive to said instructions for providing corresponding further sequences of microinstructions to said ALU means for controlling the operations of said ALU means directed by said instructions, at least one sequence of microinstructions of said first sequences of microinstructions corresponding to each of said instructions, and said ALU means including ALU microinstruction stack means containing at least one microinstruction stack frame for storing the state of execution of a microinstruction of said first sequences of microinstructions when the execution of said microinstruction has been interrupted.
2. The digital computer of claim 1, wherein said memory means further comprises: memory microinstruction stack means containing a plurality of microinstruction stack frames, each of said plurality of microinstruction stack frames for storing the state of execution of a microinstruction of said first sequences of microinstructions, and said ALU microinstruction stack means further comprising microinstruction stack control means responsive to the operation of said ALU means for providing stack control signals to said ALU microinstruction stack means and to said memory microinstruction stack means for controlling the transfer of microinstruction stack frames between said ALU microinstruction stack means and said memory microinstruction stack means.
3. The digital computer system of claim 1, wherein said microcode control means further comprises: monitor microcode means for storing sequences of monitor microinstructions for controlling the monitor operation of said ALU means, said monitor microcode means responsive to the operation of said ALU means to provide said sequences of monitor microinstructions to said ALU means, and said ALU means further comprises monitor stack means containing at least one monitor stack frame for storing the state of execution of a monitor microinstruction when the execution of said monitor microinstruction has been interrupted.
4. The digital computer system of claim 1 or 2 or 3, wherein said processor means further comprises: arithmetic means connected from said bus means for performing arithmetic operations on certain of said instructions, said arithmetic means including arithmetic microcode control means for storing sequences of arithmetic microinstructions for controlling the operation of said arithmetic means, said arithmetic microcode control means responsive to the operation of said ALU means to provide said sequences of said arithmetic microinstructions to said arithmetic means, and ALU arithmetic stack means containing at least one arithmetic stack frame for storing the state of execution of an arithmetic microinstruction when the execution of said arithmetic microinstruction has been interrupted.
5. The digital computer system of claim 4, wherein said memory means further comprises: memory arithmetic stack means containing a plurality of arithmetic stack frames, each one of said plurality of microinstruction stack frames for storing the state of execution of an arithmetic microinstruction, and said memory arithmetic stack means further comprises arithmetic stack control means responsive to the operation of said arithmetic means for providing control signals to said ALU arithmetic stack means and said memory arithmetic stack means for controlling the transfer of arithmetic stack frames between said ALU arithmetic stack means and said memory arithmetic stack means.
6. The digital computer system of claim 1, 2 or 3 wherein said memory means further comprises: instruction stack means responsive to the operation of said ALU means and containing at least one instruction stack frame for storing the state of execution of an instruction.
7. The digital computer system of claim 5, wherein said memory means further comprises: instruction stack means responsive to the operation of said ALU means and containing at least one instruction stack frame for storing the state of execution of an instruction.
8. The digital computer system of claim 4, wherein said memory means further comprises: instruction stack means responsive to the operation of said ALU means and containing at least one instruction stack frame for storing the state of execution of an instruction.
9. The digital computer system of claim 3, wherein: said general register file means is further horizontally divided into a first set of registers, a second set of registers, and a third set of registers, said first set of registers for storing selected operands and selected addresses for general ALU operations, said second set of registers comprises said ALU microinstruction stack means, and said third set of registers comprises said monitor microinstruction stack means.