Digital Frequency-Shift Keyed Demodulator

This invention relates to demodulation of frequency-shift keyed message-data signals.

In data transmission systems, data is often transmitted to a remote location by transmitting frequency-shift keyed (FSK) signals over a telephone line. An FSK signal received at the remote location is demodulated to recover the original data signal. To this end, a number of digital FSK demodulators have been proposed. The prior known FSK demodulators are designed to process analog line signals. Thus, if such FSK demodulators were to be used in a terminal with digitized line signals, for example, a .mu.-1aw PCM signal, the individual line signals to be demodulated would require digital-to-analog conversion before demodulation. Additionally, digital multipliers would be required which are complex and, therefore, undesirable.

These and other problems are overcome in the demodulation of frequency-shift keyed message-data signals in a received digital signal by employing an autocorrelation type demodulator using digital integration. Digital integration increments, i.e., area increments, are generated in accordance with an aspect of the invention by turning to account a relationship between zero crossings of the received signal, zero crossings of a delayed version of the received signal and polarity of the product of the received digital signal and delayed version relative to sampling points of the received signal. Specifically, the area increment in an n.sup.th sampling interval is determined by the time interval since the last zero crossing of the received signal before the n.sup.th sampling point, the time interval since the last zero crossing of the delayed signal before the n.sup.th sampling point and the polarity of the product signal at the n.sup.th sampling point. The area increments are accumulated by a saturating accumulator and compared to threshold values including hysteresis to generate signals representative of mark and space at the digital signal sampling rate.

The invention will be more fully understood from the following theoretical discussion and circuit description of an illustrative embodiment thereof taken in connection with the drawing including the appended figures, in which:

FIG. 1 is a graphical representation of estimating zero crossing locations employing linear interpolation between signal samples;

FIG. 2 is a graphical representation of a sequence of waveforms useful in describing the invention;

FIG. 3 is a table showing logic for generation of u(n);

FIG. 4 is a table showing logic for generation of v(n) and SGN[s(nT-.tau.)];

FIG. 5 is a graphical representation of the mark and space output of the demodulator; and

FIGS. 6 and 7 when combined as shown in FIG. 8 show in simplified block diagram form a FSK demodulator including an embodiment of the invention.

In an autocorrelation type FSK demodulator signals representative of the message-data, i.e., mark and space, are generated by multiplying a received signal with a delayed version of the received signal to generate a product signal, integrating the product signal and comparing the integrated product signal to a threshold value including hysteresis. In this example, the delay is .tau. where ##EQU1## where k=0, 1, . . . , fH is the mark frequency of, for example 1270 Hz,

fL is the space frequency of, for example 1070 Hz, and

k is selected to be, for example, 5. In general, .tau. is of the form .tau.=(L+f)T where T is the sampling interval, L is an integer and f is between 0 and 1.

As indicated above, the desired integration is realized in accordance with an aspect of the invention by turning to account a unique relationship between zero crossings of the received signal and delayed signal relative to the sampling points. Accordingly, the zero crossings of the received signal and its delayed version must be obtained. This is realized by linear interpolation between magnitudes of successive signal samples, s(n-1) and s(n), as illustrated in FIG. 1. The time t(n) from the estimated zero crossing to the time of occurrence of sample s(n) shown in the FIG. 1 is given by t(n)=Tx(n) where ##EQU2## where in this example T=1/8000=125 .mu.sec,

s(n) is the n.sup.th sample and

s(n-1) is the (n-1).sup.th sample.

Digital integration is realized in accordance with an aspect of the invention by accumulating increments in area of the product signal over sampling intervals T as illustrated in FIG. 2. As shown in FIG. 2, the area increment Z(n) (integration increment) in the n.sup.th sampling interval is determined entirely by x(n), the estimated quantized normalized time since the last zero crossing of received signal s(t) before the n.sup.th sample, by x(n)', the time since the last zero crossing of the delayed signal s(t-.tau.), and by the polarity of product signal s(nT)s(nT-.tau.). The received signal sampling points, i.e., sampling instances, are shown in FIG. 2 as n-1, n, n+1, etc. The magnitude of the area increment at the n.sup.th sampling, i.e., sampling instant is

where ##EQU3## where

and

The value u(n)=x(n) is obtained from (2) if a zero crossing, evidenced by a sign (polarity) change between s((n-1)T) and s(nT), was detected. If no zero crossing was detected, then x(n) exceeds 1 and u(n) is set to 1. The quantity u(n) is formed by selecting x(n) or 1, according to the prescribed logic criteria of the table shown in FIG. 3.

The value of x(n)' as the time since the last zero crossing of the delayed signal s(t-.tau.) signifies that a zero crossing occurred x(n)'+.tau./T time units in the past. If the ratio .tau./T were an integer, L, then x(n)' can be derived exactly as x(n) is derived, employing a L-sample delay of the received sample. In this example, L=10. However, in general, .tau./T will be of the form L+f, where 0<f<1. In this situation, the extra fractional delay f must be subtracted from equation (2) to form x(n)'. Specifically, if a sign change from s[(n-L-1)T] to s[(n-L)T] is detected, a representation of x(n-L)-f is generated which may be positive or negative. If the result is negative, it means that the zero crossing actually occurs in the next sampling interval of the (L+f)-delayed signal. In this situation, the result x(n-L-1)-f is stored and then augmented by 1, forming x(n-L-1)-f+1. Selection of x(n-L)-f, x(n-L-1)-f+1 or 1 to form the quantity v(n) is made according to the prescribed logic criteria of the table shown in FIG. 4.

The demodulator accumulates the area increments Z(n), i.e., integrates the product signal to generate area A(n), as follows,

The quantity H is a fixed positive saturating value and threshold. As illustrated in FIG. 5, the demodulator's output is Mark (positive) after A(n) exceeds H and remains so until A(n) first crosses the -H threhold, at which time the output is Space (negative) until the next time A(n) crosses +H. Thus, the estimated zero crossings of the data waveform coincide with crossings by A(n) of thresholds .+-.H.

FIG. 6 shows in simplified block diagram form a digital asynchronous FSK demodulator incorporating the present invention. The demodulator is intended for use with low data rate voice band message-data signals, for example, 300-baud. For simplicity and clarity of description timing signals have not been included, since use of such signals will be apparent to those skilled in the art.

The FSK demodulator shown in FIG. 6 is of the autocorrelation type in which digital signal s(t) including samples s(nT) representative of incoming mark and space frequencies used to transmit the message-data is supplied to input terminal 10. In practice, an input filter and limiter (not shown) may be employed in well known fashion. If the digital signal is .mu.-1aw, a converter (not shown) may be employed to generate a linear digital signal. In this example, 6 bit quantized samples including a sign bit and 5 magnitude bits are employed in s(nT) which are transmitted in parallel in the demodulator. In this example, the sampling rate is 8000 bits/second and T is 125 microseconds.

Accordingly, signal samples s(nT) of the mark and space frequencies are supplied via terminal 10 to bit select 11, delay 12 and delay 13. Bit select 11 is employed to supply the sign bit of s(nT) samples to a first input of Exclusive OR gates 14 and 15 and the 5 magnitude bits to an address input of interpolator 16. An appropriate gating circuit may be used for this purpose. Delay 12 is employed to delay s(nT) one sampling interval T to obtain s[(n-1)T]. Delay 12 may be a plurality of flip-flops or a shift register to realize the desired delay interval in well known fashion. Delayed samples s[(n-1)T] are supplied to bit select 17 which controllably supplies the sign bit of s[(n-1)T] samples to a second input of Exclusive OR gate 14 and the 5 magnitude bits of samples s[(n-1)T] to an address input of interpolator 16. Exclusive OR gate 14 operates as a sign (polarity) change (SC) detector between the presently received sample s(nT) and the last previously received sample s[(n- 1)T]. Output SC from Exclusive OR gate 14 is supplied to controllably enable interpolator 16 and signal select 18 when a change in sign and, hence, a zero crossing has occurred between successive signal samples. Interpolator 16 generates interval estimate x(n) to the zero crossing by simple interpolation between the amplitudes of the signal samples as described above and shown in FIG. 1. Interpolator 16 may be, for example, a read only memory (ROM) having signals stored in memory locations representative of values for x(n) relative to the magnitudes of s(n) and s(n-1). The appropriate memory location for generating x(n) is addressed by the 10 magnitude bits of s(n) and s(n-1) and an output signal representative of x(n) is generated when a sign change (SC) between s(n) and s(n-1) is detected via Exclusive OR gate 14. Signal x(n) includes 8 parallel bits which are supplied to a first input of select logic 18. Select logic 18 is used to generate output signal u(n). To this end, a signal representative of one (1) is supplied to a second input of select logic 18. Signal u(n) is generated in response to states of sign change signal SC from Exclusive OR gate 14 in accordance with the prescribed logic criteria of the table shown in FIG. 3 discussed above. Thus, u(n) is selected to be x(n) when there is a sign change represented by a logical 1SC signal and one (1) when there is no sign change represented by a logical 0SC signal. Signal u(n) is supplied to a negative input of summing circuit 20.

As indicated above, received signal samples s(nT) are also supplied via delay 13 to generate signal samples s[(n-L)T] which are supplied to bit select 21 and delay 22. Delay 13 may be a plurality of flip-flops or a shift register for realizing delay LT. Indeed, bit select 21, delay 22, Exclusive OR gate 24, interpolator 26 and bit select 27 perform functions essentially identical to bit select 11, delay 12, Exclusive OR gate 14, interpolator 16 and bit select 17, respectively. A difference is that appropriate signal representations are stored in a ROM in interpolator 26 to generate an 8-bit output signal representation of x(n-L)-f upon detection of a zero crossing, i.e., sign (polarity) change SC, from signal sample s[(n-L-1)T] to s[(n-L)T]. This output signal from interpolator 26 may be postive or negative and is supplied to bit select 28, delay 29 and select logic 30. Bit select 28 supplies the sign (polarity) bit, namely, RN(n), of the output from interpolator 26 to select logic 30 and select logic 31. Delay 29 is employed to store the output from interpolator 26 for one sampling interval. The output from delay 29 is supplied to summing circuit 32 and to bit select 33 which, in turn, supplies the sign (polarity) bit, namely, RN(n-1) of the stored signal to select logic 30 and select logic 31. Summing circuit 32 algebrically combines the delayed output from interpolator 26 and one (1) to generate x(n-L-1)-f+1. Select logic 30 controllably supplies either x(n-L)-f, x(n-L-1)-f+1 or 1 to generate v(n) in accordance with the prescribed logic criteria of the table shown in FIG. 4. Signal v(n) is supplied to a positive input of summing circuit 20.

Summing circuit 20 algebrically combines v(n) and u(n) to generate (v(n)-u(n)) in well known fashion which, in turn, is supplied to 2.times.MAG unit 34 which is a summing circuit for modifying the magnitude of (v(n)-u(n)) to generate 2.vertline.v(n)-u(n).vertline.. A signal representing 2.vertline.v(n)-u(n).vertline. is supplied to a negative input of summing circuit 35 while a signal representative of one (1) is supplied to a positive input to algebrically combine the signals to generate Y(n)=1-2.vertline.v(n)-u(n).vertline.. A signal representative of Y(n) is supplied to sign inverter 36 for generating the area increment, Z(n), i.e., integration increment for the n.sup.th sampling interval. Sign inverter 36 is responsive to the sign of the product signal P(n) for generating Z(n) in accordance with Y(n) of equation 4 with the sign of P(n) of equation 5.

The sign of product signal P(n) is generated by supplying the sign (polarity) bit of sample s(nT) and sign (polarity) bit of s(nT-.tau.) to Exclusive NOR gate 15 which operates to generate a logical 1 when the sign of P(n) is negative. In turn, the logical 1 P(n) signal causes sign inverter 36 to invert the sign of Y(n). A logical 0 P(n) signal causes no inversion of the sign of Y(n). Sign (polarity) bit SGN(nT-.tau.) of s(nT-.tau.) is generated by supplying the sign bits of s(nT-L) and s(nT-L-1) to select logic 31 which is enabled in response to sign (polarity) change signal SC from Exclusive OR gate 24, sign (polarity) bit RN(n) and sign (polarity) bit RN(n-1) to generate SGN[s(nT-.tau.)] in accordance with the prescribed logic criteria shown in the table of FIG. 4.

Area increment Z(n) is supplied to saturating accumulator 40 including summing circuit 41, 8 bit limiter 42 and delay 43. Saturating accumulator 40 operates in well known fashion to generate A.sub.SAT (n) as described above. A.sub.SAT (n) is supplied to threshold comparator 44 including hysteresis to generate a signal representative of mark (positive) and space (negative) of the received message-data in accordance with equation 6 discussed above and shown in FIG. 5. Threshold comparator 44 includes decoder 45 which generates a 2 bit word in response to the 8 bit A.sub.SAT (n) signal. The 2 bit word output from decoder 45 is used to control select logic 46 to generate a logical 1 or 0 output depending on the presently generated output fedback via delay 47. Thus, the output from select 46 and, hence, the FSK demodulator output is either a logical 1 (mark) or logical 0 (space) at an 8000 bit/second rate.

Time sharing of the demodulator over N input time-division multiplexed trunks is readily realized by multiplying the 8000 bit/second rate by N and employing N-word shift registers for delay units 12, 13, 22, 29, 43 and 47.