Compound Current Mirror

The present invention relates generally to integrated electronic circuits, particularly those which use FET (field effect transistor) devices, and relates more particularly to a type of current amplifier commonly used in such circuits.

A current mirror is a type of current amplifier which provides a high impedance output current proportional to an input current. The output current is typically used to drive a load for high gain. A simple mirror generally consists of a single input and a single output transistor pair, with the gate electrodes of the pair being tied together and to an input voltage node at the drain of the input transistor. The sources of the transistors are connected to a reference voltage node which is common to both. The drain and gate of the input transistor are connected to a current source which provides a quiescent reference current. Because the input and output transistors have their gates and sources tied together, a corresponding output current arises in the conduction path of the output transistor. Generally, the input and output transistors are identical and there is a substantially unity gain in the current. Such mirrors are commony used to provide active loads in high gain amplifier stages.

There are presently two conflicting trends in the design of MOS circuits. One is a trend toward MOS (metal-oxide-silicon) devices with shorter conduction channel lengths for accommodating higher signal frequencies. The other is a trend toward lower supply voltages for reducing power consumption, so that more devices may be included in a single circuit, on a chip. The conflict arises in that as the devices of a current mirror have their channel lengths shortened, their transconductance rises, but their output conductance rises even faster. The resulting lower available current mirror output impedance has led to combined arrangements of two or more mirrors in which the output transistors are connected in series. These, however, require increased power supply voltage, or overhead, for obtaining increased output impedance because each of the output transistors requires sufficient drain-to-source voltage to be biased in saturation.

The novel arrangement in accordance with the present invention is a compound current mirror which includes at least two input and output transistor pairs. The input transistors have separate and equal conduction path currents but different conduction path geometries. The geometries of the input transistors are related to each other in such a manner that they result in gate bias voltages which optimize the drain-to-source voltages V.sub.DS of the output transistors. For a dual pair combination with MOS devices, one of the input transistors has a conduction channel width-to-length ratio W/L which is at least about four times that of the other input transistor device.

With both ouput transistors operating at their minimum required V.sub.DS, it is possible to obtain a greater voltage swing from an output node for a given supply voltage.

FIG. 1 is a schematic circuit diagram of a compound current mirror in accordance with the one embodiment of the present invention and including an upper and a lower input and output transistor pair.

FIG. 2 is a schematic circuit diagram of a compound current mirror in accordance with another embodiment of the invention in the form of the mirror of FIG. 1 modified by the inclusion of an additional transistor for equalizing the transistor drain-source voltages of the lower transistor pair.

FIG. 3 is a schematic circuit diagram of a complementary MOS operational amplifier having a differential input stage which includes a compound current mirror in accordance with the invention.

The current mirror 10 shown in FIG. 1 of the drawings includes an upper input an ouput pair of transistors 12, 14 and a lower input and output pair of transistors 16, 18. All the transistors 12, 14, 16, 18 are N-channel MOS devices of the enhancement mode type. The upper transistors 12, 14 have their gates connected together and tied to the drain of the upper input transistor 12 to form a cascode arrangement. The lower transistors 16, 18 have their gates connected together and tied to the drain of the lower input transistor 16. The upper input transistor 12 has its conduction path connected between an upper input current source 20 and a reference node 22, while the lower input transistor 16 has its conduction path connected in series with a lower input current source 24 and the reference node 22. The output transistors 14, 16 have their conduction paths connected in series between the reference node 22 and an output node which is positive with respect to the voltage on the reference node 22. The input transistor 16 and both of the output transistors 14, 18 are substantially similar in their geometry and thus in their operational characteristics. In particular, they have the same conduction channel width-to-length ratio W/L. The upper input transistor 12, however, has a conduction channel ratio of 1/4 (W/L). The width W of the conduction channel of an MOS transistor is the effective physical width of the source and the drain electrodes. The length L of the conduction channel of an MOS transistor is the shortest physical distance between the source and drain electrodes as taken along the conduction channel. As will be seen from discussion below, the 1/4 W/L geometry of the upper input transistor 12 permits setting the quiescent state bias voltages of the gate nodes at levels which puts both the upper and lower output transistors 14, 18 in a saturated operating state.

The current sources 20, 24 are designed so that in the quiescent state equal reference currents I.sub.ref. flow through the conduction paths of the input transistors 12, 16. Since MOS devices are "square law" devices, their drain current is related to their gate-source voltage by a polynomial expression which can be simplified by eliminating terms of practically insignificant magnitude so that it becomes ##EQU1## where I.sub.D is the drain-to-source current, or the conduction path current,

W/L is the channel width-to-length ratio,

V.sub.GS is the gate-to-source voltage, and

V.sub.T is the threshold voltage of the device.

This square law relationship applies to MOS devices only when biased in saturation; that is, devices for which

The amount by which a device's gate-to-source voltage V.sub.GS exceeds V.sub.T will be referred to as the on-voltage V.sub.ON of the device. For operation in saturation, then, V.sub.DS .gtoreq.V.sub.ON.

The reference current from the current source 24 and the W/L of transistor 16 establish: ##EQU2## so that the quiescent state voltage at the drain and gate of the lower input transistor 16 is V.sub.T +V.sub.ON. It follows that the drain-to-source voltage under these conditions for the lower output transistor 18 must exceed V.sub.ON. Proceeding in a like manner for the upper input transistor 12 leads to a gate voltage of V.sub.T +2 V.sub.ON for it. It follows that the upper output transistor 14 will be in saturation, provided its drain voltage exceeds only 2 V.sub.ON. Thus it is seen that by virtue of the 1/4 W/L geometry of the upper input transistor 12 with respect to the W/L geometry of the lower input transistor 16, the gate bias voltages of the mirrors are determined so that in the quiescent state both the output transistors 14, 18 can operate at their V.sub.ON, which is just enough for saturation. This is a highly desirable condition, since it permits the voltage ouput for a double-to-single ended converter application to have a voltage swing to well within a threshold voltage V.sub.T of the voltage on the reference node 22.

The FIG. 2 of the drawings is a schematic circuit diagram of a current mirror 30 which is a modified version of the mirror 10 of FIG. 1 and has corresponding elements identified by the same reference numerals. The mirror 30 includes in addition to the four transistors 12, 14, 16, 18 a fifth, equalizing transistor 32 connected between the drain of the lower input transistor 16 and the current source 24. The gate of the lower input transistor 16 is connected to the drain of this equalizing transistor 32. The equalizing transistor 32 has its gate connected to the gates of the upper input and output transistors 12, 14. Its presence assures that the V.sub.DS of the lower input transistor 16 will be equal to the V.sub.DS of the transistor 18, thereby substantially eliminating current offsets in the compound mirror 30.

In FIG. 3 of the drawings there is shown a CMOS (complementary MOS) operational amplifier 34 which includes a current mirror in accordance with the invention. The amplifier 34 has a negative supply voltage node 36 and a positive supply voltage node 38. All the transistors are enhancement mode MOS devices. An N-channel negative differential input transistor 40 and an N-channel positive differential input transistor 42 have their sources connected to the drain of a current source transistor 44 which has its own source connected to the negative supply voltage node 36. The gate of the current source transistor 44 is connected to a bias voltage V.sub.bias. The gate of the negative input transistor 40 forms an inverting input port (-). The gate of the positive input transistor 42 forms a noninverting input port (+). The drain of the positive input transistor 42 is connected to the source of an isolating transistor 48. A P-channel compound current mirror provides an active load for the input stage of the amplifier 34. It is noted than this P-channel mirror has a configuration which appears inverted when compared to that of the N-channel transistor mirrors 10, 30 of FIG. 1 and FIG. 2 due to the opposite channel polarity of the devices. Two P-channel transistors 50, 52 have their conduction paths connected in series, respectively, between the positive supply voltage node 38, which here corresponds to a reference voltage node, and the drain of the isolating transistor 48. The gate of the transistor 50 is tied to the gate of a P-channel input transistor 54. The input transistor 54, a P-channel equalizing transistor 56, and an N-channel isolating transistor 58 are connected with their conduction paths in series, respectively, between the positive supply voltage node 38 and the drain of the negative input transistor 40 to form a first input current branch. An input transistor 60 and an N-channel diode-connected isolating transistor 62 have their conduction paths connected in series, respectively, between the positive supply voltage node 38 and the drain of the negative differential input transistor 40 to form the second input current branch. The drain of the equalizing transistor 56 is tied to the gates of the transistors 54, 50. The gates of the equalizing transistor 56 and the isolating transistors 48, 58, 62 are all tied to the gates of the transistors 60, 52.

The drain of the current mirror output transistor 52 forms an ouput node of the input stage of the amplifier 34 and is connected to the gate of a P-channel output transistor with an N-channel current source transistor 66, respectively, between the positive supply voltage node 38 and the negative supply voltage node 36. A capacitor 70 is connected between the gate of the output transistor 64 and to one side of a parallel pair of complementary resistor-connecred MOS devices 72, 74 which have their other side connected to the drains of the output transistors 64, 66. The capacitor 70 and the resistor devices 72, 74 together form a frequency compensation network. The drains of the output transistors 64, 66 are part of the output node of the amplifier 34.

The W/L rations of input transistor 54 and equalizing transistor 56 are the same. The width-to-length ratio W.sup.1 /L.sup.1 of the isolating transistors 48, 58, 62 are related to each other, but not necessarily to the W/L of the transistors 50, 52, 54, 56, 60 of the mirror. Transistors 58, 62 divide the bias current equally into the two input branches of the compound mirror. Transistor 60, at 1/4 the W/L of the transistors 54, sets up the bias level of the transistor 52, 56 at V.sub.T +2 V.sub.ON below the V.sub.DD rail. Transistors 50 and 52 are sized at 2 times the W/L of the transistor 54 to force the drain currents of transistors 40 and 42 to be nominally equal. Transistors 50, 54 are biased at the edge of saturation, allowing the high-gain region of the input stage to extend above V.sub.DD -V.sub.T. Greatly enhanced input stage voltage gain is combined with simple second stage design.

The compound mirror configurations 10 and 30 of FIGS. 1 and 2 are designed to have unity current gain in the interest of facilitating their descriptions by eliminating needless complexity. They could readily be modified in known ways analogous to those which apply to simple current mirrors to have a non-unity current gain. This is accomplished, in principle, by changing the relative width-to-length ratios of the input and output transistors of a given pair according to the desired gain. The mirror in the amplifier 34 of FIG. 3, for example, has twice the gain of the mirrors 10 and 30.

It will be apparent to those skilled in the art that any of the above-described circuits can be realized with transistors having a conduction channel of the conductivity type which is the opposite of that for the corresponding shown transistor by switching the power supply and reference voltage node polarities accordingly. Moreover, in either case the transistors may be of the enhancement mode type, the depletion mode type, or combinations of both types.

The invention can be realized with any "square-law" device, i.e., a device for which the conduction path current is proportional to the square of the minimum voltage V.sub.ON on the conduction path for establishing a saturation of majority carriers in it. Such devices include the various FET devices, particularly insulated gate FET's, such as MOS transistors. The various different N-channel and P-channel MOS devices, whether enhancement mode or depletion mode, can be configured either in unmixed or mixed configurations to form an arrangement in accordance with the invention. In general, therefore, the width-to-length ratio of the conduction channel of the larger ratio input transistor will be proportional to the width-to-length ratio of the conduction channels of the output transistors as the input reference current is proportional to the corresponding output current.

While in the above Examples 1, 2, and 3 there are only two current mirror output transistors present, more could be added as desired and associated with corresponding additional input branches, with input transistors having the appropriate W/L to bias their output transistor at V.sub.DS =V.sub.ON. For example, a third output transistor added to the mirror of FIG. 1 would have its conduction path connected between the source of the lower output transistor 18 and the reference node 22. An input transistor associated with it in a third input current branch would have a (1/9 ) W/L; an input transistor associated with a fourth output transistor would have a (1/16) W/L, and so on. As a practical matter, however, the use of three or more output transistors rapidly approaches a point of diminishing returns. The output voltage node can swing only as close to the supply voltages as the sum of the output transistor V.sub.ON 's. Therefore, the benefits of low supply voltage operation are soon compromised by a combination which includes too many output transistors.