Cross Coupled Amplifier

The present invention relates to the field of differential pair amplifiers, and more specifically to a new differential amplifier circuit for providing improved transconductance and input impedance characteristics.

Differential amplifiers function, in general, to amplify the difference between two signals. They are used in a wide variety of measurement applications where response from DC to many megahertz is required. In addition, differential amplifiers are the basic stage of integrated operational amplifiers with differential inputs.

While there are a wide variety of differential amplifier circuit topologies, most, if not all, include a constant current source, two load resistors and symmetrical transistors input stages for splitting the constant current between the load resistors. Usually, the output voltage is taken as the difference in the voltage drops across the load resistors; in this manner, large variations in output voltages may be achieved with extremely small input voltage differentials. One such amplifier, and perhaps the simplest, is the symmetrical emitter-coupled differential amplifier. This amplifier topology comprises two transistors having their emitters connected to a current source, their collectors each tied to a positive potential, possibly through an equivalent load resistance, with the output taken in the form of a current from the collectors which is related to the input potential difference between the two bases. The collector current is most often converted to a voltage by the load resistance. The circuit makes an excellent differential amplifier if the emitter resistance is kept relatively large.

For all differential amplifiers there are associated therewith certain differential voltage gain and input resistance performance characteristics. These characteristics and others determine the usefulness of the amplifier in any given application. For example, some applications may require an amplifier with a high input impedance and moderate gain, and vice versa. For the simple emitter-coupled differential amplifier, differential voltage gain is directly proportional to the level of the constant current (I.sub.o), and the load resistance (R.sub.1); differential input resistance is directly proportional to the input transistor .beta. and inversely proportional to I.sub.o. Therefore, in order to increase the gain without changing R.sub.1 and thereby degrading the output impedance, I.sub.o must be increased, giving rise to an undesirable decrease in input resistance.

One well-known modification to the basic differential amplifier that provides for increased input resistance is the addition of a single transistor to each side to form a Darlington pair. This Darlington differential amplifier topology provides a differential input resistance which, compared to differential input resistance of the simple emitter-coupled type of amplifier, is a factor of .beta. larger. As a result, differential gain may be improved, by increasing I.sub.o, while maintaining a relatively high differential input resistance.

While the two foregoing topologies provide adequate performance for most applications, improvements in the differential gain and input impedance characteristics of differential amplifiers have been a constant goal for designers. Accordingly, there exist numerous differential amplifier designs, each attempting to maximize certain performance characteristics. However, until now there have been no significant improvements in differential amplifier performance without relatively large increases in their corresponding degree of complexity, usually requiring multiple stages with increased power dissipation. As a result these improvements have had limited usefulness, especially in designs where power consumption and space limitations are critical.

Unlike the above-mentioned prior art improvements, the present invention provides for a significant increase in differential gain and greatly improved differential input resistance with the addition of only two transistors to the basic Darlington pair differential amplifier topology. In accordance with the present invention, this improved differential amplifier preferably comprises two Darlington transistor pairs connected to form complementary sides of a differential amplifier with two cross-coupling transistors connected to provide complementary positive feedback of gain less than one between the sides.

According to another aspect of the present invention, there is provided negative input impedance. This and other characteristics give the present invention wide application possibilities, including uses in high frequency limiter amps, comparator input stages, programmable Schmitt triggers, automatic gain controllers, implantable devices, and any other application where the improved characteristics of the present invention may be advantageously utilized.

In the drawing:

FIG. 1 is a schematic illustration of a prior art simple emitter-coupled differential amplifier;

FIG. 2 is a schematic illustration of a prior art Darlington pair differential amplifier;

FIG. 3 is a schematic illustration of a cross-coupled amplifier according to the present invention;

FIG. 4 is a schematic illustration of an alternative embodiment of a cross-coupled amplifier according to the present invention; and

FIG. 5 is a graph showing the gain response of the present invention for three different values of feedback resistance.

In order to facilitate the understanding of the present invention's advantages, a short review of the basic differential pair differential amplifier and common Darlington differential amplifier is provided herein. FIG. 1 shows a simple differential pair differential amplifier having a constant current source, which sinks a constant current I.sub.o, connected to its tail. The amplifier's differential input voltage, V.sub.d, is defined as:

The amplifier's small signal differential gain Av.sub.d, which is the ratio of the change in the output voltage V.sub.out to the change in the input voltage V.sub.d, is then expressed by: ##EQU1##

Similarly, the amplifier's differential input resistance is expressed as the ratio between incremental changes in V.sub.d to incremental changes in I.sub.in. This relationship may be expressed as: ##EQU2## Finally, if driven with a source resistance R.sub.s, the amplifier's gain becomes: ##EQU3##

FIG. 2 shows the differential amplifier of FIG. 1 with a Darlington input modification. The differential gain for this circuit may be given as: ##EQU4## It is seen, then, that for the same values of R.sub.1 and I.sub.o the differential gain of this circuit is only half of that for the circuit of FIG. 1. (Note: this problem can be eliminated by inserting current sources from the input transistor emitter to ground, at the expense of increased supply current and added complexity.) However, the differential input resistance is greatly improved: ##EQU5## This improvement is due primarily to the circuit's .beta..sup.2 dependence. Finally, the gain for this amplifier, when driven with a source resistance R.sub.s, is: ##EQU6##

As evidenced above, source resistance R.sub.s has parasitic effect on the gain of either differential amplifier. If, for example, the simple differential pair differential amplifier of FIG. 1 is driven with a voltage source having a source resistance given by: ##EQU7## and a nominal .beta. value of 100, the gain drops by approximately 2%: ##EQU8## Similarly, the Darlington differential AMPs gain drops by about 0.01%: ##EQU9##

An improved amplifier according to the present invention is schematically illustrated in FIG. 3. Input voltages V.sub.1 and V.sub.2 are applied to the respective bases of transistors 44 and 46. The collectors of transistors 44 and 46 are both connected to a positive potential VCC. The emitter of transistor 46 is connected to the base of transistor 47, the base of transistor 52, and the collector of transistor 50. The emitter of transistor 44 is similarly connected to the base of transistor 45, the base of transistor 50, and the collector of transistor 52. The emitters of transistors 45, 50, 52, and 47 are connected together and tied to constant current source 42, which in turn is connected to a negative potential VEE. The collectors of transistors 45 and 47 are connected to one end of the respective load resistors 62 and 64. The other ends of both resistors 62 and 64 are connected to the positive potential VCC. The output V.sub.out is taken across the collector ends of load resistors 62 and 64.

Turning to FIG. 3, the operation of the present invention will now be explained. With the exception of the symmetrical "cross-coupling" transistors 50 and 52, the circuit of FIG. 3 is identical to that of FIG. 2. However, this addition provides significant deviation in the circuit's input impedance and gain characteristics. Equal input voltages V.sub.1 and V.sub.2 produce equal currents I.sub.1 and I.sub.2. Currents I.sub.1 and I.sub.2 are very nearly equal the respective currents I.sub.6 and I.sub.5 due to the identical nature of transistor pairs 45 and 50, and 52 and 47. Therefore, tail current I.sub.o, which is the sum of currents I.sub.3 and I.sub.4, is composed of the very nearly equal currents I.sub.1, I.sub.2, I.sub.5, and I.sub.6. If voltage V.sub.1 is then increased, voltage V.sub.3 will tend to follow it. An increase in voltage V.sub.3 increases the V.sub.be (base to emitter voltage) of transistors 45 and 50. This has two effects, the first being an increase in current I.sub.5 and the second being a corresponding increase in the current I.sub.2. As current I.sub.2 increases, the V.sub.be of transistor 46 increases, thereby resulting in a corresponding further decrease in voltage V.sub.4. The lowering of voltage V.sub.4 has the effect of decreasing the V.sub.be voltages of transistors 47 and 52, thereby reducing currents I.sub.6 and I.sub.1 by equal amounts. Furthermore, as current I.sub.1 decreases, the V.sub.be voltage of transistor 44 also decreases, and in order to keep the voltage drop from input V.sub.1 to node 40 constant, the voltage across the V.sub.be of transistors 45 and 50 has a further tendency to increase and thereby cause another increase in currents I.sub.5 and I.sub.2. So, unlike the Darlington differential amplifier illustrated in FIG. 2, in which an increase in the active condition of one side gives rise to a nearly equal decrease in the active condition of the other side, the present invention amplifies the decrease in the active condition of the other side, and thereby provides for improved gain. Even though this is a positive feedback scheme, the overall gain is less than one due to finite .beta., and therefore stability is not a problem. On the contrary, this positive feedback improves differential gain by enhancing or accentuating the effects of a small input voltage differential. It will be seen, then, that the addition of transistors 50 and 52 to the circuit of FIG. 2 greatly enhances its gain performance by providing a complementary positive feedback between the sides of the amplifier.

A theoretical derivation of transconductance (gain) and input resistance for the present invention will now be given. Before beginning, it is important to note that the theoretical basis of the present invention's operation is due to second order effects and therefore these effects must be accounted for in the analysis. The currents through resistors 62 and 64 may given as follows: ##EQU10## The differential input voltage V.sub.d is: ##EQU11## With transconductance (with respect to I.sub.4) given as: ##EQU12## The total transconductance to the output collector of transistor 48 is then: ##EQU13## Given load resistance R.sub.L the differential gain is simply: ##EQU14## Input resistance may be expressed as: ##EQU15## Therefore, for high .beta., this negative input impedance becomes: ##EQU16## While in general a negative input impedance of this type can also be provided using tunnel diodes, tunnel diodes are difficult to bias and hard to control. On the contrary, the present invention provides a negative input impedance easily biased and easily controlled by the tail current (I.sub.o), and negative input impedance can be quite useful. One major advantage of negative input impedance is seen when considering the gain of the present invention if driven with a source resistance R.sub.s. For R.sub.s <16KT/qI.sub.o, gain is given as follows: ##EQU17## It is easily seen that an increase in R.sub.s gives yield to an increase in gain. This is in direct contrast to the corresponding gain performance of the simple differential pair and Darlington differential amplifiers, in which an increase in R.sub.s results in a decrease in gain. For instance, for the same source resistance R.sub.s =8KT/qI.sub.o, the gain of the present invention increases by a factor of 2, while that of the differential pair drops by approximately 2% (equation 9), and that of the common Darlington by 0.01% (equation 10).

Improvement in the present invention's differential gain may also be illustrated by making comparison to the simple differential pair and the Darlington differential amplifiers. Taking the ratio of equation 16 to that of equation 2 we get: ##EQU18## Thus, for a nominal .beta.=100, the gain of the present invention is improved by a factor of 12.5 over that of the differential pair shown in FIG. 1. Even greater improvement is seen when comparing the gain of the present invention to the gain of the common Darlington differential amplifier shown in FIG. 2. Taking the ratio of equation 16 to that of equation 5 we get: ##EQU19## In this case for a nominal .beta.=100 the gain is improved by a factor of 25.

It will be seen from the foregoing then that when driven through the appropriate source resistance the present invention easily provides gains an order of magnitude better than those of conventional differential amplifiers without increased power dissipation.

An alternative embodiment of the present invention is shown in FIG. 4. The circuit is identical to the circuit of FIG. 3 but has the additional feedback resistor 70 (R.sub.e) which is connected on one end to the collector of transistor 50, and the bases of transistor 52 and 47, and on the other end to the collector of transistor 52 and the corresponding bases of transistors 45 and 50. As will be explained, this embodiment of the present invention provides for gain control using resistance 70 to reduce the amount of positive feedback provided by transistors 50 and 52. The plots of output voltage V.sub.out against input voltage V.sub.d, or gain, for three values of R.sub.e are depicted in FIG. 5. As indicated by the plot denoted by R.sub.e =.infin., the highest gain is obtained in the absence of feedback. As the two other plots indicate, as R.sub.e decreases, the gain is reduced, thereby making it less susceptible to .beta. variations. Another effect of this negative feedback is an increase in the value of the negative input resistance, which results in a corresponding decrease in the susceptibility of the gain to input loading. Surprisingly, as FIG. 5 demonstrates, the limiting characteristics of the present invention do not vary in response to the value of the feedback resistance. This means that the transfer characteristic maintains its functional form (not linearized as would be the case for standard emitter degeneration) until the amplifier saturates. This property of the present invention makes it potentially useful as a limiter amplifier in an FM IF system or in a signal compression circuit.

Another potential use for the present invention is in the input stage of a comparator; the amplifier's positive feedback increasing differential transconductance and improving response time. Still other potential uses exist in the areas of automatic gain control and programmable triggers. In fact, potential uses for the present invention exist anywhere differential amplifiers are now used. In addition to this myriad of potential uses, the present invention is particularly useful in applications where space and power consumption are critical, such as for implantable medical devices. Because of its much-improved gain performance, the present invention allows for the elimination of relatively complex gain boosting stages. The result is better or comparable gain performance with less power consumption and corresponding improvements in battery and device life.

Although the preferred embodiment of the present invention is shown using npn bipolar technology, it will be seen that the invention may be practiced with pnp bipolar and FET technologies, the topology for either being readily derived from the small signal models associated with the npn embodiment. Furthermore, it will be seen that the present invention may be practiced using either discrete or integrated designs.