US 4,473,939 AGrant
Process for Fabricating GaAs FET With Ion Implanted Channel Layer
Issue Date:1984-10-02
•12 Claims
•1 Drawing Sheets
Abstract
There is herein described a process for fabricating GaAs FETs with an ion implanted channel layer wherein an ion implanted substrate is capless annealed under an arsine overpressure, and a relatively shallow portion of the outer surface of the substrate in the active layer is removed for the deposition of a gate metallic electrode.
Metadata
Assignee
- Hughes Aircraft Company
Inventors
- Milton Feng
- Victor K. Eu
- Hilda Kanber
Application Information
Application Number:US 4532511
Filing Date:1982-12-27
Priority Date:1982-12-27
Art Unit:114
Classifications
IPC:
H01L 21324
Field of Search:
29148571;576 B1.5;189
Patent Drawings (1 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates generally to the field of ion implanted semiconductor materials and more particularly to techniques for producing MESFET devices.
2. Description of the Prior Art
Ion implantation technology has been used for GaAs FET channel formation over the past several years. However, devices made using ion implanted channels have demonstrated inconsistent RF and DC performance. This is because the quality of the channel layer strongly depends on the properties of the semi-insulating substrate, which contains high levels of impurities such as chromium. It is also known that redistribution of impurities takes place when the substrate is heat treated to anneal out the implantation damage.
In spite of inconsistent results associated with the use of ion implantation for the formation of the active channel, this technique provides a number of advantages. These include the possibility of planar type device and circuit technology, good uniformity of the channel layers and economy. For the microwave discrete devices, monolithic integrated circuits and digital integrated circuits, ion implantation continues to offer significant advantages over other technologies. Recently, quarter-micron gate length FET devices have been reported with a noise figure of 1.9 dB and 7 dB associated gain at 18 GHz. Other reports indicate that a noise figure of 1.3 dB with an associated gain of 10 to 11 dB at 12 GHz have been achieved. In all cases, these devices have been fabricated with deeply recessed gate structures (0.3 .mu.m) on 0.5 .mu.m thick active channel layers over high quality buffer layers grown by AsCl.sub.3 /liquid Ga/H.sub.2 vapor phase epitaxy (VPE).
As an advancement in the art, the present invention provides extremely low-noise and low-cost GaAs MESFETs fabricated by new ion implantation techniques without deeply recessed gate structures. The best performance (to date) includes a 1.3 dB noise figure with 10.3 dB associated gain at 12 GHz and a noise figure of 2.3 dB with an associated gain of 7.4 dB at 18 GHz.
Summary of the Invention
In view of the foregoing factors and conditions characteristic of the prior art, it is a primary object of the present invention to provide a new and improved method for making GaAs FET devices having an ion implanted channel layer.
Another object of the present invention is to provide a high yield method for manufacturing GaAs FETs having uniform RF and DC, and very low-noise characteristics.
Still another object of the present invention is to provide a technique suitable for large scale production of GaAs FETs having noise figure averages around 1.6 dB and 10 dB associated gain at about 12 GHz.
Yet another object of the present invention is to provide a technique for producing GaAs FETs having single wafer uniformity and excellent wafer-to-wafer reproducibility.
Still a further object of the present invention is to provide GaAs FETs with suitable application for LNFET, power FET and monolithic integrated circuits.
Yet a further object of the present invention is to provide a GaAs FET configuration that is not substrate sensitive.
In accordance with the present invention, a process for fabricating GaAs FETs with an ion implanted channel layer includes the steps of providing a semi-insulating GaAs substrate; implanting n-type ions through a surface of the substrate to produce an n-type active layer in the substrate; capless annealing the substrate under AsH.sub.3 overpressure in a non-reactive gas to a predetermined elevated temperature sufficient to remove substantial amounts of ion implantation damage in the substrate and to electrically activate the active layer, the overpressure being approximately 100 times that of the equilibrium As.sub.4 pressure of the GaAs at the aforementioned elevated temperature. The process also includes the steps of depositing source and drain ohmic contract metalizations on the surface of the substrate in spaced relationship; removing a relatively shallow portion of the outer surface of the substrate in the active layer intermediate the source and drain contact metalizations for a gate electrode contact; and depositing a gate metalization in the shallow removed portion.
The substrate may also be provided with a high resistivity buffer layer into which the n-type ions are implanted. The ions may be implanted with energy between 80 to 140 KeV and a dose between 4.times.10.sup.12 ions/cm.sup.2 to 7.times.10.sup.12 ions/cm.sup.2 fluence. Further, the annealing temperature may be between 820.degree. to 890.degree. C., and the gate electrode recess in the outer surface of the active layer between 400 to 800 .ANG. deep.
The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The present invention, both as to its organization and manner of operation together, with further objects and advantages thereof, may best be understood by making reference to the following description taken in conjunction with the accompanying drawings in which like reference characters refer to like elements in the several views.
Brief Description of the Drawings
FIGS. 1a through 1c illustrate a preferred process sequence according to the present invention; and
FIG. 2 is a graphic representation showing a comparison of electrical profiles comparing a capped implant with the capless implant process according to the invention.
Detailed Description of the Invention
Referring now to the drawings and more particularly to FIGS. 1a through 1c, there is shown in FIG. 1a a semi-insulating GaAs substrate or an undoped high resistivity buffer layer over a GaAs substrate 11 wherein an ion implanted channel layer 13 of approximately 1200 .ANG. deep has been provided in the upper area of the substrate 11. Disposed on the upper surface 15 of the substrate is a source ohmic contact or electrode 17 and a spaced drain ohmic contact or electrode 19.
The implanted GaAs channel layer 13 is provided in the substrate by conventional ion implantation of n-type ions such as silicon or sulfur ions from about 60 KeV to about 140 KeV, and a dose between 3.times.10.sup.12 ions/cm.sup.2 to about 7.times.10.sup.12 ions/cm.sup.2, to a depth of about 0.1 .mu.m/100 KeV.
The substrate 11 is then placed in an annealing furnace without a conventional cap layer of SiO.sub.2 wherein it is heated to a temperature between 800.degree. and 1000.degree. C. for about 20 to 30 minutes. The substrate is annealed in an ambient mixture of arsine gas (AsH.sub.3) and flowing H.sub.2, where the arsine p=0.021 atm. This value is an overpressure of about 100 times greater than the equilibrium As pressure at the annealing temperature. The annealing step helps remove lattice damage and increase electrical activity in the ion implanted region and prevent the dissociation of As.sub.4 outdiffusion from GaAs without any stress effect as seen in the prior art cap annealing method.
Once source and drain contact metalizations 17 and 19 have been alloyed into the substrate surface 15, the surface between these metalizations is recess-etched a relatively small amount, of the order of 400 to 800 .ANG., as shown in FIG. 1b. This shallow recess 25 provides for higher device yield than that obtainable using a relatively deeper recess. Also, this configuration provides greater uniformity relative to drain-to-source current, and further enhances microwave performance over that obtainable in devices having relatively deeper recesses.
Finally, a gate ohmic contact 27 is deposited in the recess 25, as shown in FIG. 1c. In this embodiment, the gate is aluminum defined by direct write E-beam and its length is about 0.5 .mu.m, while the gate width is about 300 .mu.m.
The above-described process produces a GaAs FET structure exhibiting an electrical profile such as shown at curve 31 in the graph of FIG. 2. This characteristic is compared with that of SiO.sub.2 capped structure otherwise processed in a similar manner, represented by curve 33. Both structures used 100 KeV 7.times.10.sup.12 ions/cm.sup.2 Si+ implants in GaAs upon respective capless and SiO.sub.2 capped annealing, as described previously. It can clearly be seen that the slope of curve 31 is equal to 550 .ANG., while curve 33, representing the capped structure, has a slope equal to 1040 .ANG..
From the foregoing, it should be evident that the invention provides a high yield method for manufacturing GaAs FETs having uniform RF and DC, and very low-noise characteristics. Also, the inventive technique is suitable for large scale production of GaAs FETs having noise figure averages around 1.6 dB and 10 dB associated gain at about 12 GHz.
Claims
What is claimed is:
1. A process for fabricating a GaAs FET with ion implanted channel layer including the steps of: (a) providing a semi-insulating GaAs substrate; (b) implanting n-type ions through a surface of said substrate to produce an n-type active layer in said substrate; (c) capless annealing said substrate under AsH.sub.3 overpressure in a non-reactive gas to a predetermined elevated temperature sufficient to remove substantial amounts of ion implantation damage in said substrate and to electrically activate said active layer, said overpressure being approximately 100 times that of the equilibrium As.sub.4 pressure of said GaAs at said elevated temperature; (d) depositing source and drain ohmic contact metalizations on said surface of said substrate in spaced relationship; (e) removing a relatively shallow portion of the outer surface of said substrate in said active layer intermediate said source-and-drain contact metalizations for a gate electrical contact; and (f) depositing a gate metalization in said shallow removed portion.
2. The process for fabricating a GaAs FET according to claim 1, wherein said non-reactive gas is H.sub.2.
3. The process for fabricating a GaAs FET according to claim 1, wherein said gate metalization is aluminum.
4. The process for fabricating a GaAs FET according to claim 1, wherein the depth of said relatively shallow portion is approximately 400 .ANG. to 800/.ANG..
5. The process for fabricating a GaAs FET according to claim 1, wherein said predetermined temperature is between about 800.degree. C. and 1000.degree. C.
6. The process for fabricating a GaAs FET according to claim 1, wherein the partial pressure of said AsH.sub.3 equals about 0.021 atm.
7. A process for fabricating a GaAs FET with ion implanted channel layer including the steps of: (a) providing a semi-insulating GaAs substrate; (b) providing an undoped high resistivity buffer layer over said substrate; (c) implanting n-type ions through a surface of said buffer layer to produce an n-type active layer in said buffer layer; (d) capless annealing said buffer layer and said substrate under AsH.sub.3 overpressure in a non-reactive gas to a predetermined elevated temperature sufficient to remove substantial amounts of ion implantation damage in said buffer layer and to electrically activate said active layer, said overpressure being approximately 100 times that of the equilibrium As.sub.4 pressure of said As at said elevated temperature; (e) depositing source-and-drain ohmic contact metalizations on said surface of said buffer layer in spaced relationship; (f) removing a relatively shallow portion of the outer surface of said buffer layer in said active layer intermediate said source-and-drain contact metalizations for a gate electrical contact; and (g) depositing a gate metalization in said shallow removed portion.
8. The process for fabricating a GaAs FET according to claim 7, wherein said non-reactive gas is H.sub.2.
9. The process for fabricating a GaAs FET according to claim 7, wherein said gate metalization is aluminum.
10. The process for fabricating a GaAs FET according to claim 7, wherein the depth of said relatively shallow portion is approximately 400 .ANG. to 800/.ANG..
11. The process for fabricating a GaAs FET according to claim 7, wherein said predetermined temperature is between about 800.degree. C. and 1000.degree. C.
12. The process for fabricating a GaAs FET according to claim 7, wherein the partial pressure of said AsH.sub.3 equals about 0.021 atm.
Patent Citations (6)
Non-Patent Literature (1)
- Kasahara et al., "Capless Anneal of Ion-Implanted GaAs in Controlled Arsenic Vapor, J. Appl. Phys., 50 (1), Jan. 1979, pp. 541-543.