Image Scanning Method and Device

The invention relates to image scanning methods and devices, which can be used for producing an image signal indicative of the intensity, in particular light intensity, of adjacent points of the image, from sampling signals produced by detecting means displaced over the image.

Two types of rasters are known and used in image scanning, the orthogonal raster, where the pictures elements are sampled along two axes at right angles to each other, forming substantially square cells, and the hexagonal raster, with three axes at 60 degrees, forming hexagonal cells. The theoretical literature presents many advantages for hexagonal scans compared to orthogonal scans for certain types of image processing problems, but this scanning is not used in practice. Up to now no convenient means exists for generating hexagonal scans.

In known orthogonal scans, linear solid state arrays of photodetectors are commonly used. The scan direction orthogonal to the linear array, called the column array, is supplied by a translation of the array relative to the scanned medium in the direction orthogonal to the column. By scanning down the column repeatedly the image of the medium is dissected into the required array or raster. The relative motion between the array and the medium can be obtained by an actual physical displacement of one of them with respect to the other or by rotating mirrors, prisms, etc.

It is the object of the present invention to supply a means whereby a hexagonal raster can be generaed by the use of a column array of photodetectors, due to the use of such arrays consisting of two interdigitated series of photodetectors, namely the even and the odd half columns, each with separate clock-sampling pulses, reset circuits, and outputs. It is also an object of the present invention to supply an improved design for such arrays.

The invention will be further explained by means of the appended diagrams, wherein:

FIG. 1 is the block diagram of the apparatus for generating the hexagonal raster,

FIG. 2 shows the detail of one of the circuit blocks,

FIG. 3 shows the timing diagrams of the various control signals in the circuit,

FIG. 4 represents the resulting scan patterns,

FIG. 5 presents the detailed geometrical relations existing in the hexagonal scan generator,

and FIG. 6 shows the design of an improved array of solid-state photodetectors.

FIG. 1 is the block diagram of the apparatus for generating the hexagonal scan. It consists of a counter 1, generating successive binary codes from the clock pulse A, a control signal and address decoder 2, the photodetector array 3, an analog-digital converter 4 (A/DC), and storage means 5 consisting of a known random access memory (RAM). The raster output is taken from the RAM 5.

The operation of the circuit will be explained hereinafter with specific reference to an array comprising 16 aligned detecting elements, i.e. 8 even and 8 old elements, but the same principles are valid as well for arrays of any number of elements and the modification necessary for a particular case will be obvious to an expert.

The counter will have a number of states at least equal to the number of photodetectors in the array. It will advance through these states in sequence under the action of the input clock pulse A. The various contron signals and RAM addresses required for the correct operation of the system will be obtained from the control signal and address decoder 2 whose inputs are the individual state signals at the output terminals of the counter and whose outputs are the required control signals and addresses. The control signals for the photodetector array 3 are the reset pulses for the even (R.sub.E) and odd (R.sub.0) half column arrays, the clock and output sampling pulses for the even (S.sub.E) and odd (S.sub.O) half column arrays, the RAM address code H, and the RAM read/write control pulse I. The two output terminals of the photodetector array 3 are tied together and supply the input to the A/DC whose output is the data input to the RAM G. The RAM output is the bus J.

The operation of the system will be clarified by means of the following table and FIG. 3, the timing diagram reflecting the relationships implied by the table.

In this table the binary code corresponds to the states of the counter outputs A.sub.5 A.sub.4 A.sub.3 A.sub.2 while the write/read columns list the positions of the elements in the photodetector array whose sampled and digitised data are written into or read out of the RAM during the time that the given counter state is valid. Referring to FIG. 3, we see that a read operation takes place after a write operation.

The state of the sampled photodiode appearing at the output terminal F of the array 3 is first digitised by the A/DC 4 before being written into the RAM 5. The number of bits to which the signal is digitised will depend on the particular application, and may be as little as 1 bit, obtained by a simple black/white threshold operation or may be as much as 8 for good quality photodiode arrays. To allow for digitising time, the sampling times S.sub.E and S.sub.0 precede the write times W.sub.E and W.sub.0 by one half sampling period.

The examination of the table and FIG. 3 also shows that the even and odd photodetectors are sampled, digitised, and written to RAM alternately, while the odd samples are read out in sequence, followed by the even samples. If the number of elements in the photodetector array is 2.sup.n, during each period of 2.sup.n clock pulses A.sub.1 the entire photodetector array shall have been sampled, each element once, an even and an odd elements being sampled in alternation, and the samples read out in trains of 2.sup.n-1, first the train of 2.sup.n-1 odd samples, then the train of 2.sup.n-1 even samples.

It will also be observed that while the top, or first half of the even elements is being sampled, the bottom, or last half of the odd elements is being sampled, and vice versa. Thus element 9 is sampled directly after element 0 and element 1 directly after element 8. An examination of the binary codes corresponding to the even elements shows that if the elements 0,2,4,6,8,10,12,14, are renumbered 0,1,2,3,4,5,6,7, that is, are numbered from 0 to 7 in order, then the corresponding binary numbers will be found by taking the three high-order bits of the binary code that is output from the counter when the data from the corresponding sample are to be written to RAM, while the corresponding binary numbers will be found by taking the three low-order bits from the binary code that is output from the counter when the corresponding data are to be read out of the RAM. Similarly, renumbering the elements 1,3,5,7,9,11,13,15, by 0,1,2,3,4,5,6,7, we find the same relationship for the readout of these data. However, for the write of these elements, we find that the high-order bit is inverted. This is due to the fact that the bottom half of the odd half column of photodetector elements is sampled during the first half of the cycle, when the top half of the even half column is being sampled, and vice versa. This enables us to construct partial address codes for the odd and even data sequences for storage and readout from RAM in the correct sequence. It is further necessary to supply one bit that will separate the odd and even data into separate zones of the RAM. During the write cycles this additional bit will be A.sub.2 which takes on opposite polarities during even and odd write cycles, and for the read cycles this will be A.sub.5. We assign the code A.sub.5 A.sub.4 A.sub.3 A.sub.2 to the even elements when they are being written to RAM and the code A.sub.4 A.sub.3 A.sub.2 AHD 5 when they are being read out, the code AHD 5A.sub.4 A.sub.3 A.sub.2 to the odd elements on write and A.sub.4 A.sub.3 A.sub.2 AHD 5 on read. This will have the effect of assigning even elements to even RAM addresses and odd elements to odd RAM addresses. It is understood that these address codes are the concatenation of the corresponding bits output from the counter and not the logical product of the designated variables, where the bits take on variables.

FIG. 2 represents the detailed block diagram of the address decoder which forms part of the control signal and address decoder 2. The output variables of the counter A.sub.2,A.sub.3,A.sub.4 A.sub.5 are connected as shown to the inputs of multiplexers 21, 22, 23, 24, where the multiplexer 21 is a 4-way multiplexer and multiplexers 22, 23, 24 are 2-way multiplexers. Variable A.sub.5 is input in direct polarity to one input of multiplexer 21 and inverted to a second input of multiplexer 21 and to one input of multiplexer 24. The control inputs to the multiplexers are A.sub.1 to all the multiplexers and A.sub.2 to the second input of multiplexer 21. When A.sub.1 =1 the left inputs are switched to the outputs and when A.sub.1 =0 the right inputs. This controls the shift from high-order to low-order variables for the address codes between writing and reading in RAM. When A.sub.2 =0 the noninverted input of A.sub.5 is connected to the output of multiplexer 21 if A.sub.1 =1 and when A.sub.2 =1 the inverted input of A.sub.5 is connected to the output of multiplexer 21 if A.sub.1 =1. This controls the inversion of A.sub.5 when an odd sample is being written to RAM.

The other control signals are given by the following table, where the strings of variables here are taken in the sense of logical AND gate functions.

R.sub.E =AHD 1A.sub.2 A.sub.3 A.sub.4 A.sub.5

R.sub.0 =AHD 1AHD 2AHD 3AHD 4A.sub.5

S.sub.E =AHD 1A.sub.2

S.sub.0 =AHD 1A.sub.2

C.sub.E =R.sub.0

C.sub.0 =AHD 1AHD 2AHD 3AHD 4AHD 5

where the meanings of these control signals are defined in FIG. 3.

The geometrical effect on the resulting raster is represented in FIG. 4. FIG. 4(a) shows the geometrical arrangement of samples taken during the first half period. Since the sample from the odd element 9 is taken immediately after the sample from the even element 0 the relative motion between the scanning array and the scanned medium is very small during this time and the two samples are in effectively the same vertical column on the medium. For each successive even-odd sample pair the medium has moved slightly with the result that each successive pair is displaced by the same amount. Assuming that the relative motion of the scanning array with respect to the medium is from left to right, the result will be as shown in FIG. 4(a). Similarly, during the second half period we obtain the arrangement shown in FIG. 4(b). The entire pattern over several columns is shown at FIG. 4(c). We see that the relative motions and the scanning arrangements are such that the odd and even half columns form the spatial arrangement corresponding to a staggered scan. The slight motion between the scanning head and the scanned medium between successive odd and even samples is just the amount necessary for these samples to occur at the right positions for this staggered scan.

The geometrical relationships occuring between the centers of sampled elements in consective half columns is represented in FIG. 5. If the relative velocities of the scanning head and the scanned medium is such that the distance travelled between successive columns is given by

then the centers of the scanned samples will correspond to the center of the hexagons in a hexagonal raster. A small error will be present if the scanning array is aligned perfectly perpendicular to the direction of relative motion between head and medium, since the effective columns will be titled at an angle whose tangent is .DELTA.x/2.sup.n. Since the least value of 2.sup.n of practical interest is 128, this error is less than one half degree. While this error is insignificant compared to the other sources of error in the system, including the fact that the samples are not true hexagons it can be reduced to a theoretical value of zero by tilting the photodiode array in the opposite direction by the corresponding amount without altering the arrangements described here.

It will be appreciated that the circuit represented in FIGS. 1 and 2 and described here is given by way of example and the designer may make modifications as a function of available microcircuits and technology and the well known tradeoffs between cost and performance. As an example, the control signal and address generator 2, represented in part in FIG. 2, can be implemented by a single ROM (read-only memory) which contains at successive addresses the successive control signals and addresses required for the correct operation of the system. In this case the counter will have to have 2.sup.n+1 states, since this is the number of discrete clock times as may be seen from FIG. 3. Other modifications will be evident to the designer without altering the basic invention as described here.

The principle of interdigitated half arrays can be used to construct a solid-state photodetector array that will furnish a true hexagonal scan, thereby eliminating the defects noted with reference to FIG. 5, and enabling a substantial simplification of the control and readout circuitry. This embodiment of the invention will now be explained with reference to FIG. 6, taking the well-known CCD (Charge-Coupled Device) technology as the basis. In the known COD photodetector arrays, as in the MOS photodiode arrays, the arrangement of the photodetector has been as noted above, a single row of square or rectangular cells. In the device constructed according to the invention the two interdigitated half-columns are offset, in the manner shown in FIG. 6, and the cells given the hexagonal shape represented in the drawing. For example, elements 100, 101, 102, 103 will be part of the even half column, and elements 104, 105, 106, 107 will be part of the odd half columns. The hatched area 108 represents the serpentine channel stop as required for the correct functioning of CCD devices in one implementation. It will be appreciated that this arrangement has the double advantage of larger photodetector elements for the same length of semiconductor, while making the connection to each half-column simpler to lay out, more room being offered between elements of the same half-column. It will likewise be appreciated that all of the timing and control devices required in the above-described embodiment, using standard components, can be integrated onto the same semiconductor substrate (chip) as the photodetector array.

In particular, the transfer between photodetector elements 100-103 and the output transfer line elements 200-203, on the one hand, and the photodetector elements 104-107 and the output transfer line elements 204-207 on the other hand, is simultaneous, as in existing line arrays, while the readout from the line 200-203 is consecutive and complete before the readout from the line 204-207, which is consecutive and complete before the next simultaneous transfer operation, thus complying with the requirements of sequences J.sub.E and I.sub.O of FIG. 3.

It will be obvious to a person of the art that the same principle can be applied to the other class of solid-states monolithic photodetector array, the MOS photodiode array.