Closed-Loop Frequency Regulated Generator Apparatus

The present invention relates to apparatus for the regulation of speed and frequency, in general, and more particularly to uninterruptible power supply (UPS) motor drives and/or electrical generators operable at a fixed frequency.

The present invention will be described more specifically in the context of a motor-generator set in which a separately excited DC machine is coupled to a synchronous AC machine for the generation of AC current of a standard frequency, for instance, 60 Hertz. This type of generator is particularly suitable for the power supply of a ship where a DC power grid is available which needs to be tied to an AC power grid for interconnection with transfer of power in either direction. This is the situation encountered when a motor-generator set is used as a standby, which can, in an emergency, be introduced to provide auxiliary AC power at a fixed frequency on the AC grid, in the absence of any generator of sufficient capacity to impose a reasonably constant frequency all the time. The fixed frequency, for instance 60 Hertz, is maintained by adjusting the speed of the DC machine coupled to an AC generator which is a synchronous machine. The constancy in frequency of the generator thus depends upon the degree of accuracy in the speed regulation of the motor. Frequency adjustment is obtained with a frequency representative feedback signal compared with a speed reference signal to compensate for any error.

Two approaches have been used in the past to generate such a feedback signal. One has been to convert frequency into voltage. The frequency to voltage (F/V) converter then becomes a crucial element in achieving regulation with accuracy. Any error introduced by the F/V converter cannot be corrected by the closed loop regulator. This raises a problem when the implementation of a F/V converter requires various inductor-capacitor networks, since they are difficult to manufacture with a high degree of accuracy and are sensitive to temperature.

Another approach has been to make use of an accurate time base, such as provided by a crystal oscillator, to measure the period of the AC line, e.g., the inverse of the frequency. However, when so doing, the prior art has used digital techniques requiring signal conversion into analog for the purpose of comparison with the AC period. Here also, like with the frequency-to-voltage converter, the digital-to-analog converter is a source of error.

The present invention allows for the use in a closed-loop of both analog reference setting and analog feedback, while taking advantage of digital techniques.

The present invention makes use of a dual slope converter to derive the error in frequency. The measurement cycle is defined by the time period of the AC output to be regulated and the accumulated charge is obtained by integration in relation to the regulation setpoint under a precise time interval. Advantage is taken of the fact that any variation, or drift, affecting the gain during the charging step is automatically compensated during the discharging step of the dual slope converter.

FIG. 1 shows a speed regulator system for a motor-generator set according to the prior art using a frequency-to-voltage converter;

FIG. 2 provides a schematic representation of the circuit used according to the present invention for the derivation of a corrective control signal in the speed regulator system;

FIG. 3 is a diagram illustrating with electrical components the circuit according to a preferred implementation of the invention; and

FIG. 4 groups curves explaining the operation of the circuit of FIG. 3.

Referring to FIG. 1, at a location remote from the motor-generator set MG, potentiometers P.sub.1 and P.sub.2 are used to adjust the setpoint for a frequency regulator FR controlling the field winding FW of a DC motor M driving a synchronous generator G. From the three-phase output lines (A, B, C) of the generator is derived the line-to-line voltage V.sub.AB and such feedback signal is applied on line 1 to a frequency-to-voltage (F/V) converter, FV outputting on line 5 a frequency representative signal (frequency f.sub.0). Potentiometer P.sub.1 under a potential source V.sub.R provides a frequency setpoint (f.sub.sp) signal applied from the moving arm on line 2 to the adder ADD. Potentiometer P.sub.2 under a voltage between its two ends C, D, which represents real power, provides a droop characteristic signal (f.sub.D) which is applied from the moving arm on line 3 to the adder ADD. The resulting combined signal (f.sub.*) on line 4 is used as a reference frequency signal. The signals of lines 5 and 4 are compared by a subtracter CMP to generate an error signal .DELTA. f on line 6 to the field regulator FR, e.g., the frequency error signal of line 6 will drive the field regulator to determine the output frequency in relation to the setpoint reference of line 4. However, any error inherent in the operation of F/V converter FV will affect the magnitude of the f.sub.0 signal of line 5 which otherwise should be proportional to the output frequency.

Referring to FIG. 2, it is now proposed to generate an error signal shown as .DELTA.f on line 6, without the use of a frequency signal, while taking advantage of a precise time signal, such as obtained with a crystal oscillator, to relate the amplitude of the correction signal to the period of the AC output. This is achieved with a dual slope converter typified in FIG. 2 by an integrator INT and a time basis circuit providing a charging time and a discharging time for the integrator which are determined by a timer TM. The charging time defined by the timer is T.sub.r provided by a precision one-shot multivibrator, e.g., a crystal oscillator, and T.sub.r is controlling switch S.sub.1 applying to the integrator during such time T.sub.r a signal derived from the setpoint potentiometer P which is analogous in FIG. 2 to the two potentiometers P.sub.1, P.sub.2 combined of FIG. 1. The signal of line 4 from potentiometer P is inverted by a unity gain operational amplifier A.sub.2 and the outputted negative signal on line 11 is passed by switch S.sub.1 via a resistor R.sub.2 onto the inverting input of the operational amplifier A.sub.3 of the integrator INT. Amplifier A.sub.3 includes a capacitor C between output and input as generally known and which according to the present invention is charged during T.sub.r and discharged during T.sub.0 -T.sub.r), as illustrated by curve (c) of FIG. 4 hereinafter. If the integral of the setpoint signal magnitude on line 11, weighted by resistor R.sub.2, applied during fixed time interval T.sub.r matches exactly the integral of the signal on line 14, weighted by resistor R.sub.1, applied during time interval (T.sub.0 -T.sub.r), capacitor C is totally discharged at the end of T.sub.0. Otherwise it will either not be completely discharged and a remaining positive charge will be detected at the output 12 of the integrator, or it will have come, negatively, past the discharging cross-over point and a negative voltage will be detected at the output 12. The error voltage represents a period error (T.sub.0 '-T.sub.0)=.DELTA.T which is a frequency error to be compensated by the field regulator FR (see FIG. 1) in order to match the controlling setpoint signal of line 4.

The determination of (T.sub.0 -T.sub.r) is obtained, as shown by FIG. 2, by applying a time interval T.sub.0 characteristic of the period and defined between cross-over points of the AC wave on line 1 detected by a pulse shaper symbolized in FIG. 2 by an amplifier A.sub.1. Times T.sub.r and T.sub.0 are initiated at the same instant, T.sub.r being defined by clocking from amplifier A.sub.1 the one-shot multivibrator of timer TM synchronously with the occurrence of a crossover point. During time T.sub.r switch S.sub.1 is closed and amplifier A.sub.3 sees a net negative input signal on line 10, which is the sum of the negative setpoint signal on line 11, weighted by resistor R.sub.2, and a signal due to the positive potential source V.sub.R on line 14 weighted by resistor R.sub.1. Resistor R.sub.2 is chosen to be substantially smaller than R.sub.1 so that the input from line 11 predominates over the effect of source +V.sub.R. When, however, switch S.sub.1 is open, only the positive potential source V.sub.R via resistor R.sub.1 is effective, thereby initiating a discharging step for integrator INT. Such discharging step will last until period T.sub.0 has expired, namely, when another cross-over point from line 13 will short-circuit the integrator and trigger another time period T.sub.r.

At the moment T.sub.0 expires, the dual slope converter of FIG. 2 will sample and hold any error appearing on line 12 and will quickly reset capacitor C to zero, thereby preparing for another charging-discharging cycle. Assuming integrator INT has been zeroed initially, the output after one line period T.sub.0 is a voltage .DELTA.e such that ##EQU1## where k is a coefficient defining the setting of potentiometer P.

When the setting of P matches T.sub.0, e.g., the frequency, the integrator output is zero and equation (1) becomes ##EQU2## The gain of the detector is the derivative of equation (1) with respect to T.sub.0. Then, ##EQU3##

From equation (1) it appears that any variation of V.sub.R will affect equally both sides of the subtraction, therefore will not affect .DELTA.e. This is a well known advantage of the dual slope converter.

Equation (2) indicates that the setpoint stability i.e., the regulating point with potentiometer P.sub.1, depends only on the ratio of R.sub.1 /R.sub.2, the pulse width T.sub.r of the precision one-shot multivibrator used in timer TM, and the desired setpoint k. All these can be made stable very easily. Equation (3) shows that the gain of the dual slope converter depends upon C and the supply voltage. Even if these quantities vary somewhat more than T.sub.r and R.sub.1 /R.sub.2, this will not seriously affect the measurement .DELTA.e, because gain variation is not as crucial as setpoint variation.

The output of the integrator must be sampled and held when T.sub.0 expires and the integrator must be reset for the next line cycle very quickly.

Referring to FIG. 3, the implementation of the invention is illustrated with hybrid analog-digital circuitry, as follows.

The time interval T.sub.0 between two consecutive zero-crossings in the same direction is identified by two successive reset pulses from lines 31 to 34 (see curve (e) of FIG. 4). Each reset pulse terminates the current time interval T.sub.0 ad initiates both the fixed time interval T.sub.r and the next time interval T.sub.0 (see curves (c) and (d) of FIG. 4). The control signal T.sub.r is generated by counter U8 which, when clocked by line 37 from counter U6, initiates T.sub.r, and by line 39 disables itself immediately following T.sub.r. U8 remains disabled until reset by line 34 at the end of T.sub.0. As long as the signals of lines 38, 44, 47 are zero the setpoint voltage of line 11 weighted by resistor R.sub.2 acts, by switch U9A to modify the charging rate of the integrator. Switch U9A is gated ON by NOR device U1B which responds on lines 47, 44 and 38 to respective signals Q.sub.0, Q.sub.1 and T.sub.r. The output of U1B, line 51, is a ONE when neither line at the input has a ONE. During T.sub.r line 38 has a zero. During time T.sub.r the reference voltage V.sub.r on line 14 weighted by resistor R.sub.1 acts through switch U9B to modify the charging rate of the integrator. Switch U9B is gated on by NOR device U1C which responds on lines 42 and 43 to signals Q.sub.0 and Q.sub.1, respectively. Time T.sub.r is the charging period of the integrator when capacitor C is charging up except during time intervals (t.sub.1, t.sub.2) and (t.sub.2, t.sub.3) when Q.sub.0 and Q.sub.1 have a ONE, respectively (see curves c, f, e, j).

The carryout signal of line 36 from counter U6 is applied to the clock pin of another counter U7, outputting on line 42 at its Q.sub.0 output a square pulse of 20 microseconds duration. Counter U7 generates on line 43 at its Q.sub.1 output a square pulse of 20 microseconds immediately following the end of the square pulse of Q.sub.0, and by line 41 from its pin Q.sub.2, counter U7 disables itself immediately following Q.sub.1. Time interval defined by Q.sub.0 is used to sample the error outputted by the integrator, whereas the consecutive time interval defined by Q.sub.1 is used to reset the integrator. Sampling is achieved by applying the signal Q.sub.0 of line 42 to the gate pin line 46 of switch U9D in line 22 to the sample and hold device A.sub.5. Resetting is performed by applying the signal Q.sub.1 of line 43 to the gate pin line 43 of switch U9C, thereby shortcircuiting the connection between output junction J.sub.5 and input junction J.sub.1 of the integrator A.sub.3.

From setpoint potentiometer P.sub.1 and from droop adjust potentiometer P.sub.2, lines 2 and 3, respectively, join at J.sub.2 on the inverting input of an operational amplifier A.sub.2 providing on line 11 an inverted signal which is used to charge, via resistor R.sub.2 and line 10 the integrator INT once switch U9A has been closed. Positive potential source V.sub.R by line 14 is applied via resistor R.sub.1 to the same inverting input of A.sub.2, at junction J.sub.1 with line 10, provided switch U9B is closed. The integrator built around operational amplifier A.sub.3 outputs on line 20 a voltage signal representative of the charge on capacitor C.sub.1, connecting output junction J.sub.5 to input junction J.sub.1. Capacitor C.sub.1 is reset to zero when short circuited between J.sub.5 and J.sub.1 by switch U9C. The output of the integrator is passed from line 20 to line 22 at the non-inverting input of a sample and hold operational amplifier A.sub.5, provided switch U9D is closed between line 20 and line 22 to set capacitor C.sub.2 to the voltage of J.sub.5. The sampled error .DELTA.T is outputted on line 12.

The AC line voltage feedback on line 1 is applied to a cross-over detector comprising a squarer built around a comparator operational amplifier A.sub.1 and a pulseshaper PS comprising: a differentiating capacitor C.sub.5 (value 0.001 .mu.f) in line at the output; a source (+V.sub.R) applied via the parallel network of a diode D.sub.1 and a resistor (1 k.OMEGA.); and a NOR device U1A. The input to A.sub.1 is a heavily filtered sample of the AC bus voltage. Each time there is a cross-over in the same direction, a 1 .mu.s digital pulse will appear on line 31 at the output of NOR device U1A. Each pulse is one period apart, e.g., T.sub.0 away. A crystal oscillator OSC built around an operational amplifier A.sub.4 with a crystal CTL of a period of 500 kHertz generates on line 35 a series of clock pulses which are 2 .mu.s apart. The clock signal is applied by line 35 to the clock pin of a decade counter U6 which begins to count on the next positive clock pulse following each reset pulse applied by lines 31 and 32 to its R pin. The clock crystal oscillator (CTL) frequency of 500 Hz provides a maximum 2 .mu.s time duration from the end of the reset pulse on line 32 to the start of counter U6. This minimizes the variation in T.sub.0 due to the lack of synchronization of the crystal oscillator with the line frequency. Counter U6 having effected a divide by 10 operation on the clock signal of line 35, the clock signal on line 36 has a 20 microsecond period.

The time interval T.sub.0 between two consecutive zero-crossings in the same direction is detected by the zero-crossing detector generating on lines 31-34 successive pulses applied to the reset pin of counters U6, U7 and U8 (see curve (b) of FIG. 4). Each pulse initiates both the fixed time interval T.sub.r generated by counter U8, which resets itself at the end of T.sub.r by line 39, and the period characterizing time interval T.sub.0 which is generated by the combination of counters U6, U7. The reset pulse also indicates the termination of time interval T.sub.0 (see curves (c) and (d) of FIG. 4).

In contrast with the prior art, the dual slope converter according to the present invention is not used as a measuring instrument. The detected error of line 12 (see curve (c) of FIG. 4) is applied to a frequency corrective circuit which is part of the closed loop in which the dual slope converter is inserted. An operator reads on a frequency meter the actual frequency outputted by the system and manually adjusts the setpoint on potentiometer P.sub.1 until the error of line 12 has led to the correct frequency, typically 60 Hertz. Once this is achieved, the error on line 12 has been nullified and the duration T.sub.0 matches exactly the desired frequency imposed by the setpoint.

Accordingly, the dual slope converter is modified in order that the conventional sample and hold, as well as resetting steps, do not interfere with the closed loop control operation. Therefore, referring to FIG. 4 and curve (j) the steps of detection and zeroing of the error signal dT of line 12 are taken at a precise occurrence after the occurrence of the cross-over point (t.sub.0) of the line frequency signal, line 1, typically after one counting period has lapsed after triggering of switch U6, namely, when the time interval defined by Q.sub.0, e.g., (t.sub.1 -t.sub.2) of line 42 is initiated. As a result, due to the added time in discharging C, the error which occurs at time t.sub.0 is somewhat in want (if the error is positive) or in excess (if the error is negative). However, the charging step is initiated at time t.sub.3 at the end of another counting period defined by switch U7 on line 43, thus, after a total delay defined by Q.sub.0 and Q.sub.1, e.g., (t.sub.1 -t.sub.3). This delay, which adds up the sampling and reset periods, extends between the discharging step (ending at t.sub.1) and the charging step (starting at t.sub.3). It is taken up from the true period T.sub.0 which determines the error dT of line 13. This measurement error, though, by reducing somewhat the charging time is in the opposite direction relative to the earlier mentioned measurement error due to time interval t.sub.0 -t.sub.1, which makes the discharge step somewhat longer. Accordingly, these measurement errors compensate each other to a certain extent. Moreover, each of these time intervals (t.sub.0 -t.sub.1), (t.sub.1 -t.sub.2) and (t.sub.2 -t.sub.3) are of the order of 20 microseconds, whereas the charging time is of the order of 5 milliseconds, and the total time T.sub.0 is about 16 milliseconds (for 60 Hertz). Therefore, the value of dT on line 12 is only very slightly affected. This is an extremelly small discrepancy in the operation of the dual slope converter, which is a small price to pay for accuracy in using T.sub.r and T.sub.0 for closed-loop control since, as opposed to the conventional use of a dual slope converter as an error measurement device, this is the contemplated field of application of the invention.

Referring to FIG. 4, when OSC circuit generates pulses which are 2 .mu.s apart, counter U6 effects a division by 10, and counter U8 effects division by 256, which leads to pulses on line 38 which are 5.12 milliseconds apart. With an integrator including a capacitor C of 0.022 microfarad and resistors R.sub.1 =267K and R.sub.2 =150K.OMEGA., the time constant is such that for the setpoint chosen for 60 Hertz, it takes 16.67 milliseconds to charge and discharge completely the capacitor since T.sub.0 corresponds to 60 Hertz, e.g., 16.67 milliseconds exactly. Actually as earlier mentioned, the total time T.sub.0 is not used in the process, since a time (t.sub.1 -t.sub.2) or (t.sub.2 -t.sub.3) of 20 microseconds is taken out, while discharging is postponed by 20 microseconds (t.sub.0 -t.sub.1) and charging is also postponed by 20 microseconds, e.g., (t.sub.2 -t.sub.3) or (t.sub.1 -t.sub.2). The charging period is defined by line 38 during T.sub.r when the signal of line 38 is a zero, when Q.sub.0 is a zero on line 42 and Q.sub.1 also is a zero on line 43, whereby NOR device U1B causes U9A to be closed and NOR device U1C causes U9B to be closed applying both the setpoint voltage line 11 and the reference voltage line 14 to the integrator.

The discharging period is initiated when T.sub.r has expired and the signal of line 38 has become a ONE thereby causing switch U9A to disconnect. At the end of T.sub.0 junction J.sub.1 is disconnected from the potential source V.sub.R by switch U9B, when either Q.sub.0 or Q.sub.1 is a ONE. Discharging is terminated not at t.sub.0 but at t.sub.1 when the start of Q.sub.1 (end of the T.sub.0) causes, at time t.sub.1, switch U9D to be closed, at the input of the sample and hold circuit SH, for 20 microseconds (Q.sub.0, from t.sub.1 to t.sub.2). Then, the error dT of line 12 causes process control action to change T.sub.0. Capacitor C is short-circuited when Q.sub.1 on line 43 so controls switch U9C. Time T.sub.r, though, is not applied to the dual slope converter until time intervals t.sub.0 -t.sub.1, t.sub.1 -t.sub.2 and t.sub.2 -t.sub.3 have expired, namely when T.sub.r is defined by a zero into NOR device U1B on line 38 and zeroes at the inputs of NOR devices U1B and U1C on line 42 (Q.sub.0) and line 43 (Q.sub.1).

The solid state devices shown in FIG. 3 are illustrated as follows:

U1A, U1B, U1C are 4025B 3-input NOR gate devices;

U6 and U7 are 4017B series logic decade counters;

U8 is a 14-stage 4020 ripple carry binary counter;

U9A, U9C, U9D are CMOS gates 4066B quad bilateral switches;

A.sub.1, and A.sub.4 are LM139 operational amplifier devices used as comparators A5, A2 and A3 are LM108A operational amplifier devices.