Method for Reducing the Consumption of a Stepping Motor and Device for Performing the Method

This application is related to Ser. No. 426,316 filed Sept. 29, 1982, by the same applicants for Method and Device for Controlling a Stepping Motor of a Timepiece.

The present invention concerns a method for reducing the consumption of a stepping motor by automatically adapting the duration of each drive pulse supplied to the motor to the load that the motor is to drive.

The invention also concerns a device for controlling a stepping motor of a timepiece, for performing the abovementioned method.

A number of methods for reducing the consumption of a stepping motor have already been proposed.

French Pat. No. 2 200 675 for example proposes measuring the load which the motor is required to drive, by permanently measuring the current flowing in the winding of the motor when a drive pulse is applied to the winding and interrupting the drive pulse when the current passes through a minimum.

Detecting the minimum current value is difficult because of the parasitic noise which may be superimposed on the current measuring signal. This means that the known method is generally unreliable. In addition, when employed with some motors, and when the load which is to be driven by the motor becomes substantial, the current minimum disappears so that the known method can no longer be used.

The present invention aims to propose a reliable and sure method which is suitable for all types of motor and which permits the length of the drive pulse to be adapted to the load which the motor is required to drive.

The method according to the invention comprises producing, in the course of each drive pulse, a plurality of elementary interruption periods during which the power supply source is disconnected from the winding, and determining the mechanical load driven by the motor by measuring, during the interruption periods, a parameter which is representative of the variation in the movement induced voltage, that is to say, the voltage induced in the winding of the motor by the movement of the rotor.

The voltage U.sub.i which is induced in the winding of the motor by virtue of the rotary movement of the rotor depends on the speed of the rotor, and the variation in respect of time thereof depends on the load which is to be driven by the motor. It is therefore possible to determine the load to be driven, by measuring the variation in the movement induced voltage from the beginning of the drive pulse.

During the rotary movement of the rotor, the induced voltage U.sub.i rises, reaches a maximum and then falls in a different manner, depending on whether the load on the motor is low or high. In the first situation, the induced voltage rises and falls at moments which are closer to the beginning of the drive pulse, than in the second situation.

By detecting the time t.sub.1 at which the induced voltage reaches a suitably selected predetermined value U.sub.is and by measuring the period of time which elapses between the beginning of the drive pulse and the time t.sub.1, the result obtained is a measure of the variation of the induced voltage and therefore of the instantaneous value of the load driven by the motor. As that measurement operation is performed at the very moment that the drive pulse is applied to the winding of the motor, it is hence possible to regulate the length of the same drive pulse in dependence on the instantaneous value of the load, thus providing direct control.

The applicants have found that an optimum duration of the drive pulses, providing minimum consumption of the motor while guaranteeing that the rotor correctly terminates all its stepping movements, can be determined by measuring the period of time T.sub.d which elapses between the beginning of the drive pulse and the time t.sub.1, and by calculating for the total duration of the drive pulse, a value T.sub.opt =.lambda.T.sub.d +.DELTA. in which .lambda. and .DELTA. are constants which are determined experimentally for each type of motor and which are valid for all motors having the same electrical and magnetic characteristics.

The features and advantages of the invention will be better appreciated from the following description of a number of embodiments of the invention, with reference to the accompanying drawings in which:

FIG. 1 is an equivalent circuit diagram of a stepping motor,

FIG. 2 is a synoptic diagram of a control device in accordance with one embodiment of the invention,

FIG. 2a is a diagram showing a number of signals as measured in the FIG. 2 circuit,

FIGS. 3 and 3a are detailed circuit diagrams of a part of the device shown in FIG. 2, in two embodiments of the invention,

FIG. 4 is a detailed diagram of a second part of the device shown in FIG. 2, in one embodiment of the invention,

FIG. 4a is a diagram showing, in respect of time, the counting condition of the counter 27 shown in the circuit of FIG. 4,

FIG. 5 is a detailed diagram showing a third part of the device of FIG. 2, in accordance with an embodiment of the invention,

FIG. 5a partly shows the configurations of the current flowing in the winding of the motor and the signals measured at various points in the circuit shown in FIG. 5,

FIG. 6 is a detailed diagram of a fourth part of the device shown in FIG. 2, and

FIG. 6a is a diagram showing signals measured at various points in the circuit of FIG. 6, in respect of time.

FIG. 1 shows the equivalent circuit diagram of a stepping motor. The winding of the motor is represented by a winding 1 of inductance L and with a resistance of zero, and a resistor 2 whose resistance R is equal to the resistance of the winding of the motor. A rotor 1a which is diagrammatically indicated by its bipolar permanent magnet is magnetically coupled to the winding 1, 2 by a stator (not shown). The movement induced voltage, that is to say, the voltage which is induced in the winding of the motor by the rotary movement of the rotor is diagrammatically indicated in FIG. 1 by the voltage source 3. The value of the induced voltage is indicated by U.sub.i.

The power supply source for the motor is represented by a source 4 having zero internal resistance and producing an electromotive force V, and a resistor 5 of resistance R* equal to the internal resistance of the real source for supplying the motor.

Finally, in the circuit diagram shown in FIG. 1, the circuit for controlling the motor is diagrammatically indicated by a first switch 6 for connecting and disconnecting the source 4, 5 of the winding 1, 2 of the motor, and a second switch 7 for short-circuiting the winding or eliminating the short-circuited condition thereof.

Broadly, the currents and voltages involved in operation of the motor are given by the following relationship:

in which U.sub.m is the voltage at the terminals of the motor and i is the current flowing in the motor winding. When the switch is closed and the switch 7 is open, the voltage U.sub.m is equal to V-R*.multidot.i. During the drive pulse interrumption periods, the switch 6 is open and the switch 7 is closed. The voltage U.sub.m is therefore zero, provided that the internal resistance of the switch 7 is negligible, which is the case under practical circumstances. During the interuption periods, above-indicated equation (1) can therefore be written as follows:

If the interruption periods are of a duration T1 which is much shorter than the time constant .tau.=L/R of the winding, it may be assumed that ##EQU1## in which I.sub.a and I.sub.b are the values of the current i at the beginning and at the end of each interruption period.

Under these conditions, when L is replaced by R.multidot..tau., equation (2) can be written as follows: ##EQU2##

Equation (3) shows that the voltage U.sub.i induced in the motor winding by the rotary movement of the rotor may be determined in each interruption period, that is to say, in each period during which the power supply source is disconnected from the winding and the winding is in a short-circuited condition, by measuring the values I.sub.a and I.sub.b of the current at the beginning and at the end of each of the interruption periods, with the values R, T1 and .tau. being known.

In practice, there is no need to measure the voltage U.sub.i itself and compare it to a threshold voltage U.sub.is to determine the time t.sub.1. It is only necessary for example to determine the value of the term ##EQU3## in above-indicated equation (3), and to compare that value to a reference value .beta.=U.sub.is .multidot.1/R.multidot.T1/.tau..

The value of the term ##EQU4## may be determined by measuring and storing the value of the current I.sub.a at the beginning of the measuring period, multiplying the measured and stored value by a constant .varies.=.tau.-T1/.tau. which is known since .tau. and T1 are known, measuring the current I.sub.b at the end of the measuring period, and calculating the difference (.varies..multidot.I.sub.a -I.sub.b).

That difference is then compared to the value .beta., and a signal is produced when the comparison operation shows that (.varies..multidot.I.sub.a -I.sub.b).gtoreq..beta.. That signal indicates that the voltage U.sub.i has become equal to or higher than the threshold voltage U.sub.is and that therefore the time t.sub.1 has been reached or passed.

In order to determine the time t.sub.1, it is also possible to measure the current I.sub.a and calculate the product .varies..multidot.I.sub.a as above, calculate the difference (.varies..multidot.I.sub.a -.beta.), measure the current I.sub.b, flowing in the winding at the end of the interruption period, and compare that current I.sub.b to the difference (.varies..multidot.I.sub.a -.beta.). When the current I.sub.b is equal to or higher than the difference (.varies..multidot.I.sub.a -.beta.), the voltage U.sub.i is equal to or higher than the reference voltage U.sub.is.

It should be noted that the foregoing considerations remain valid if the calculation and comparison operations are performed by using, in place of the values of the currents I.sub.a and I.sub.b, the values of two currents I.sub.a ' and I.sub.b ' which are measured at the beginning and at the end of a measuring period which is of a duration T1' that is less than T1 and if of course the value T1 is replaced by that value T1'.

There is no need to wait for the end of the interruption or measuring period to carry out the various calculation and comparison operations referred to above. It is possible continuously to measure the current i flowing in the winding after the beginning of the interruption or measuring period and to use the value of that current, in place of the current I.sub.b, to perform the calculation and comparison operations, also on a continuous basis.

In the examples which will be described hereinafter, the various currents I.sub.a, I.sub.b and i are measured by the values of the voltages U.sub.a, U.sub.b and u which they respectively produce in passing through a measuring resistor connected in series with the winding of the motor during the drive pulse interruption periods. It will be appreciated that the various calculations referred to hereinbefore are then performed on the voltages which represent such currents, and which are proportional thereto. The factor .beta. is then replaced by a factor: .beta.=U.sub.is .multidot.R.sub.m /R.multidot.T1/.tau. in which R.sub.m is the value of the measuring resistor.

Equation (3) above, under those conditions, then becomes: ##EQU5##

The timepiece shown by way of example in FIG. 2 comprises a circuit 8 for generating a time base signal H at a frequency for example of 16384 Hz. The circuit 8 is formed by a quartz oscillator and a first divider stage for dividing by two, its output being connected to the input of a divider circuit 9 which, on the basis of the time signal H, produces various periodic signals including more particularly a signal I at a frequency equal to 1/2 Hz, a signal J at a frequency of 1 Hz and a signal K at a frequency of 64 Hz.

The timepiece shown in FIG. 2 further comprises a pulse shaper circuit 15 having an output which produces a signal, designated by means of Z, formed by a series of pulses which go to state "1" whenever the signal J itself goes to state "1", that is to say, every second (see FIG. 2a). The pulses of the signal Z go back to state "0" in response to a signal N supplied by a calculating circuit 26 which will be described hereinafter. The moment at which the signal N appears therefore determines the duration of the pulses of the signal Z.

The pulse shaper circuit 15 also supplies an auxiliary signal indicated at 0, which is formed by pulses which go to state "1" at the same time as the pulses Z but which are fixed in duration, being for example 7.8 milliseconds in duration.

Each time that the signal Z is at state "1", a drive circuit 12 supplies a drive pulse to the winding 11a of the motor 11. The voltage measured at the terminals of the winding 11a is indicated at U.sub.m in FIG. 2a. The energy applied to the winding 11a during each drive pulse is supplied by a power supply source 10.

The polarity of the drive pulses is determined by the logic state of the signal I which is alternately at state "0" and at state "1" for one second.

The drive circuit 12 is also so arranged that the drive pulses are chopped in response to a signal M formed by pulses at a high frequency. Each time that the signal M is at state "1", for example, the drive circuit 12 interrupts the connection between the power supply source 10 and the winding 11a, and short-circuits the winding. During those interruption periods, the circuit 12 supplies, at an output 12a, a voltage that is proportional to the current flowing in the winding 11a. That voltage is used by a measuring circuit 16, an example of which will be described hereinafter, to determine the time t.sub.1 at which the voltage U.sub.i induced in the winding 11a by the rotary movement of the rotor attains the reference value U.sub.is.

At time t.sub.1, the measuring circuit 16 produces, at its output 16e, a signal P which in turn is used by the calculating circuit 26 to produce the signal N at a time t.sub.2. The calculating circuit 26, an example of which will be described hereinafter, is so arranged that the time t.sub.2 is separated from the beginning of the drive pulse by a time equal to (.lambda..multidot.T.sub.d +.DELTA.) in which .lambda. and .DELTA. are the above-mentioned, experimentally determined constants. That period of time is therefore equal to the optimum duration of the drive pulse. As the signal N causes the signal Z to go back to state "0", the signal Z and therefore the drive pulse are equal in duration to the above-mentioned optimum duration.

The signal M is produced by a circuit 13, an example of which will be described hereinafter. The duration of each pulse of the signal M and the duration of the period of time which separates those pulses are determined by the content of a memory 14.

FIG. 3 shows the circuit diagram of an example of a first embodiment of the circuit 16 for measuring the induced voltage U.sub.i, in the device shown in FIG. 2. The circuit 16 comprises an input 16a which receives from the circuit 12 the voltage proportional to the current flowing in the winding 11a, a capacitor 18 having one plate connected to earth 19 and the other plate 18a connected to the input 16a by way of a transmission gate 20 and to the non-inverting input of an operational amplifier 21, the output of which is directly connected to its inverting input. The control electrode of the gate 20 is connected to the output Q of a T-type flip-flop 22 whose clock input T receives the signal M by way of the input 16c and whose zero resetting input R receives the signal H by way of the input 16d.

A calculating circuit 23 comprises a voltage divider formed by two resistors 231 and 232 which are connected in series between the output of the amplifier 21 and earth, and a differential amplifier 233 whose non-inverting input is connected to the junction between the resistors 231 and 232. The circuit 23 further comprises two resistors 234 and 235 which are connected in series between the output of the amplifier 233 and a voltage generator 24. The inverting input of the amplifier 233 is connected to the junction between the resistors 234 and 235.

The output of the amplifier 233 is connected to the noninverting input of another differential amplifier 25 whose inverting input is connected to the terminal 16a by way of a transmission gate 20a. The control electrode of the gate 20a is connected to the output Q of a T-type flip-flop 22a whose clock input T receives the signal M by way of an inverter 22b and whose input R receives the signal H.

The output of the amplifier 25 forms the output 16e of the measuring circuit.

The most of operation of the circuit shown in FIG. 3 is as follows: at the moment that the signal M goes to state 1, at the beginning of each interruption period, the output Q of the flip-flop 22 switches to state "1", which causes the gate 20 to be opened. When the signal H also goes to state "1", about 30 microseconds later, the output Q of the flip-flop 22 goes back to state "0" and the gate 20 is closed again. While the gate 20 is open, the capacitor 18 is charged up to a voltage U.sub.a that is proportional to the current I.sub.a flowing in the winding 11a at that time. By way of the amplifier 21, the voltage U.sub.a is applied to the voltage divider formed by the resistors 231 and 232. The values of those resistors are such that the voltage applied to the non-inverting input of the amplifier 233 is equal to .varies..multidot.U.sub.a in which .varies. is equal to .tau.-T1/.tau. as above, that is to say, it is proportional to .varies..multidot.I.sub.a.

The resistors 234 and 235 and the voltage supplied by the generator 24 are such that the output of the amplifier 233 produces a voltage equal to (.varies..multidot.U.sub.a -.beta.'), in which .beta.'=U.sub.is .multidot.R.sub.m /R.multidot.T1/.tau. as above.

At the end of the interruption period, the signal M goes to state "0" and the output Q of the flip-flop 22a goes to state "1" for a period of about 30 microseconds. The voltage U.sub.b that is proportional to the current I.sub.b flowing in the winding 11a at that time is therefore applied to the inverting input of the amplifier 25 which compares it to the voltage (.varies..multidot.U.sub.a -.beta.') at the output of the amplifier 233. As long as the voltage U.sub.b is higher than the voltage (.varies..multidot.U.sub.a -.beta.'), the output of the amplifier 25 remains at state "0". If the voltage U.sub.b is lower than the voltage (.varies..multidot.U.sub.a -.beta.'), the output of the amplifier 25 produces the signal P, going to state "1", which indicates that the voltage U.sub.i induced in the winding by the rotary movement of the rotor has exceeded the threshold voltage U.sub.is . That going to state "1" of the output of the amplifier 25 marks the time t.sub.1.

FIG. 3a shows the circuit diagram of a second embodiment of the circuit 16 for measuring the induced voltage U.sub.i. The components 18, 20, 20a, 21, 22, 22a, 22b, 24, 231 and 232 of the illustrated circuit are identical to the components denoted by the same references in FIG. 3, and operate in the same way.

The signal .varies..multidot.U.sub.a present at the junction between the resistors 231 and 232 is applied to the non-inverting input of an amplifier 233'. Two resistors 234' and 235' are connected in series between the gate 20a and the output of the amplifier 233'. The junction between those two resistors is connected to the inverting input of the amplifier 233'. The output of the amplifier 233' is connected to the non-inverting input of an amplifier 25' whose inverting input is connected to the output of the voltage generator 24. In this case, the output of the amplifier 25' forms the output 16e of the measuring circuit 16.

The resistors 234' and 235' are such that the output of the amplifier 233' produces a voltage equal to (.varies..multidot.U.sub.a -U.sub.b). The amplifier 25' compares the voltage to the voltage .beta.' supplied by the generator 24. The output of the amplifier 25' produces the signal P, going to state "1": when the voltage (.varies..multidot.U.sub.a -U.sub.b) becomes higher than the voltage .beta.', that is to say, again when the voltage U.sub.i induced in the winding by the rotary movement of the rotor becomes higher than the threshold voltage U.sub.is.

As already pointed out above, there is no need to wait for the end of the interruption period in order to carry out the different calculation and comparison steps referred to above. The gate 20a, the flip-flop 22a and the inverter 22b may be omitted from the circuits shown in FIGS. 3 and 3a, in which case input 16a of the circuit 16 is directly connected to the inverting input of the amplifier 25 and the resistor 235' respectively. In that case, the calculation and comparison operations are therefore performed on a continuous basis on the voltage u produced in the measuring resistor by the current i flowing in the winding 11a after the beginning of the interruption period. The signal P is then produced as soon as the voltage u falls below the voltage (.varies..multidot.U.sub.a -.beta.') or as soon as the voltage (.varies..multidot.U.sub.a -u) is higher than the voltage .beta.'.

FIG. 4 shows an embodiment of the calculating circuit 26 shown in FIG. 2. In that embodiment, the circuit 26 comprises an up-down preselection counter 27 having preselection terminals P1, P2, P3 and P4 which are respectively connected to the output terminals M1, M2, M3 and M4 of a read only memory 28. The counter 27 comprises a preselection control input PE for receiving the signal 0 by way of an inverter 29. The clock input CL of the counter 27 is connected to the output of a NAND-gate 30 having two inputs, each connected to the output of a respective NAND-gate 31 and 32, respectively. The circuit 26 further comprises a divider circuit 33 for supplying two signals Q1 and Q2 at respective frequencies f1 and f2, in response to the signal H. The signal Q1 is applied to one of the inputs of the gate 31 while the signal Q2 is applied to one of the inputs of the gate 32. A second input of the gate 31 is connected to the output Q of a T-type flip-flop 34 having its clock input T connected to the input terminal 26a of the circuit 26. A second input of the gate 32 is connected to the output Q of the flip-flop 34. The input U/D for controlling the direction of counting of the counter 27 is connected to the output Q of the flip-flop 34.

The counter 27 also comprises a coincidence output C which goes to state "1" for a short time when the content of the counter reaches a value of zero. The output C is connected to the clock input T of a T-type flip-flop 35 whose output Q forms the output 26b of the circuit 26 and whose resetting input R is connected to the output Q of a T-type flip-flop 101. The latter flip-flop receives the signal 0 at its clock input T and the signal H at its resetting input R. The output C of the counter 27 is also connected to the resetting input R of the flip-flop 34.

FIG. 4a illustrates the mode of operation of the circuit 26 shown in FIG. 4.

Between the drive pulses, the signal 0 is at state "0" and the input PE of the counter 27 is at state "1". The counter 27 is therefore blocked in the condition in which its content corresponds to the content of the memory 28, which is indicated by No. At time t.sub.o which coincides with the beginning of a drive pulse, the signal 0 goes to state "1", setting the input PE of the counter 27 to state "0", whereby the counter 27 is freed and begins to count, in the normal direction, the pulses issuing from the gate 30, starting from that condition No. That counting operation is performed at a frequency f1. At time t.sub.1 at which the voltage U.sub.i reaches the value U.sub.is, the input 26a goes to state "1" and the outputs Q and Q of the flip-flop 34 respectively go to state "1" and to state "0". The up-down control input of the counter 27 goes to state "0". From that time, the counter 27 operates in a down-counting mode. The down-counting operation is performed at the frequency f2. At the time t.sub.2 at which the content of the counter 27 becomes equal to zero, its output C goes to state 1 for a short time, setting the flip-flop 35 to state "1", the output Q of which, which was previously at state "0", going to state "1".

At the same time, the outputs Q and Q of the flip-flop 34 go back to state "0" and state "1" respectively. At the end of the pulse 0, the input PE of the counter 27 goes back to state "1". The content of the counter 27 therefore resumes the fixed value in the memory 28 and remains at that value until the signal 0 goes to state "1" again.

The output Q of the flip-flop 35 is reset to state "0" at the beginning of each drive pulse by the state "1" which appears at the output Q of the flip-flop 101 in response to the signal 0. That state "1" is suppressed after about 30 microseconds when the signal H goes to state "1".

FIG. 4a shows that the time T which elapses between the beginning t.sub.o of the drive pulse and the occurrence, at time t.sub.2, of the signal N at the output 26b of the circuit 26, is linked to the time T.sub.d which elapses between times t.sub.o and t.sub.1, by the following relationship: ##EQU6## in which f1 and f2 are the frequencies of the signals supplied by the outputs Q1 and Q2 of the divider 33 and No is the number contained in the memory 28 and therefore the number contained in the counter 27 at time t.sub.o.

Comparison between that equation and above-mentioned equation T.sub.opt =.lambda.T.sub.d +.DELTA., in which .lambda. and .DELTA. are constants that are determined experimentally for each type of motor, makes it possible to choose values for f1, f2 and No such that the period of time T which elapses between the beginning of the drive pulse and the appearance of the signal N is always equal to the optimum duration T.sub.opt of the drive pulse.

FIG. 5 shows the circuit diagram of an example of the circuits 12 and 15 in FIG. 2. The circuit 15 is formed in this embodiment by two T-type flip-flops whose clock inputs T both receive the signal J supplied by the frequency divider 9 in FIG. 2, at a frequency of 1 Hz. The resetting input R of the flip-flop 38 receives the signal K which is also supplied by the frequency divider 9, at a frequency of 64 Hz. The output Q of the flip-flop 38 therefore goes to state "1" every second, at the moment that the signal J goes to state "1", and goes back to state "0" about 7.8 milliseconds later, when the signal K in turn goes to state "1". The output Q of the flip-flop 38 therefore produces the signal 0.

The reset input R of the flip-flop 39 receives the signal N from the calculating circuit 26 shown in FIG. 2. The output Q of the flip-flop 39 therefore also goes to state "1" when the signal J goes to state "1", and goes back to state "0" when the circuit 26 supplies the signal N at the time t.sub.2, determined in the above-described manner. The output Q of the flip-flop 39 therefore produces the signal Z which is equal in duration to the optimum duration of the drive pulse.

In this embodiment, the circuit 12 of FIG. 2 comprises a logical circuit 43 formed by four AND-gates 431 to 434, two OR-gates 435 and 436 and two inverters 437 and 438. The winding 11a of the motor is connected into a circuit formed by four transmission gates 44 to 47 which are connected in conventional manner between the terminal +V of the power supply source 10 and earth.

Two other transmission gates 48 and 49 each connect one of the terminals of the winding 11a to a first terminal of a resistor 17 whose second terminal is connected to the input 16a of the circuit 16 shown in FIG. 2. The resistor 17 forms the above-mentioned measuring resistor.

The control electrodes of the gates 44 to 49 are connected to the outputs of the circuit 43, the inputs of which respectively receive the signals I, Z and M. The circuit 43 will not be described in greater detail herein, as it can be readily seen, by referring to FIG. 5a, that:

when the signal Z is at state "0", that is to say, between the drive pulses, the control electrodes of the gates 44 to 49 are all at state "0", irrespective of the state of the signal I and M. The gates 44 to 49 are therefore closed and the winding 11a is separated from the power supply source;

when the signal Z is at state "1", that is to say, during the drive pulses, and the signal M is a state "0", the gates 44 and 46 are in a conducting condition if the signal I is at state "0", with all the other gates being in a non-conducting condition, while the gates 45 and 47 are in a conducting condition if the signal I is at state "1", in which case all the other gates are also in a non-conducting condition. The power supply source is therefore connected to the winding 11a by way of the gates 44 and 46 or 45 and 47, and a current flows in the winding 11a in the direction indicated by the arrow 11b or in the opposite direction. That situation is the situation which occurs between the interruption periods, during the elementary pulses; and

when the signal Z is at state "1" and the signal M is also at state "1", the gates 47 and 48 or 46 and 49 are in a conducting condition, depending on the state "0" or "1" of the signal I, with all the other gates then being in a non-conducting condition. The power supply source is therefore disconnected from the winding 11a and the current flowing in the winding 11a also flows in the resistor 17 in which it produces the voltage that is applied to the input 16a of the measuring circuit 16. That situation is the one which occurs during the drive pulse interruption periods.

FIG. 6 shows by way of example, the circuit diagram of an embodiment of the circuits 13 and 14 of the FIG. 2 device.

The circuit 13 comprises two up-down preselection counters 131 and 132. The inputs U/D for controlling the direction of counting of the counters 131 and 132 are permanently at state 1. The counters 131 and 132 therefore operate in a down-counting mode. Their preselection terminals, which are generally denoted by Pi, are respectively connected to the outputs, generally denoted by Si, of two memories 141 and 142 which form the memory 14 of the circuit shown in FIG. 2. The memories 141 and 142 may be for example read only memories.

The clock inputs CL of the counters 131 and 132 are both connected to the output of the generator 8 (see FIG. 2) which produces the signal H. The counters 131 and 132 each comprise a coincidence output C which produces a short pulse whenever the content of the counters becomes equal to zero. The coincidence outputs C are connected to the inputs of an OR gate 133 having its output connected to the clock input T of a T-type flip-flop 134. The output Q of the flip-flop 134 is connected to the preselection control input PE of the counter 131, by way of an inverter 135, to the preselection input PE of the counter 132. The output Q of the flip-flop 134 is also connected to the output 13a of the circuit 13.

The mode of operation of the circuit shown in FIG. 6 will now be described with reference to FIG. 6a.

When the output Q of the flip-flop 134 is at state "0", the input PE of the circuit 132 is at state "1". The content of the counter 132 therefore assumes a condition corresponding to the content of the memory 142 and the counter 132 remains blocked in that condition, which is indicated by N142 in FIG. 6a.

On the other hand, the input PE of the counter 131 is at state "0" and the counter 131 counts the pulses of the signal H, in the down-counting mode. When the counter content reaches zero, its output C produces a pulse which is transmitted to the input T of the flip-flop 134, by way of the gate 133. The output Q of the flip-flop 134 and the input PE of the counter 131 therefore go to state "1". The content of the counter 131 therefore assumes a condition corresponding to the content of the memory 141 and the counter 131 is blocked in that condition, which is indicated by N141 in FIG. 6a. At the same time, the input PE of the counter 132 goes to state "0". The counter 132 begins to count the pulses of the signal H, in the down-counting mode. When the counter content reaches zero, the output C of the counter produces a pulse which is transmitted by means of the gate 133 to the input T of the flip-flop 134. The output Q of the flip-flop 134 goes back to state "0", and the above-described procedure begins again.

The output Q of the flip-flop 134 which produces the signal M therefore goes alternately to state "0" and to state "1" during periods of time which depend on the frequency of the signal H and the content of the memories 141 and 142 respectively.

The duration of the periods of interruption of the drive pulses, which is equal to the period of time for which the signal M is at state "1", and the duration of the elementary pulses which separate the interruption periods, which is equal to the period of time for which the signal M is at state "0", can therefore be determined independently of each other. The above-mentioned durations are determined in any fashion. They may be fixed or they may vary, in a manner which will not be described herein, in dependence on parameters such as the voltage of the power supply source 10, or the mechanical load driven by the motor, or any other parameter.