Metallic Silicide Production

This invention relates to metallic silicide production and, in particular, to the production of metallic silicide layers on substrates, such as semiconductor bodies, for electrical interconnection purposes.

The reduction of semiconductor device geometries necessary for the realisation of very large scale integration (VLSI) circuits requires a reduction in the resistivity of the high-temperature-compatible interconnect materials employed, and to this end metallic silicides, such as titanium, tantalum, tungsten or molybdenum silicide, are increasingly being adopted as an alternative to polysilicon.

A general reduction of process temperatures or times is also desirable to minimise redistribution of dopants and interdiffusion of adjacent layers. Presently, for example, titanium and silicon layers are annealed for some 30 to 40 minutes in order to form titanium disilicide, and the length of such anneal times is disadvantageous. Whilst it has been shown that such anneal times can be reduced, this necessitates the acceptance of a reduction in the conductivity of the titanium disilicide films produced.

According to the present invention there is provided a method of forming a metallic silicide layer on a substrate, including the steps of depositing the metal and silicon on the substrate, and subsequently pulse heating the substrate, in an inert atmosphere, to a temperature and in a time sufficient to cause interdiffusion of the metal and silicon to form a homogenous layer and reaction of the constituents thereof to form the metallic silicide.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which:

FIG. 1 shows, schematically, pulse anneal apparatus employed for titanium silicide layer production according to one embodiment of the present invention,

FIG. 2 shows plots of sheet resistance versus anneal temperature for the pulse anneal process of the present invention and a conventional furnace process, and

FIG. 3 shows plots of sheet resistance versus the number of heat pulses employed for different anneal temperatures.

It has previously been shown that a short high temperature anneal at the end of a process is highly beneficial in terms of activating dopants (U.S. Pat. No. 4,350,537) or reactivating dopants (U.S. patent application Ser. No. 413,327, filed Aug. 31, 1982). We have now found that it is possible to achieve the desired high conductivity in titanium silicide films by using only very short high temperature anneal processes during their manufacture.

In one experiment for obtaining titanium disilicide films, an 80 nm thermal oxide layer was grown by a wet oxidation process on a silicon wafer in order to provide a suitable substrate which is comparable with a processed (diffused) wafer on which titanium disilicide interconnections would be provided. Titanium and silicon layers, which are 7 nm and 14 nm thick respectively, were alternatively sputtered onto the substrate until a total film thickness (titanium and silicon layers) of 200 nm was achieved on the oxide layer. The film had a metallic silver appearance and a sheet resistance of 25.OMEGA./.quadrature.. A dc magnetron sputtering source was used for the titanium layers, whereas an rf magnetron sputtering source was used to provide the silicon layers, in view of the higher resistivity of the polycrystalline silicon target. Both of the titanium and silicon targets employed were specified pure to 99.99%. The sputtering was carried out in a chamber evacuated to 10.sup.-5 torr prior to back filling with argon to a pressure of 8.times.10.sup.-3 torr. The thickness and composition of the film were calculated from deposition rates, which were checked by etching a step in the film and measuring its height, and also by measuring the weight increase after deposition.

Prior to an annealing process, in which the film constituents interdiffuse to form an homogenous layer and then react to form the low resistivity disilicide, for experimental purposes the wafer was scribed into 1 centimeter squares and a drop of colloidal carbon solution was placed on each square in order to enable the actual wafer temperature to be monitored by a pyrometer during the anneal. The squares were then annealed in the pulse anneal apparatus shown schematically in FIG. 1.

Anneal chamber 1 includes a graphite heater 2 on which one or more coated squares 3, only one of which is shown, are arranged for heating purposes. The square 3 has a carbon coated surface portion 4 used for monitoring the temperature of the square by means of an infra-red pyrometer (not shown). The anneal chamber 1 is first evacuated to 5.times.10.sup.-6 torr and then back filled with nitrogen to a pressure slightly above atmospheric. The square 3 was then heated by passing current through the graphite heater 2 and monitoring the temperatures achieved by means of the infra-red pyrometer. As in the case of the previously mentioned co-pending applications, the heating is pulse heating, that is rapidly raising the temperature to a peak value and then allowing it to cool, immediately in the case of "triangular" pulse heating. Depending on the square temperature required the current was passed through the graphite heater for a corresponding time, which varied from 8 seconds for 700.degree. C. to 19 seconds for 1100.degree. C. The thicker the individual layers, the longer the anneal necessary to interdiffuse the layers. The square 3 was left to cool in the chamber 1 for 10 to 15 minutes, taking under 30 seconds to cool below 600.degree. C. All trace of the carbon coating 4 was removed and a four point probe used to measure the sheet resistance of the annealed film.

FIG. 2 shows the relation between sheet resistance of annealed titanium/silicon films and the anneal temperature for the pulse heating process of the present invention and a conventional 30 minutes furnace anneal process. The pulse anneal curve shows that the sheet resistance can be reduced rapidly thereby from the as deposited value of 25.OMEGA./.quadrature. to 6.OMEGA./.quadrature. by employing 10 second pulse heating to temperatures of up to approximately 900.degree. C., the heater current being suitably varied to achieve the required temperature in 10 seconds, however temperatures in excess of 900.degree. C. are required for further drop in the sheet resistance to approximately 1.OMEGA./.quadrature..

As previously mentioned the completion of two processes is required to achieve low resistivity films when the film constituents are sputtered alternately. The film constituents must first interdiffuse to form an homogenous layer, and they must then react in order to form the silicide. It is considered likely that sufficient interdiffusion to form titanium monosilicide occurs very rapidly at temperatures above 750.degree. C., but that temperatures in excess of 900.degree. C. are required, given the short length of the heating pulse, to form the lower resistivity titanium disilicide throughout the film. The sheet resistivity of the films pulse annealed above 900.degree. C. is directly comparable with that obtained from films annealed in a conventional furnace for 30 minutes, as can be ascertained from the furnace anneal plot in FIG. 2, indicating that the interdifusion and reaction of titanium and silicon are complete.

The post pulse anneal film thickness for the 1100.degree. C. sample was estimated by Auger profiling to be 175 nm. This and the measured sheet resistance of 1.3.OMEGA./.quadrature. show that the bulk resistivity of the annealed film is close to 23 .mu..OMEGA.cm, which is in good agreement with previously reported values for titanium disilicide.

FIG. 3 shows the sheet resistivity after repeated pulses, and indicates the effectiveness of pulse annealing compared with a full furnace anneal. As mentioned above, for pulse anneals at temperatures in excess of 900.degree. C. the interaction appears to be complete, with subsequent pulses yielding no further improvement. The sample pulse annealed at 870.degree. C., however, shows a dramatic drop in sheet resistance after only a few (three) pulses, whereas the sample pulse annealed at 770.degree. C. does not show a similar change after more than twice as many (eight) pulses.

It is presently considered that by decreasing the thickness of the individual titanium and silicon layers, the peak temperature of the pulse anneal required to obtain high conductivity (low resistivity) will drop. The 770.degree. C. plot of FIG. 3 could then be expected to approximate more to the 870.degree. C. plot, or even the 1000.degree. C. plot. The limiting temperature is approximately 600.degree. C., which is the lowest temperature at which titanium disilicide is the favoured phase for formation. Even with the anneal pulse at approximately 950.degree. C., the equilibrium diffusion of dopants is predicted to be negligible, by analogy with the dopant activation and reactivation effect of pulse heating referred to in the above co-pending applications, and in fact the short high temperature anneal used to activate or reactivate dopants at the end of a process could also be used to anneal titanium silicide gate electrodes and interconnects. The pulse heating (annealing) of the present invention for silicide production avoids the problem of over-diffusing other dopants in the semiconductors.

Whereas the invention has been described with reference to providing titanium silicide layers on semiconductor substrates, it can also be applied to other substrates. Metallic silicides other than titanium silicide may be produced in a similar manner, such as tantalum, tungsten or molybdenum silicide.

The method described above employs sputtering of the metal and silicon alternately onto a substrate. Alternatively, however, the metal and silicon may be simultaneously co-sputtered, whereby to achieve an almost homogenous film, in which case the pulse heating mainly serves for causing the necessary reaction between the metal and the silicon to form the silicide.

The above described metal silicide production may be employed in the manufacture of, for example, n-channel MOS integrated circuits, the basic processing steps of which are as follows, namely: (1) define device area for local oxidation; (2) implant field; (3) grow field oxide; (4) grow gate oxide and implant gate region; (5) deposit titanium silicide and define; (6) implant source and drain; (7) pulse anneal titanium silicide and source/drain; (8) grow or deposit intermediate oxide and define contacts; (9) reactivation pulse anneal; (10) metal deposition and definition, and (11) passivation and packaging.