Sync Suppression Scrambling of Television Signals for Subscription TV

The present invention relates to subscription TV in which TV signals are scrambled by suppressing the sync intervals thereof so that the TV signals are distorted when displayed except at authorized receiving stations which are equipped to descramble the TV signals.

The invention is especially suitable for use in the transmission of premium, subscription TV programs by cable systems. Features of the invention may also be applied to the transmission and reception of premium TV by broadcast or in other networks such as in hotels, dormitories and other places of public accommodation.

Sync suppression scrambling and descrambling systems of various types have been suggested, and some systems are presently in use on those channels of cable TV systems which offer premium subscription programming. These systems generally operate by the transmission of the TV signals with the horizontal sync intervals thereof suppressed. At the authorized receiving stations, the sync signals are restored by the use of a restoring signal, which may be transmitted as a pilot tone on an unused cable channel or which is generated in response to the horizontal sync components of the transmitted signal or by other means. Various systems for sync suppression scrambling are described in the following patents. In most cases the suppression signals are pulses. Sine wave suppression signals have been suggested in the five patents which are listed last below. Druz, U.S. Pat. No. 2,705,740, issued Apr. 5, 1955; Weiss, U.S. Pat. No. 2,907,816, issued Oct. 6, 1959; Loughlin et al, U.S. Pat. No. 3,081,376, issued Mar. 12, 1963; Doundoulakis, U.S. Pat. No. 3,116,363, issued Dec. 31, 1963; Court et al, U.S. Pat. No. 3,184,537, issued May 18, 1965; Doundoulakis, U.S. Pat. No. 3,201,511, issued Aug. 17, 1965; Salit et al, U.S. Pat. No. 3,242,258, issued Mar. 22, 1966; Walker, U.S. Pat. No. 3,439,113, issued Apr. 15, 1969; Rieiter et al, U.S. Pat. No. 3,478,166, issued Nov. 11, 1969; Reiter et al, U.S. Pat. No. 3,530,232, issued Sept. 22, 1970; Vogelman et al, U.S. Pat. No. 3,736,369, issued May 29, 1973; Blonder, U.S. Pat. No. 3,813,482, issued May 28, 1974; Sperber, U.S. Pat. No. 4,095,258, June 13, 1978; Mistry et al, U.S. Pat. No. 4,163,252, issued July 31, 1971, Court, U.S. Pat. No. 3,729,576, issued Apr. 24, 1973; Harney et al, U.S. Pat. No. 4,024,575, issued May 17, 1977; Saeki et al, U.S. Pat. No. 4,064,536, issued Dec. 29, 1977; Uemora et al, U.S. Pat. No. 4,145,716, issued Mar. 20, 1979; and Guif et al, U.S. Pat. No. 4,145,717, issued Mar. 20, 1979. All of the above listed patents are United States patents.

The problem with sync suppression scrambling schemes which have been suggested, except for those which transmit complex coding signals and which have not been generally accepted, is the ease with which the signals can be descrambled and restored to normal amplitude so that they can be displayed at unauthorized receiving stations. For example in the case where the signals are encoded by a pilot tone or timed to the horizontal sync signals, all that is required is a simple circuit for detecting these pilot or sync rate signals and generating a restoring pulse for a gated attenuator through which the television signal passes in order to restore the television signal to normal amplitude. One such scrambler has been offered by a company known as C&D Engineers, their model CDK 234 and 236 descrambler.

It is a feature of this invention to provide improved methods of and systems for the transmission of premium subscription TV programs with greater scrambling efficiencies and which is more difficult to defeat and descramble without authorization, but without increasing the complexity and cost of sync suppression scrambling so as to make the use thereof impractical.

It is a further feature of the invention to provide improved methods of and systems for the transmission of encoded suppressed sync TV signals, as well as for the reception and descrambling of such signals, which can be implemented by digital circuits which further facilitates the fabrication and use of sync suppression scrambling having high security efficiency at low cost.

It is a further feature of the present invention to provide improved methods and systems for sync suppression scrambling and descrambling of TV signals which may be encoded with selectively coded timing which may be dynamically varied, so that the generation of sync restoring signals with the proper timing to descramble and normalize the TV signal is available only to authorized parties thereby making it very difficult to defeat the security of the system and discouraging the use of unauthorized descramblers.

Briefly described, sync suppression scrambling and descrambling of TV signals for subscription TV programs, in accordance with the invention, may be carried on by generating sync suppression pulses in overlapping time relationship with the horizontal sync pulses of the TV signal. Timing pulses are generated in selected time relationship with the sync suppression pulses such that each of the timing pulses and the sync suppression pulses have a selected time delay With respect to each other. This time delay may be selected, preferably digitally, from a plurality of different delays or dynamically varied. The horizontal sync pulses are suppressed to below normal amplitude, which sync detectors of conventional TV receivers at the receiving stations are capable of using. The timing pulses are transmitted with the TV signals, preferably by modulating the FM audio carrier thereof to encode the TV signals. The scrambled and encoded TV signals are transmitted from the transmitting stations which may, for example, be the head end system of a cable TV system to the receiving stations, for example on a channel dedicated to premium programming. The timing pulses are derived at these receiving stations with the selected delay to provide delayed timing pulses. Then restoring pulses are generated in proper overlapping time relationship with the horizontal sync pulses upon occurrence of the delayed timing pulses. The TV signals are restorable to normal amplitude through the use of the restoring pulses to descramble the TV signals. Digital delays are preferably interposed on the timing pulses to provide the delayed timing pulses. The selected delays may be pre-set, for example as pre-set digital delays at the transmitting point and also at those receiving stations which are authorized to receive premium programming. If desired and when the delays are to be dynamically varied, delay control signals are transmitted with the TV signals to vary the delay dynamically at the authorized receiving stations so as to correspond to the variation in delay at the transmitting point. Only at authorized receiving stations will the restoring pulses be in synchronism with the horizontal sync intervals of the TV signals, thereby enabling them to be restored to normal amplitude and to be displayed in a visually satisfactory manner on TV receivers at the authorized stations.

The foregoing and other objects features and advantages of the invention, as well as presently preferred embodiments thereof and the best modes now known for practicing the invention, will become more apparent from a reading of the following description in connection with the accompanying drawing in which:

FIG. 1 shows a series of wave forms illustrating sync suppression scrambling and descrambling in accordance with the invention;

FIG. 2 is a block diagram illustrating, in a general manner, a system for sync suppression scrambling in accordance with the invention;

FIG. 3 is a block diagram illustrating, in a general manner, a system for sync suppression descrambling in accordance with the invention;

FIG. 4 is a block diagram illustrating a sync suppression scrambling system in accordance with an embodiment of the invention;

FIG. 5 is a block diagram of a digital circuit for providing variable delay between the timing and suppression pulses generated in the system shown in FIG. 4;

FIG. 6 is a block diagram illustrating another digital delay circuit which may be used in the system shown in FIG. 4;

FIG. 7 is a block diagram showing a descrambling system which may be used with the scrambler shown in FIG. 4;

FIG. 8 is a series of wave forms illustrating the operation of the scrambling and descrambling system shown in FIGS. 4 and 7;

FIG. 9 is a block diagram illustrating a digital system for providing selected delays which may be dynamically variable and which may be used in the system shown in FIG. 4;

FIG. 10 is a block diagram illustrating a digital system, particularly useful when the selected delay between the scrambling and timing pulses is dynamically varied, for example, by the use of the digital system shown in FIG. 9, for deriving the delayed timing pulses which may be used for the generation of restoring pulses in the system shown in FIG. 7; and

FIG. 11 is a block diagram of a digital system for providing selected delays which may be used for the generation of restoring pulses in the system of FIG. 7.

Referring to the drawings and more particularly to FIG. 1, there is shown in wave form (a) the normal video signal of a TV signal with horizontal and vertical sync intervals. Horizontal sync pulses are located in the horizontal sync intervals with the color burst following the picture information. The audio signal is part of the TV signal and may be FM audio signal as is conventional. The vertical interval includes horizontal as well as the vertical sync pulses. The horizontal pulses are repetitive at the horizontal sync rate of 15,534 Hz while the vertical sync intervals occur each frame of the picture, as is conventional.

A timing pulse identified as the scrambler audio timing pulse in FIG. 1(b) is generated at the horizontal sync rate. This pulse amplitude modulates the FM audio signal to encode the TV signal with information as to the timing of the scrambler sync suppression pulse. The suppression pulse is shown in wave form (c) of FIG. 1 as the scrambler video suppression pulse. This pulse is also repetitive at the horizontal sync rate and has a selected time relationship, indicated in FIG. 1 as t.sub.XT with respect to the timing pulse. In effect, the scrambling pulse may be considered to be the timing pulse delayed by the selected time delay t.sub.XT and reshaped as shown in FIG. 1(c). The timing is such that the suppression pulses are in overlapping relationship with the horizontal sync pulses and coincident with the horizontal interval. The time delay t.sub.XT may be selected from a plurality of delays, which in accordance with an embodiment of the invention, may be 12 delays each of different duration. The delay t.sub.XT can also be a dynamically varying delay (a delay which varies in time, preferably continually such that in successive intervals of time the delay t.sub.XT is a different duration, for example one of the twelve different durations which may be selected).

The vertical interval is also shown in FIG. 1(c) as a vertical suppression pulse, indicated as a level equal to the level of the suppression pulses during the horizontal intervals. The use of the vertical suppression pulses is optional, but is preferred in that it increases the distortion of the picture represented by the scrambled video signal at unauthorized receivers. It will be noted that audio timing pulse ceases and the video signal is attenuated during the vertical interval. The video signal is preferably converted to IF frequency when the suppression pulses are applied to attenuate the video signal to provide a scrambled video signal as shown in wave form (d) in FIG. 1. The FM audio is also preferably at IF frequency when it is modulated by the timing pulses to encode them onto the FM audio carrier. The scrambled video signal may be converted to the desired RF channel and transmitted to the receiving stations. Transmission may be on a cable of a cable TV system in a channel dedicated to premium subscription TV programs. When the scrambled signal is displayed on a conventional television receiver the picture will shift in a visually disturbing manner and will lack sufficient information or entertainment value.

Wave form (e) of FIG. 1 shows the demodulated timing pulse indicated as the descrambler audio timing pulse, which is derived by demodulating the FM audio signal at the receiving stations. The equipment for demodulation and descrambling may be part of a set-top converter which is provided to subscribers who pay for the premium programming. The descrambler detects the timing of the pulse shown in wave form (e) of FIG. 1 and delays the pulse by the selected delay, indicated as t.sub.XR. The timing pulses are used to generate restoring pulses, indicated as being the descrambler video restoring pulses in wave form (f) of FIG. 1. These restoring pulses are coincident with the horizontal sync pulses and a portion of the horizontal sync interval which is of slightly shorter duration than that interval so as to assure restoration of the horizontal sync pulses without affecting the picture components of the signal. The restoring pulses appear as a restoring level during the vertical interval. The level of the pulses is shown as being inverse to the level of the scramble video signal so as to illustrate that the restoring pulses may be used to restore the horizontal and vertical sync pulses to their original or normal amplitude. In practice an attenuator operated by the restoring pulses which enables the horizontal and vertical sync signals to be increased in relative amplitude with respect to the other components of the video signal may be used.

The descrambled video signal with correct timing is shown in wave form (g) of FIG. 1. Devices which duplicate the inverse video restoring pulses that fail to duplicate the selected timing, t.sub.XR, will for example, produce a signal similar to that shown in wave form (h) of FIG. 1. Fragmentary wave form (h) shows the erroneous restoring pulse, with the wrong timing, t.sub.XE. Such a signal (like wave form (h)) will cause the normal sync pulses to appear as gray vertical bars on the television receiver. The picture information is split on both sides of these bars. There is no color burst lock. Such a poor quality picture contains little of entertainment or informational value. The higher security efficiency provided by the system should discourage the use of unauthorized descramblers, since they will provide only a distorted picture as mentioned above.

The scrambler system shown in FIG. 2 provides for high efficiency of scrambling of video signals in the manner illustrated in FIG. 1. The baseband video input of the premium programming is converted at the head end of the cable system by an input converter to IF frequency. The accompanying IF audio signal is similarly converted. This conversion is carried out by the input converter of the head end modulator (HEM) 10. A sync detector 12 detects the horizontal sync and may also detect the vertical sync pulses. A scrambler timing pulse generator 14, operated by a delay control 16, generates the timing pulses with the selected delay, which may be one of a plurality of different durations or dynamically varying, either continually or continuously as determined by the delay control 16. The timing pulses are applied to a variable attenuator 18 which effectively amplitude modulates the FM carrier of the FM audio signal, as by attenuating it except during the timing pulse.

A scrambler suppression pulse generator 20 generates the suppression pulses coincidentally with the horizontal sync intervals. Since both the suppression and timing pulses derive their timing from the sync pulses in the video signal, the selected time relationship between the timing and suppression pulses is maintained during each line of the television signal. The timing and suppression pulses are preferably generated by timing the suppression pulse generation from the timing pulses (as will be described in greater detail in connection with FIG. 4). The scrambler suppression pulse generator 20 generates the suppression pulse with sufficient delay to make up the difference in delay in the video and audio IF channels. Another variable attenuator 22 in the video IF channel suppresses the horizontal, and if desired the vertical sync signals, during their respective intervals of the video signal, and outputs a scrambled video IF signal to the output combiner and output converter 24 of the head end modulator (HEM). The converter locates the FM audio signal adjacent to the video signal in the RF channel allocated to the premium programming. This RF signal may be applied to the cable at the head end of the cable TV system. Accordingly the TV signal is scrambled and then encoded with the timing pulse on the FM audio.

Each receiving station which is adapted to receive subscription TV is provided with a system which is shown in general in FIG. 3. The RF input from the cable goes to the set-top converter 26 which may convert the cable channels to the standard channel frequencies and bands of the TV receiver which is to display a subscription TV program at the receiving station. The TV signal with audio and video combined is, when the premium channel is selected, connected through a variable attenuator 28 to the input terminal (the antenna terminals) of the TV receiver. The variable attenuator and the other circuits for descrambling may be contained in the set-top converter. The scrambler timing pulse is detected from the FM audio component of the TV signal by a timing pulse detector 30. This detector may include the usual traps and filters for the audio component of the TV signal and a diode AM detector. The timing pulse is subject to the selected delay in a variable delay circuit 32. The delay is selected by a delay control 34. The variable delay and delay control circuits 32 and 34 may be similar to the circuits which provide the selected delay in the scrambler timing pulse generator 14 (see FIG. 2). The delayed timing pulse is used to time the generation of each restoring pulse in a restore pulse generator 36. The restoring pulses are coincident with the horizontal sync pulses and most of the horizontal sync intervals of the video signals.

This restore pulse circuit may include a timing circuit responsive to the horizontal sync pulses in the TV signal to produce restoring pulses during the vertical sync interval as well as during the horizontal sync intervals. This circuitry is optional and is not used when vertical sync interval suppression pulses are not generated in the scrambler. It will be noted that the timing pulses are not transmitted during the vertical sync intervals of the scrambled signal. Accordingly receiving stations which are not equipped with the descrambler (for example, a separate board which may be installed in the set-top converter 26 at those receiving stations which subscribe for premium programming), the vertical sync pulses remain suppressed. Those receiving stations which are not equipped to detect timing pulses will, of course, not descramble the premium TV signals. Even those stations which are equipped to detect timing pulses will not descramble the signals because there will be no knowledge of the selected delays.

The selected delay may be one of 12 different durations which may be changed from time to time by visits of service personnel. The delay may be dynamically variable, as will be more fully explained below, in which case a delay control signal from the delay control 16 of the scrambler system (see FIG. 2) is combined with the TV signal in the combiner and output converter 24 and transmitted to the receiving stations. These signals will then operate the delay control so that the selected delay can be varied either continuously or continually from time to time. Only when the scrambler restore pulse is coincident with the horizontal sync pulses, and is operative to restore the TV signals with their horizontal and vertical components in normal amplitude relationship, is the TV receiver capable of extracting the sync signals and properly displaying the pictures represented by these signals on the screen of the TV receiver. Such display will be carried out only at those receiving stations which are authorized to receive premium programming, since the descrambling circuitry will not operate properly to descramble the TV signal except at such authorized stations.

Referring to FIG. 4, the scrambler is shown in greater detail and in accordance with a presently preferred embodiment thereof. The composite TV signal, the video signal thereof or, and more preferably, the composite sync signal which has been stripped from the video, is applied to the input terminal of a sync separator circuit 38, which provides the horizontal sync signal (shown in wave form (f) of FIG. 8) and the vertical sync signal. The horizontal sync signal is used as a reference to locate the sync suppression pulses, shown in wave form (g) of FIG. 8 (labelled video attenuator suppression pulses) in overlapping, coincident time relationship with the horizontal sync pulses, as was discussed in connection with the scrambler suppression pulse generator 20 shown in FIG. 2.

A phase locked loop 40 provides the means for locating the suppression pulses in the necessary overlapping, coincident relationship with the horizontal sync pulses in the horizontal sync intervals. This loop also contains circuits for generating the timing pulses which are shown in wave form (d) of FIG. 8 (labelled audio attenuator timing pulses), and for generating the suppression pulses with the selected time relationship. The phase locked loop 40 includes a voltage controlled oscillator of relatively high frequency as compared to the horizontal sync rate (8.06 MHz, which is 512 times the horizontal sync pulse rate, being suitable). This oscillator is indicated as being a voltage controlled oscillator 42. The high frequency output from the oscillator is indicated in wave form (a) of FIG. 8. The oscillator output is shaped in the form of a pulse train. A divider 44 divides the oscillator output into a 50% duty cycle rectangular wave at the horizontal sync pulse rate (15,734 Hz). The divider output is shown in wave form (b) of FIG. 8. The leading edge of the divider output is used to generate the timing pulses. A timing pulse shaper 46, which may be a one shot, provides timing pulses of suitable duration, for example approximately 6 microseconds, through a gate circuit 48 to the variable attenuator 22 in the audio IF channel.

The divider output is applied to a variable delay circuit 50 to produce the selected delay between the suppression and timing pulses. This variable delay circuit is preferably a digital delay circuit of the type which will be described in greater detail in connection with FIGS. 5 and 7. The variable delay, t.sub.XT is illustrated in wave form (d) of FIG. 8 which shows the output of the variable delay circuit 50. The divider pulse train is delayed by the selected delay so that the selected timing for the suppression pulses with respect to the timing pulses is obtained. The selected delay may be selected from a plurality of different delay increments or continuously variable, in which case the delay control 16 outputs a delay control signal (DCS) to the combiner and output converter 24 of the head end modulator (HEM). The variable delay circuit 50 may be designed to insert a predetermined delay, to which the selected delay is added. Conceptually, this predetermined delay may be considered part of the total phase locked loop predetermined delay or set-up delay to compensate for different delays in the video IF and audio IF channels of the system.

The leading edges of the output pulses from the variable delay circuit 50 time and operate a pulse shaper 52. The duration of the output pulses from the pulse shaper 52 is preferably greater than the horizontal sync interval (for example, approximately 13 microseconds) so that the suppression pulse overlaps the horizontal sync pulses as shown in wave forms (f) and (g) of FIG. 8. The suppression pulses are applied through a gate 54 to the variable attenuator 18 in the video IF channel.

Another delay circuit 56 imposes the predetermined delay which is indicated as the set-up delay, t.sub.setup, in the showing of such pulses in wave form (e) of FIG. 8. This delay circuit 56 is also desirably a digital delay circuit, a preferred form of which is illustrated in FIG. 6. The output pulses from the divider 44 (wave form (b) of FIG. 8) are effectively delayed to be within the locking range of the phase detector 58 of the phase locked loop 40. The phase detector then outputs a control voltage through a low pass filter 60 which changes the phase of the voltage controlled oscillator 42 output. The divider 44 output then moves in phase so that the leading edge of the output of the delay circuit 56 lines up with the horizontal sync pulse leading edge. Accordingly, the output of the variable delay circuit 50 which imposes the selected delay t.sub.XT, and the set-up delay move in time, but maintain the selected delay, whereby timing of the restoring pulses in the descrambler from the timing pulses always produces the restoring pulses in overlapping relationship with the horizontal sync pulses so that they can be restored in the descrambler circuit.

Scrambling during the vertical sync interval is obtained by a pulse generator or timer circuit 62, which detects the vertical sync pulses and outputs a suppression pulse during the vertical sync interval. A suitable timer circuit for use in the pulse generator system 62 may respond to the vertical sync pulses and include delay circuits for generating pulses during the entire vertical retrace intervals. These vertical suppression pulses are applied to the gate 48, which operates as a NAND gate, so as to delete the timing pulses during the vertical sync interval. The gate 54 which passes the suppression pulses acts as an OR gate so that the vertical sync interval pulses are transmitted as suppression pulses during the vertical sync interval. Accordingly, the scrambled TV signal, encoded by the timing pulses, is generated and transmitted with the delay control signal, if variable selected delay is used, to the receiving station as a composite signal via the head end modular 24 of the cable system.

Referring to FIG. 5, the variable delay 50 may be a digital delay circuit having a clock oscillator 64 which produces a high frequency clock pulse train. A repetition rate of approximately 3.5 MHz may be suitable. These pulses are counted by a counter 66 which counts up to a four bit binary count of 16. The output of this counter has a repetition rate of approximately 224 KHz and is used as a clock for a variable bit length shift register 68. A length control switch 70 is provided to set the length of the variable length shift register 68 from zero to eleven bits, which in turn delays the pulses from the divider from zero to approximately 49 microseconds in eleven steps of approximately 4.5 microseconds each. The shift register output pulses may be applied to logic circuits containing one shots or other digital timers to provide more exact timing in the event that t.sub.XT is not precisely one of the twelve variable shift register delays.

The predetermined delay may be precisely set by means of the circuit shown in FIG. 6. There are two variable bit length shift registers 76 and 84 in tandem to delay the pulses from the variable delay circuit 50 to provide the output pulses from the delay circuit 56 to the phase detector 58 (See FIG. 4). The bit length of the variable length shift register 76 is set by a digital switch 78, the bit length of the variable length shift register 84 is set by another digital switch 86. The first variable length shift register 76 is clocked from a one MHz clock which is derived from a divide by eight divider 74 which is clocked by an eight MHz clock oscillator 72. The eight MHz clock oscillator also clocks a variable bit length shift register 80 which is set by a digital switch 82 to delay the one MHz clock in increments of 0.125 microsecond. The output to the phase detector 58 is delayed in one microsecond increments by the variable length shift register 76 and by the variable length shift register 84 and is delayed in 0.125 microsecond increments by phasing the variable length shift 84 clock by means of the variable length shift register 80. By phasing the clock pulses and selecting the variable delays in the chain, very precise digital delays of predetermined duration are obtained to provide alignment and location of the pulses in the phase lock loop 40.

Referring next to FIG. 7, the descrambler is there shown in greater detail in accordance with presently preferred embodiment of the invention. The set-top converter 26 is separately indicated, but may include a circuit board containing the descrambler circuits. When the descrambler circuits are not in operation, the set-top converter output may be switched directly to the RF (antenna) input to the TV set. Such switching may be omitted, if desired, in that the variable RF attenuator 92 normally inserts a fixed amount of attenuation which is decreased by the restoring pulses. This fixed amount of attenuation may be made up in the amplifiers of the TV set. The set-top converter may include circuits such as traps and filters for extracting the FM audio signal. This signal is then applied to an AM detector circuit 94 which may be a voltage doubler type diode detector. The timing pulses modulated on the FM carrier are detected as amplitude modulation. The AM detector may also include traps for the chroma component of the signal. The audio AM detector pulses are shown in wave form (h) of FIG. 8. These pulses are delayed slightly with respect to the timing pulses due to the delays in the detector circuit 94. This delay is accommodated by the predetermined or set-up delay in the scrambler so that the selected delays, t.sub.XR =t.sub.XT, are maintained.

The timing pulses may be fed to a pulse shaper 96 and then to a variable delay circuit 98. The variable delay circuit may precede the pulse shaper. The arrangement shown in FIG. 7 is, however, presently preferred since it lends itself better to the use of a shift register chain as a digital, variable delay circuit. The pulse shaper includes one shots or, preferably, a digital timer circuit for generating the restoring pulse of the desired duration less than the horizontal blanking interval. In the example shown in FIG. 8, where the horizontal interval is 13 microseconds, the restoring pulse may be 11 microseconds in duration starting after and ending before the horizontal interval and covering only the portion thereof which contains the horizontal sync signals. The variable delay circuit 98 and its delay control 100 may be similar to the corresponding circuits 50 and 16 shown in FIG. 4. They may be implemented by a digital delay circuit and digital control switch 70 as shown in FIG. 5. Preferably a chain of shift registers including variable bit length register, such as the 64 bit shift register 108 together with the 1-bit shift register 110 which is connected thereto, as will be described more fully hereinafter in connection with FIG. 9 may be used. The output of the variable delay circuit 98 is the restoring pulses shown in wave form (j) of FIG. 8.

A control gate and timer circuit 102 is operated by an authorization control which may be a digital switch or signal generator 104. When vertical scrambling pulses are used, the timer and the control gate 102 detects the absence of the timing pulses as they arrive from the variable delay circuit 98 and generates the vertical restoring pulse. The authorization signal enables the gate to pass the restoring pulses, which have been generated with the selected delay, t.sub.XR. The control gate and timer therefore passes the restoring pulses, as indicated in wave form (k) in FIG. 8 to the RF attenuator 92 to restore the TV signal to normal amplitude. The delay control signal detector 106 design depends upon the location of the delay control signal in the TV signal. In cases where vertical interval scrambling is not used, the delay control signal may be transmitted during the vertical interval as a series of pulses modulated on the FM audio carrier. The delay control signal detector is then a digital decoder which translates the delay control signals into digital signals for operating switches in the delay control 100. In the event that the delay control signals are modulated on a carrier adjacent to the FM audio carrier, traps and filters for extracting that carrier are also contained in the delay control signal detector. Tones of different frequency or other analog coding may be used for the delay control signals. Digitally coded serial signals are preferred.

These signals are generated in a dynamic delay control and control signal generating circuit which is digitally operative and is shown in FIG. 9. The output of divider 44 (FIG. 4) which also goes to the timing pulse shaper 46 is applied to a chain 107 of shift registers, the 64-bit variable bit length shift register 108 in that chain 107 and the 1-bit shift register 110 also in the chain 107 provide the dynamically variable delay (the function of the variable delay circuit 50 of FIG. 4). The register 108 is preset by 6 bits of a 7 bit digital signal obtained from data stored in a programmable read only memory (PROM) 112. The other of the 7 bits presets the 1-bit shift register 110. Digital codes corresponding to, for example, 12 different delays in 4.5 microsecond increments with a 1/2 microsecond resolution are stored in the PROM and are available at the 7-bit output and also at a 4-bit output thereof. The 4-bit output presets another shift register 114 which outputs the delay control signal.

A 4-bit code from the delay control addresses the PROM 112. The delay control may be a programmer 116, such as a counter which successively provides different ones of the 4 codes. These codes may be changed in sequence, in predetermined order, or in random or pseudorandom order as may be desired. The clock rate of the counter in the programmer 116 should be slower than the horizontal sync rate so that the code does not change any faster than the horizontal sync pulses occur. Sufficient security may be provided by a much slower change in the code, for example, each frame time or even after long periods of time such as minutes or even hours. The shift registers 108 and 110 have data therein corresponding to the divider pulse train. This data may be provided with a fixed predetermined delay by an input 64-bit variable bit length shift register 118 which is preset to desired bit length by a 6-bit code from a digital switch 120. Additional predetermined delay may be provided by an 8-bit variable length shift register 122 which is preset by another digital switch 124. The output of the chain may be from a 1-bit shift register 124 which is preset in the 0 state to provide a 1-bit (1 clock pulse delay). The 1-bit shift register 124 may be considered to be part of the predetermined or set-up delay.

The clock pulses for shifting data corresponding to the divider pulses through the chain 107 are obtained from a clock oscillator 126 which provides 0.125 microsecond pulse period clock pulses. These clock pulses clock only the 8-bit variable bit length shift register 122 which affords a variable delay of up to one microsecond in 1/8 microsecond steps. A divide by 4 divider 128 provides 1/2 microsecond clock pulses to the 1-bit shift register 110. A divide by 2 divider 130 provides 1 microsecond clock pulses to the 64-bit variable length shift registers 108 and 118. The register 118 can provide up to 64 microseconds of predetermined delay. The variable delay provided by the 64-bit register 108 and the 1-bit register 110 is the 12 selected delays which may be separated by 1/2 microsecond increments. The suppression pulses are generated from the output of the 8-bit variable bit length shift register 122. This is the delay t.sub.XT shown in wave form (d) of FIG. 8. The last shift register in the chain 124 begins the delay which occurs between the start of the timing pulse and the leading edge of the horizontal sync pulse. The 1-bit shift register 124 and other delay circuits 56 provide the set-up or predetermined delay and produce the output shown in wave form (e) of FIG. 8.

The control signal output from the PROM 112 (4 bits) is used to preset the last 4 bits (Q.sub.4 to Q.sub.8) of the shift register 114. A digital switch 132 presets the initial 4 bits (Q.sub.0 to Q.sub.3) of the register 114 with an enabling code. At the same time as the PROM outputs the 4 signal delay signal code to the shift register 14, the programmer 116 applies a preset enable pulse to the shift register 114 so as to preset the register with the enabling code and the 4-bit control signal code. The data in the shift register 114 is shifted out using a clock at a special delay control signal rate. This may be a divided down (to about 3.5 MHz) from the system clock pulse train (from the clock 126). Alternatively, a separate crystal clock which is stable in frequency may be used. As the clock shifts the data out of the register, the parallel multi-bit delay signal code is converted to a serial code. This serial digital control signal is applied to the head end modulator where it may be used to modulate the audio IF or a separate carrier as discussed above. All of the circuits shown in FIG. 9 such as digital circuits which may be implemented in integrated circuit form.

Referring to FIG. 10, there is shown a circuit which may be used in the delay control 100 of a descrambler of a system having the circuitry of FIG. 9 in the scrambler at the head end of the cable. Each receiving station which is authorized for premium programming will use a delay control such as shown in FIG. 10. The demodulated delay control signal from the detector 106 (FIG. 7) is shifted into an 8-bit shift register 134. The first four output stages thereof provide a 4-bit parallel signal to a comparator 136. A digital switch 138 applies the enable code (the same code determined by the digital switch 132 FIG. 9) to the comparator 136 for comparison with the 4-bit codes of the DCS signal. If the codes match, a pulse is generated by a one-shot 140, which enables a 4-bit latch circuit 142 to store the latter 4 bits in the shift register 134. The control signal code is then converted back into a 4-bit parallel digital signal. The shift register 134 is clocked at the DCS rate by clock pulses derived from a crystal clock 144 divided down to the DCS rate by a divider 146. The slower clock clocks the DCS code into a decoder which translates it into a 7-bit parallel digital signal. These 7 bits may be applied to a 64-bit and one-bit shift register similar to the registers 108 and 110 shown in FIG. 9, which provides the variable delay circuit 98. A microprocessor 148 may be suitably programmed to operate the decoder.

The pulse shaper 96 and variable delay circuit 98 functions to obtain selected ones of the twelve delays may be implemented as shown in FIG. 11. Detected pulses from the A M detector 94 (See FIG. 4.) trigger a pulse generator 150 which is clocked from a 3.58 MHz clock oscillator 152. The 280 nanosecond pulse from the pulse generator 150 resets the flip flop 154 and resets the counter 156 through OR gate 158. The delay control 00 (See FIG. 4) controls a count selector 160 which counts from zero to 176 clock pulses (approximately 49 microseconds) in eleven 16 pulse groups (approximately 4.5 microseconds each). After the selected clock pulses are counted, flip flop 154 is set. The setting of the flip flop 154 causes the generation of an approximately 100 nanosecond pulse from the pulse generator 162. The pulse from pulse generator 162 resets the counter 156 through OR gate 158 and sets flip flop 164. After the counter 156 has counted 36 clock pulses the pulse gate 166 resets the flip flop 164 which outputs the delayed shaped pulse to the control gate 102 (See. FIG. 7).

From the foregoing description it will be apparent that it has been provided improved systems and methods for scrambling and encoding and descrambling and decoding television signals which carry premium programming to subscribers. The herein described system provides increased security efficiency against unauthorized descrambling of such premium programming. Variations and modifications in the herein described methods and systems, within the scope of the invention, will undoubtedly suggest themselves to those skilled in this art. Accordingly, the foregoing description should be taken as illustrative and not in a limiting sense.