Auxiliary Scanning Control System for Facsimile

This invention relates to an auxiliary scanning control system for use in facsimile apparatus in which the regions between lines of an original or the blank region of the original is fast forwarded in the auxiliary scanning direction in facsimile transmission and reception so as to reduce communication time.

In a conventional auxiliary scanning control system, when the element reads a blank space on an original, a white line skip operation is generally effected. During the white line skip operation, the original is fast forwarded. When black information (data) is detected, the fast forwarding of the original is suspended, so that the original information on a line can be read out.

In such a conventional auxiliary scanning control system, the black information read out during the white line skip operation is neglected, and only the information read after the forwarding of the original has been stopped is employed as effective information. In general, there is a brief time delay between the detection time of the black information during the white line skip operation and the time at which the forwarding of the original is stopped. In other words, the position where the original is stopped may be slightly ahead of the top of the detected black data. Accordingly, the conventional auxiliary scanning control system suffers from a drawback such that when black data is read out immediately after a white line skip operation, the top portion of the black data is not read out.

Accordingly, an object of this invention is to eliminate the above-described difficulty accompanying the conventional auxiliary scanning control system. More specifically, an object of the invention is to provide an auxiliary scanning control system for a facsimile in which the top portion of the black data occurring immediately after the white line skip operation can be read out.

FIG. 1A is a block diagram of one embodiment of an auxiliary scanning control system for a facsimile according to this invention;

FIG. 1B is a block diagram showing part of the embodiment of FIG. 1A;

FIG. 2 is an explanatory diagram for describing the operation of the control system of FIG. 1A; and

FIG. 3 is a flow chart for describing the operation of a central processing unit unit used in memory control circuit.

FIG. 1A is a block diagram showing one preferred embodiment of the auxiliary scanning control system according to this invention. Reference numeral 1 designates a solid scanning image sensor; 2, a read control circuit; 3, a first gate circuit; 4, a first memory circuit; 5, a second memory circuit; 6, a second gate circuit; and 7, a memory control circuit.

FIG. 2 is a diagram for explaining the operation of the auxiliary scanning control system shown in FIG. 1A. In FIG. 2, reference numeral 8 designates a section of an original on which is shown the scanning condition of the image sensor which scans the original line by line. Reference numeral 10 designates a memory circuit section, in which the data read out by the image sensor are stored.

In the original section 8, reference characters 9a and 9b designate black portions of the original, and reference characters A.sub.1, A.sub.2, B.sub.1, . . . , H.sub.1 and H.sub.2 designate the loci of the image sensor scanning the original. The locus of the image sensor made when there is black information in a line is indicated by the solid lines, and the locus of the image sensor made when there is no black information in the line is as indicated by the dotted lines. In the memory circuit section 10, reference numerals 4 and 5 designate the first and second memory circuits shown in FIG. 1A, respectively. In the memory circuit section 10, each shaded portion indicates that black information has been written into the memory circuit.

The operation of the auxiliary scanning control system of the invention will be described with reference to FIGS. 1A and 2.

The scanning image sensor 1 reads information from the original line by line in response to a control signal from the read control circuit 2. The original information thus read out is applied through the gate circuit 3 and a switch S.sub.1 to either the first or second memory circuit 4, 5, and is stored therein. Each of the memory circuits 4 and 5 has a memory capacity corresponding to one line. The switches S.sub.1 and S.sub.2 are oppositely switched, or are switched in opposite phase to each other by a signal provided by the memory control circuit 7 according to whether or not a black signal is contained in a line provided by the read control circuit 2. For instance, in the case where data has been stored in the first memory circuit 4, the previously stored data is read out of the second memory circuit 5. Writing data into and reading data out of the first and second memory circuits 4 and 5 is controlled by control signals from the memory control circuit 7, which wll be described hereafter. In addition to the switch S.sub.2, a switch S.sub. 3 is provided at the output side of the memory circuits 4 and 5. The switch S.sub.3 is switched in phase with the seitch S.sub.1. When black information is contained in a line being scanned, the gate circuit 6 is enabled to allow information to pass therethrough whereas when no black information is contained in a line being scanned, the gate circuit 6 is disabled to stop the passage of information. This control is effected by signals provided by the memory control circuit 7, which will be described hereafter.

When a line A.sub.1 of the original is read out by the solid image sensor 1 as indicated in FIG. 2, the information is stored in the memory circuit 4. Since black information is contained in the line A.sub.1, the control signal for enabling the gate circuit 6 is applied to the gate circuit 6 from the memory control circuit 7. As a result, the information stored in the first memory circuit 4 is delivered to the input side of the gate circuit 3, where it is added to the information on the line A.sub.2 which is read out in succession. This resultant added information (A in FIG. 2) is stored in the first memory circuit 4.

Thereafter, the switches S.sub.1, S.sub.2 and S.sub.3 are switched in the above-described phase relations, so that subsequent information read from the original is stored in the second memory circuit 5, while the data A stored in the first memory circuit 4 is read out. If no black data is contained in the next line B.sub.1, the white line skip operation is effected beginning from the next line. During this period, the white data are stored in the second memory circuit 5. If, during the white line skip operation, black data is read from the original, the black data is written in the second memory circuit 5 and the movement of the original is stopped. Under this condition (the original being stopped), the line G.sub.1 is read. Similarly as in the above-described case, the information of the line F.sub.1 is applied through the second gate circuit 6 to the input side of the first gate circuit 3, where it is added to the information of the line G.sub.1, and the resultant added information is written in the second memory circuit 5.

In succession, the states of the switches S.sub.1, S.sub.2 and S.sub.3 are changed back to their original states. The information of the lines H.sub.1 and H.sub.2 are added, similarly as in the above-described case, and the resultant added information is stored in the first memory circuit 4, while the information (F.sub.1 +G.sub.1) obtained by adding the information of line F.sub.1 to that of the line G.sub.1 is read out of the memory circuit 5.

In the above-described embodiment, the information of the line F.sub.1 which is neglected in the conventional system, is superposed on the information of the line G.sub.1 so as to be stored in the memory circuit.

Next, the control operations of the memory control circuit 7, which are executed by a central processing unit (CPU), will be described with reference to FIGS. 1B and 3. FIG. 1B is a block diagram showing the image sensor 1, the read control circuit 2, and the memory control circuit (CPU) 7. FIG. 3 is a flow chart for describing one example of the sequence control executed by the CPU.

In the initial state, the second memory circuit 5 has been selected. Firstly, judgement is made as to whether or not the rising edge of an XPHP (Xmit Phasing Period) pulse signal is detected, and thereafter upon detection of the same it is determined whether the falling edge of the XPHP pulse signal is detected. The XPHP pulse signal is provided as a phase signal, for the purpose of phasing check, and has a period of, for instance, 138.9 msec within which the high level duration is set to 6.25 msec. After the falling edge of the XPHP pulse signal has been confirmed, a signal for enabling the CPU is applied to the latter and the memory 4 is selected.

An SDCBSY (Scan Data Counter Busy) pulse signal is applied to the CPU from an SDC (Scan Data Counter) 21 which, together with a WLD (White Line Detector) 22, constitutes the read control circuit 2, and it is determined whether or not the SDCBSY pulse signal is at a high level. While the SDCBSY pulse signal is maintained at the high level, the video data is read out from the original line by line by the image sensor 1. When it is judged that the SDCBSY signal is at the low level, a MWRT (Memory Write) pulse signal is issued from the CPU and the data is written in the memory 4 which has been selected. After the data is written therein, an Xmit motor (not shown) is driven by applying driving pulses thereto so that the next line can be read out.

An XSKIP (Xmit Skip Line) signal is applied to the CPU from the WLD 22, which is set at high level in the initial state and is changed to the low level when black data is contained in the line being read out by the image sensor 1. When black data is contained in the line, i.e. when the XSKIP pulse signal is at the low level, the first memory 4 is selected by the CPU upon once again effecting the phasing check. Thereafter, an ENDOR (Enable Data Or) pulse signal is issued from the CPU so that the second gate 6 is enabled to thereby add the data which has been stored in the first memory 4 to the data being currently read out by the image sensor 1. Then, the MWRT pulse signal is again issued from the CPU so that the resultant added signal is written in the memory circuit 4. The above-described routine is continuously executed.

As is apparent from the above description, according to the invention, the black information of a line detected during the white line skip operation is added to the information of the next line, and therefore the problem arising due to the top of the black information being missed. When the white line skip operation is switched back to black information reading is eliminated.