US 4,462,057 AGrant
A.C. Switching Circuit
Issue Date:1984-07-24
•4 Claims
•5 Drawing Sheets
Abstract
A.C. switching circuit capable of opening and closing contacts without generating any arc. When D.C. source restores from its interruption, the contacts are maintained in or shifted to a predetermined state. A change-over switch is provided for selecting as required whether the contacts are to be forcibly opened or closed after the D.C. source interruption, or whether the previous state of the contacts is to be maintained.
Metadata
Assignee
- Matsushita Electric Works, Ltd.
Inventors
- Masato Kobayashi
- Hideki Fukuzono
- Hiromi Nishimura
Application Information
Application Number:US 4122445
Filing Date:1982-08-27
Priority Date:1981-09-04
Art Unit:216
Classifications
IPC:
H02H 300H02H 700
Field of Search:
3612;3;7
Patent Drawings (5 sheets)
Description
Background of the Invention
The present invention relates to an A.C. switching circuit which is inserted between an A.C. source and a load circuit and is capable of preventing an arc from being generated between contacts upon their opening or closing operation.
There has been suggested one of the A.C. switching circuits of the kind referred to in, for example, German Pat. No. 1,161,618, but the circuit of this patent still has been defective in the following respects. According to the patent, a first relay switch is connected in series with an A.C. source and a load, a series circuit of a diode and second relay switch is inserted in parallel to the first relay switch, and the two relay switches are opened or closed respectively by a further relay which is driven by a flip-flop. However, it is difficult to control the opening and closing operations of the first and second relay switches at a proper timing. More specifically, the second realy switch is closed during each negative half cycle of the A.C. source current to apply a positive voltage to the diode so as to prevent the arc generation at the second relay switch, while the first relay switch is closed during each positive half cycle of the source current, upon which closing the arc generation is also prevented from occurring because of the same potential with the diode. Further, the first relay switch is opened during the positive half cycle of the source current and the second relay switch is opened during the negative half cycle to prevent the arc generation. However, this operation has the disadvantage of requiring the relay switches opened and closed in a very accurately timed relation. In addition, in the case where the relays are of latching type and D.C. source voltage restores from an interruption, it is necessary to initially reset the relays and to subsequently detect the state of the flip-flop, whereby the circuit arrangement has been made rather complicated.
Summary of the Invention
Accordingly, a primary object of the present invention is to provide an A.C. switching circuit which can automatically prevent any arc from being generated upon opening and closing operations of switching contacts.
Another object of the invention is to provide an A.C. switching circuit which can automatically open the contacts when D.C. source restores from an interruption.
A further object of the invention is to provide an A.C. switching circuit which can maintain, if required, a previous state of the contacts upon the restoration of the D.C. source from the interruption.
Still another object of the invention is to provide an A.C. switching circuit which can automatically open the contacts when the D.C. source is restored after its interruption and automatically prevent any arc from being generated upon opening and closing operations of the contacts.
A still further object of the invention is to provide an A.C. switching circuit which can maintain, as required, the contacts in the previous state at the time of the restoration of the D.C. source from the interruption while automatically preventing the arc generation from occurring upon the opening and closing operations of the contacts.
Brief Description of the Drawings
Other objects and advantages of the present invention will become clear from the following description of the invention detailed with reference to accompanying drawings, in which:
FIGS. 1A through 1C show a circuit diagram of a preferred embodiment of an A.C. swtiching circuit in accordance with the present invention, in which FIGS. 1A and 1B are to be referred to as joined as shown in FIG. 1C;
FIGS. 2A and 2B are explanatory views for the opening and closing operations of contacts without any arcing in the circuit of FIG. 1 during a steady supply of an A.C. source voltage; and
FIGS. 3A and 3B are explanatory views for a forcible contact opening and closing operations in the circuit of FIG. 1 at the time when the D.C. source restores from its interruption.
Description of the Preferred Embodiments
While the A.C. switching circuit of the present invention shall now be detailed with reference to the preferred embodiment shown in the drawings, it should be understood that the description is made only for ready understanding of the invention and the intention is not to limit the invention only to that embodiment but rather to cover all alterations, modifications and equivalent arrangements possible within the scope of appended claims.
The A.C. switching circuit according to the present invention is capable of performing various operations under various conditions for achieving the respective objects of the invention, and such operations shall be detailed respectively in the followings in conjunction with the circuit arrangement shown in the drawings.
I. Contact Opening and Closing Operations with A.C. Source Voltage Being Steady:
Referring to FIGS. 1 through 3, an A.C. source ACS is applying a voltage V.sub.ACS to a load circuit LD through a parallel circuit of relay contacts ry1 and ry2. A diode D.sub.o is connected in series with the relay contact ry1 and a primary winding of a transformer TRS is connected in parallel to the relay contact ry2.
(1) When ry1 and rys in open state are closed:
So long as the contacts ry1 and ry2 are open, the voltage V.sub.ACS is applied to the primary winding of TRS through the load LD, whereby a voltage V.sub.TRS is provided across a secondary winding of TRS, which voltage is made to be a rectangular-wave voltage V.sub.REC1 by a rectangular-wave forming circuit REC1. The voltage V.sub.REC1 is modified by a differentiation circuit DIF.sub.1 to a pulse PUL.sub.1 of a small width for detecting the open or closed state of the relay contacts and is further modified by a delay circuit DL.sub.1, becoming delay pulse PUL.sub.1DL. On the other hand, a current transformer CTRS is disposed adjacent a junction between the load LD and the relay contacts ry1 and ry2. A detection output V.sub.CTRS of this CTRS is subustantially zero, since a current flowing through the primary winding of TRS through the load LD is of a small value. Therefore, an output V.sub.REC2 of another rectangular-wave forming circuit REC.sub.2, another contact state detecting pulse PUL.sub.2 provided as an output of another differentiation circuit DIF.sub.2 and another delay pulse PUL.sub.2DL provided as an output of another delay circuit DL.sub.2 are all zero.
When an instruction for closing the contacts ry1 and ry2 is applied to an input terminal TRM.sub.1, that is, when an instruction signal S.sub.ONOFF for opening or closing ry1 and ry2 is at its high level, a signal applied through a noise limiter NOSL to one of input terminals of a NAND gate NAND.sub.1 (which may be regarded substantially as identical to the signal S.sub.ONOFF and thus shall be referred to hereinafter as the signal S.sub.ONOFF) is also made at a high level. An output from the gate NAND.sub.1 varies according to an input applied to the other input terminal. Here, a signal being provided to an input terminal TRM.sub.2 of a reset-signal generating circuit REST in a D.C. voltage V.sub.cc. As a result, a high level signal S.sub.REST1 is provided to the other input terminal of NAND.sub.1 which thus generates an output signal S.sub.NAND1 of low level, as will be detailed in the following.
An AND gate AND.sub.1 receives at an input terminal an inverted signal S.sub.NAND1 of S.sub.NAND1 as inverted by an inverter INV.sub.1 and at the other input terminal the pulse signal PUL.sub.1DL, and thus the gate AND.sub.1 generates an output S.sub.AND1 in response to PUL.sub.1DL. On the other hand, an AND gate AND.sub.2 receives at first one of three input terminals the delay pulse PUL.sub.2DL, at second input terminal another output signal S.sub.REST2 from the reset signal generator REST and at third input terminal an inverted signal S.sub.AND3 to which a logical product signal S.sub.AND3 from an AND gate AND.sub.3 of the signal S.sub.REST2 and a further signal S.sub.REST3 of REST is inverted by an inverter INV.sub.2. Since PUL.sub.2DL is at low level, the gate AND.sub.2 generates a low level output S.sub.AND2, while an AND gate AND.sub.4 receiving S.sub.NAND1 and S.sub.AND2 produces an output signal S.sub.AND4 of low level.
The signal S.sub.AND3 is provided to an AND gate AND.sub.5 which also receives PUL.sub.2DL and, as this PUL.sub.2DL is at low level, the gate AND.sub.5 generates a low level output signal S.sub.AND5. As will be referred to later, S.sub.AND3 is at low level because a constant voltage V.sub.cc is applied to the terminal TRM.sub.2. Therefore, an NOR gate NOR.sub.1 receives S.sub.AND3 and S.sub.AND3, the latter being inverted here by means of an inverter INV.sub.3' and generates a low level output S.sub.NOR1. An output S.sub.AND6 of an AND gate AND.sub.6 receiving at one input terminal the signal S.sub.NOR1 from NOR.sub.1 is kept always at low level regardless of the input level applied to the other input. Further, an OR gate OR.sub.1 receives S.sub.AND5 and S.sub.AND6 and generates a low level output signal S.sub.OR1.
An OR gate OR.sub.2 receiving the signals S.sub.AND1, S.sub.AND4 and S.sub.OR1 produces an output signal S.sub.OR2 substantially of the same contents as S.sub.AND1, because S.sub.AND4 and S.sub.OR1 are both at low level as has been explained above. The signal S.sub.OR2 is provided to a monostable multivibrator MONM.sub.1 to be converted to a signal S.sub.MNOM1 having a pulse width W.sub.1, which is provided through the inverter INV.sub.3 to an AND gate AND.sub.7 and its inverted signal S.sub.MONM1 through an inverter INV.sub.4 is provided also to this gate AND.sub.7. While the gate AND.sub.7 receives the signal S.sub.MONM1 and its re-inverted signal S.sub.MONM1, the latter of which is slightly delayed with respect to S.sub.MONM1 because the inverter INV.sub.4 has an inherent delay time and, as a result, the AND gate AND.sub.7 provides at its output terminal an output pulse signal S.sub.AND7 of a short pulse width and delaying by a width W.sub.1 with respect to S.sub.OR2.
Since an OR gate OR.sub.3 which receiving at an input terminal the signal S.sub.AND7 also receives at the other input terminal the signal S.sub.OR2 through a buffer BUF, the gate OR.sub.3 provides an output signal S.sub.OR3 which including the pulse of S.sub.OR2 and another pulse also of a short width and delaying by the width W.sub.1 with respect to S.sub.OR2, whereby a monostable multivibrator MONM.sub.2 is coused to provide at its output terminal an output signal S.sub.MONM2 comprising two pulses respectively of a pulse width W.sub.2 smaller than the width W.sub.1 and appearing with a slight time interval (W.sub.1 -W.sub.2). A NOR gate NOR.sub.2 receiving the signal S.sub.MONM2 also receives the signal S.sub.MONM1 and generates a high level signal S.sub.NOR2 which is provided to an AND gate AND.sub.6 only when the input signals are both at low level. However, this will not affect the operation of the switching circuit as has been explained above.
An AND gate AND.sub.8 receives the signals S.sub.NAND1, S.sub.MONM1 and S.sub.MONM2 and provides at its output terminal an output signal S.sub.AND8 having the pulse width W.sub.2, an AND gate AND.sub.9 receives S.sub.NAND1, S.sub.MONM1 and S.sub.MONM2 and provides an output signal S.sub.AND9 of the width W.sub.2, an AND gate AND.sub.10 receives S.sub.NAND1, S.sub.MONM1 and S.sub.MONM2 and provides an output signal S.sub.AND10 of the width W.sub.2, and an AND gate AND.sub.11 receives S.sub.NAND1, S.sub.MONM1 and S.sub.MONM2 and provides an output signal S.sub.AND11 also of the width W.sub.2. There exists a time interval (W.sub.1 -W.sub.2) between the respective pulses of S.sub.AND8 and S.sub.AND10 and also between those of S.sub.AND9 and S.sub.AND11, whereas a time interval substantially equal to the high level duration of S.sub.ONOFF exists between the pulse of S.sub.AND8 and those of S.sub.AND9 and S.sub.AND11 and between the pulse of S.sub.AND10 and those of S.sub.AND9 and S.sub.AND11.
The signals S.sub.AND8 and S.sub.AND9 are provided to a flip-flop FF.sub.1 for driving a latching relay R.sub.y1 which operates the relay contact ry1, while the signals S.sub.AND10 and S.sub.AND11 are provided to a flip-flop FF.sub.2 for a latching relay R.sub.y2 operating the relay contact ry2. The flip-flop FF.sub.1 is activated in response to S.sub.AND8 to cause a current to flow through the relay R.sub.y1 in a rightward direction in FIG. 1 and the relay contact ry1 to be closed, whereas the flip-flop FF.sub.2 responds to S.sub.AND10 to cause a current to flow through the relay R.sub.y2 also in the rightward direction and the relay contact ry2 closed.
Since the pulse PUL.sub.1 is being generated when the voltage V.sub.TRS delayed with respect to the voltage V.sub.ACS alters from its negative half cycle to the positive half cycly, PUL.sub.1DL is positioned in the positive half cycle of V.sub.TRS, and S.sub.MONM1 rises at the positive half cycle of V.sub.TRS and, after the pulse width W.sub.1, falls at the negative half cycle. In other words, S.sub.MONM1 rises at the positive half cycle of V.sub.ACS and drops at its negative half cycle, whereas S.sub.MONM2 rises at the both positive and negative half cycles of V.sub.ACS. S.sub.AND8 and S.sub.AND10 rise respectively at each of the positive and negative half cycles of V.sub.ACS. The relay contact ry1 requires a time W.sub.3 (.ltoreq.W.sub.2) for its closing operation but, by setting the terminating point of the time W.sub.3 running from the rising point of S.sub.AND8 to be in the negative half cycle of V.sub.ACS, the relay contact ry1 can be closed during the negative half cycle of V.sub.ACS so that any arc can be prevented from occurring. Similarly, the relay contact ry2 requires a time W.sub.4 (.ltoreq.W.sub.2) for the closing but, by setting the time W.sub.4 from the rising of S.sub.AND10 to be in the positive half cycle of V.sub.ACS, ry2 can be closed during the positive half cycle of V.sub.ACS without any arc generation. As will be clear from a comparison of respective states of the contacts denoted by S.sub.SW1 and S.sub.SW2 with V.sub.ACS, there is applied to the load LD through ry1 and ry2 a current C.sub.LD which has an angle of lag .theta. with respect to V.sub.ACS and partly flows through the diode D.sub.o during periods shown as hatched in the wave-form diagram of FIG. 2B, whereby any arcing at the time of closing ry2 can be prevented.
It will be clear that ry2 is closed during the positive half cycle of V.sub.ACS since V.sub.ACS and C.sub.LD respectively have a zero-cross A.sub.o at an identical time point.
(2) When ry1 and ry2 in closed state are opened:
So long as the contacts ry1 and ry2 are closed, the current C.sub.LD is supplied to the load LD from the source ACS and the respective voltages V.sub.TRS, V.sub.REC1 and pulses PUL.sub.1, PUL.sub.1DL are all at low level and the respective wave-forms and pulses of the voltages V.sub.CTRS, V.sub.REC2 and pulses PUL.sub.2, PUL.sub.2DL appear. The signal S.sub.AND1 is at low level because PUL.sub.1DL is at low level. The signal S.sub.AND2 of the logical product of PUL.sub.2DL, S.sub.REST2 and S.sub.AND3 will be at high level only when PUL.sub.2DL is at high level, because S.sub.REST2 and S.sub.AND3 are both at high level as will be clear from the foregoing.
When the signal S.sub.ONOFF is turned to be low level, the signal S.sub.NAND1 becomes high level. The signal S.sub.AND4 is a logical product of S.sub.NAND1 and S.sub.AND2 and is thus substantially of the same contents as S.sub.AND2. The signal S.sub.OR1 is at low level as will be clear from the foregoing and the signal S.sub.OR2 is substantially of the same contents as S.sub.AND4 and also as S.sub.AND2.
Substantially in the same manner, S.sub.AND8 to S.sub.AND11 are applied to the flip-flops FF.sub.1 and FF.sub.2 which are activated in the order opposite to the above to cause a current to flow through the respective relays R.sub.y1 and R.sub.y2 in the direction opposite to each other, whereby the relay contact ry2 can be opened in a positive half cycle of Cld and the relay contact ry1 can be opened in its negative half cycle so that the arc generation can be effectively prevented.
II. Initial Stage Resetting with D.C. Source Restored from Long Interruption:
In the case when the D.C. voltage V.sub.CC being provided to the input terminal TRM.sub.2 (which may be prepared from V.sub.ACS through a rectifier but may even be obtained from an independent source, as will be evident) is interrupted for a relatively long time (the interruption has lasted over a response time of the reset signal generating circuit REST) and is thereafter restored, the relay contacts ry1 and ry2 are to be forcibly opened. (This function is not performed upon a mere momentary interruption of the voltage).
(1) When the interruption has occurred in closed state of ry1 and ry2:
As soon as V.sub.CC restored reaches a Zener voltage V.sub.ZD1 of a Zener diode ZD.sub.1, a transistor TR.sub.1 is made conductive, due to which a transistor TR.sub.2 is made non-conductive and its collector voltage V.sub.TR2 is made to be at high level (V.sub.TR2 is provided as S.sub.REST2). Upon non-conduction of (TR.sub.2, a transistor TR.sub.3 is conducted and its collector voltage V.sub.TR3 exists as a pulse present up to this time from the beginning of the restoration of V.sub.CC. Upon the conduction of TR.sub.3, trnasistors TR.sub.4 to TR.sub.6 are made non-conductive, responsive to which of TR.sub.4 and TR.sub.5 a condenser CON.sub.1 starts its charging through a diode D.sub.1 to gradually increase a charging voltage V.sub.CON1 as well as a collector voltage V.sub.TR5 of the transistor TR.sub.5, and this voltage V.sub.TR5 is provided as S.sub.REST1. By the non-conduction of TR.sub.6, a charging of a condenser CON.sub.2 is initiated and, when its charging voltage V.sub.CON2 reaches a Zener voltage V.sub.ZD2 of a A Zener diode ZD.sub.2, a transistor TR.sub.7 is conducted, upon which its collector voltage V.sub.TR7 becomes low level. Therefore, the signal S.sub.REST3 increases gradually from the beginning of the restoration of V.sub.CC to the non-conduction of TR.sub.7. As the signal S.sub.AND3 is a logical product of S.sub.REST2 and S.sub.REST3, the signal will be a pulse which rises in correspondence to the rise of V.sub.TR2 and falls in correspondence to the fall of V.sub.TR7, thus having a pulse width of W.sub.5.
Under a condition where the signal S.sub.ONOFF is kept at high level, the high level signals S.sub.ONOFF and S.sub.REST1 are applied to the gate NAND.sub.1, so that the signal S.sub.NAND1 is kept at high level until S.sub.REST1, that is, V.sub.CON1 reaches a predetermined level "Th".
While the signal S.sub.AND3 is provided to the gate AND.sub.2 which also receiving S.sub.REST2, this S.sub.AND3 is a signal which becomes high level gradually after V.sub.CC is restored to a predetermined level and becomes low level during the high level period of S.sub.AND3. Since the pulse PUL.sub.2DL applied to the gate AND.sub.2 is set to exist during the low level period of S.sub.AND3, S.sub.AND2 is always at low level.
Since S.sub.NAND1 is provided, together with S.sub.AND2, to the gate AND.sub.4, the signal S.sub.AND4 is always at low level. Further, S.sub.NAND1 is kept at low level until V.sub.CON1 reaches a predetermined level and S.sub.NAND1 becomes low level, during which period S.sub.AND1 is at low level (the time required for V.sub.CON1 to reach the predetermined level "Th" from its initiation of increase shall be referred to as a width W.sub.6).
As the pulse PUL.sub.2DL is present during the high level period of S.sub.AND3, a corresponding pulse is included in the output S.sub.AND5 of the gate AND.sub.5. On the other hand, the signal S.sub.NOR1 includes a period in which the both inputs to the gate NOR.sub.1 become low level when S.sub.AND3 falls, due to that the inverter INV.sub.3 has an inherent delay time. The inputs to the gate AND.sub.6 include S.sub.NOR2 in addition to S.sub.NOR1 but, as the level of S.sub.NOR2 is not clear, references shall be made here with an assumption that S.sub.OR1 includes S.sub.AND5.
The signal S.sub.OR2 is a logical sum of the signals S.sub.AND1, S.sub.AND4 and S.sub.OR1, in which at least S.sub.OR1 is at high level while others are low level, and S.sub.OR2 has a pulse corresponding to that of S.sub.OR1.
In the similar manner to the above, the signals S.sub.MONM1, S.sub.MONM2, S.sub.AND11 and S.sub.AND9 are generated to open the relay contacts ry2 and ry1 in this order, while preventing the arc generation. After the restoration of V.sub.CC to a predetermined level, S.sub.NOR2 becomes gradually high level and thereafter is made at low level only during high level period (W.sub.1 +W.sub.2 =W.sub.7) of S.sub.MONM1 and S.sub.MONM2. After the opening of the contacts, no pulse corresponding to S.sub.NOR1 appears in S.sub.AND6. S.sub.NOR1 is useless here, since the relay contacts ry1 and ry2 are already opened.
(2) When the interruption has occurred in open state of ry1 and ry2:
In this case, the pulse PUL.sub.2DL is not present but the pulse PUL.sub.1DL appears, as will be clear from the foregoing descriptions. Under a condition where S.sub.ONOFF is at low level, S.sub.NAND1 is at high level, and S.sub.AND1 and S.sub.AND4 are both at low level. While S.sub.AND3 has a rectangular pulse of the width W.sub.5, PUL.sub.2DL is at low level anr S.sub.AND5 is made to be at low level. In the signal S.sub.NOR1, however, a pulse of a short width appears as described in the above and, as S.sub.MONM1 and S.sub.MONM2 are both at low level at this time, S.sub.NOR2 will be at high level. As a result, pulses appear in S.sub.AND6, S.sub.OR1 and consequently in S.sub.OR2. In the similar manner to the above, the flip-flops FF.sub.1 and FF.sub.2 are activated to drive the latching relays R.sub.y1 and R.sub.y2. Since the relay contacts ry1 and ry2 have already been opened, however, this operation is effective only as a safety measure against a possible manual closing of the relay contacts ry1 and ry2 while V.sub.ACS has been interrupted.
As will be clear from the above, the relay contacts ry1 and ry2 can be forcibly opened in the case when V.sub.CC is restored after its interruption.
While the explanation has been made with reference to the case where the signal S.sub.ONOFF maintains the same state before and after the interruption of V.sub.CC, it should be readily appreciated that the initial resetting operation can be achieved in the similar manner to the above even in an event where S.sub.ONOFF is altered after the V.sub.CC interruption and ry1 and ry2 are made open irrespective of the high level of S.sub.ONOFF or made closed irrespective of the low level of S.sub.ONOFF. An explanation thereof is a repetition of the above and shall be omitted here.
While the above has been referred to in respect of the case where V.sub.ACS exists, the same operation can be performed even when V.sub.ACS does not exist due to a service interruption or the like. In the latter event, PUL.sub.1DL and PUL.sub.2DL are not present, but a rectangular pulse of the width W.sub.5 is produced in S.sub.AND3, whereby a pulse of a small width is produced in S.sub.AND6, as well as in S.sub.OR2, and these pulses will cause the same operation as above to be performed as to actute the flip-flop FF.sub.1 and FF.sub.2, resulting in the opening of ry1 and ry2. In this case, the opening is made without arc generation irrespective of the timing of the opening, since V.sub.ACS is absent. This should also apply to an event of such initial stage setting operation as would be referred to in the followings.
III. Initial Stage Setting with D.C. Source Restored from Interruption:
When V.sub.CC restores from its interruption, the relay contacts ry1 and ry2 are forcibly closed. It will be apparent that, for this purpose, an operation opposite to the initial resetting operation may be performed, that is, the high level signals are to be provided from the gates AND.sub.8 and AND.sub.10, instead of AND.sub.9 and AND.sub.11, and that, accordingly, S.sub.NAND1 is to be made low level and S.sub.NAND1 is to be high level. Since it is apparent from the foregoing that ry1 and ry2 may be shifted from their open state to the closed state, it is obviously required only to insert an inverter INV at the output end of the gate NAND.sub.1.
IV. Contact State Maintenance with D.C. Source Restored from Interruption:
Upon the restoration of V.sub.CC from its interruption, the relay contacts ry1 and ry2 are to be maintained in their previous state, that is, in the opened or closed state in which ry1 and ry2 have been set prior to the interruption. To this end, the respective outputs of the gates AND.sub.8 to AND.sub.11 should not be varied and, in this case, S.sub.AND3 should have a high level pulse, as will be clear from the foregoings. Accordingly, S.sub.REST3 should be at low level and, to achieve this, it may be sufficient that a junction point between the Zener diode ZD.sub.2 and the condenser CON.sub.2 is disconnected and a change-over switch is provided for connecting the Zener diode ZD.sub.2 in parallel with a collector resistance of the transistor TR.sub.7.
It will be appreciated from the above descriptions that, if the initial stage resetting and setting operations and contact state maintaining operation of the present invention are not required, then the respective elements AND.sub.2, AND.sub.5, AND.sub.6, INV.sub.2, INV.sub.3, NOR.sub.1, NOR.sub.2 and OR.sub.1 can be removed, so that the output signal S.sub.AND3 of the gate AND.sub.3 may be applied directly to the gate OR.sub.2 and the signal pulse PUL.sub.2DL may be applied directly to the gate AND.sub.4.
In summary, in accordance with the present invention, the relay contacts can be opened and closed without causing any arc to be generated, the relay contacts can be forcibly opened or closed in the case of the D.C. source interruption and, as required, the state of the relay contacts prior to the source interruption can be safely maintained even after the restoration.
Claims
What is claimed as our invention is:
1. An A.C. switching circuit including a first contact means connected through a diode in series with an A.C. source and a load, a second contact means connected in parallel with a series circuit of said diode and said first contact means, first and second latching relays respectively for driving said first and second contact means to open and close their contacts, and first and second flip-flops respectively for actuating said first and second latching relays; said switching circuit comprising (a) a first detection circuit for generating a pulse in response to each cycle of an A.C. source current when said first and second contact means are opened, (b) a second detection circuit for generating a pulse in response to each said cycle of said source current when the first and second contact means are closed, (c) a signal source of instructions for opening and closing the first and second contact means, (d) a first gate circuit allowing an output of said first detection circuit passed therethrough when an instruction for closing the first and second contact means is provided from said signal source, (e) a second gate circuit allowing an output of said second detection circuit passed therethrough when an instruction for opening the first and second contact means is provided from the signal source, (f) a first monostable multivibrator generating an output of a predetermined width in response to outputs of said first and second gate circuits, (g) a second monostable multivibrator generating an output having a width smaller than said predetermined width of said output of said first multivibrator, (h) third and fourth gate circuits applying said outputs of said first and second multivibrators to a first drive terminal of each of said first and second flip-flops when said instruction for closing the first and second contact means is provided from the signal source, and (i) fifth and sixth gate circuits applying said outputs of said first and second multivibrators to a second drive terminal of each of said first and second flip-flops when said instruction for opening the first and second contact means is provided from the signal source.
2. A circuit according to claim 1, wherein said first to sixth gate circuits respectively comprise an AND gate, said AND gate of the first gate circuit being connected at one input terminal to said first detection circuit and at the other input terminal to said instruction signal source, said AND gate of the second gate circuit being connected at one input terminal to said second detection circuit and at the other input terminal to said signal source through an inverter, said AND gate of the third gate circuit being connected at first and second input terminals respectively to output terminals of said first and second multivibrators and at a third input terminal to the signal source, said AND gate of the fourth gate circuit being connected at a first input terminal to said output terminal of the first multivibrator through an inverter, at a second input terminal directly to said output terminal of the second multivibrator and at a third input terminal directly to the signal source, said AND gate of the fifth gate circuit being connected at a first input terminal to the output terminal of the first multivibrator through an inverter, at a second input terminal directly to the output terminal of the second multivibrator and at a third input terminal to the signal source through an inverter, and said AND gate of the sixth gate circuit being connected at first and second input terminals respectively to each of the output terminals of the first and second multivibrators and at a third input terminal to the signal source through an inverter, whereby the signal source generates signals respectively of high level in response to said contact opening instruction and of low level in response to said contact closing instruction.
3. A circuit according to claim 1 or 2, which further comprises a circuit for detecting a restoration of interrupted D.C. source and generating a signal which varies during a predetermined period only upon said restoration, said signal being provided to an input terminal of said first monostable multivibrator, whereby at least one of forcibly opening and closing operations of said first and second contacts and their previous-state maintaining operation is performed.
4. A circuit according to claim 2, which further comprises a circuit for detecting a restoration of interrupted D.C. source and generating a first signal which increases upon a predetermined level reached by a restored source voltage after the interruption, a second signal which is at high level upon said predetermined level reached and a third signal which increases as said interrupted D.C. source starts to restore and becomes low level before said first signal reaches another predetermined level; a NAND gate which receives said instruction signals from said signal source and said first signal from said restoration detecting circuit, said NAND gate being connected at an output terminal directly to said the other input terminal of said second AND gate and said third input terminal of respective said fifth and sixth AND gates, and through an inverter to said the other input terminal of said first AND gate and said third input terminal of respective said third and fourth AND gates; a seventh AND gate which receives said second and third signals of the restoration detecting circuit; an eighth AND gate connected to an output terminal of said seventh AND gate and an output terminal of said second detection circuit; a first NOR gate connected at one input terminal directly and at the other input terminal through a inverter to said output terminal of the seventh AND gate; a ninth AND gate connected at one input terminal to an output terminal of said first NOR gate; a second NOR gate connected at an input terminal to the output terminals of said first and second monostable multivibrators and at an output terminal to the other input terminal of said ninth AND gate; a first OR gate connected at an input terminal to the output terminals of said eighth and ninth AND gates; a second OR gate connected at respective input terminals to the output terminals of said first and second AND gates and to the output terminal of said first NOR gate and at an output terminal to the input terminal to said first multivibrator; and a tenth AND gate which receives directly an output from said second detection circuit and said second signal from said restoration detecting circuit and through an inverter an output from said seventh AND gate, and provides an output to said one input terminal of said second AND gate.
Patent Citations (2)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3283179 | 1966-11-01 | Carlisle et al. | |
| GBX963007 | 1964-07-01 |