US 4,460,959 AGrant
Logic Control System Including Cache Memory for CPU-memory Transfers
Issue Date:1984-07-17
•3 Claims
•4 Drawing Sheets
Abstract
A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
Metadata
Assignee
- Honeywell Information Systems Inc.
Inventors
- Richard A. Lemay
- Philip E. Stanley
- William E. Woods
- David E. Cushing
Application Information
Application Number:US 3029042
Filing Date:1981-09-16
Priority Date:1981-09-16
Art Unit:236
Classifications
IPC:
G06F 1300
Field of Search:
364200 MS File;900 MS File
Patent Drawings (4 sheets)
Description
Related Applications
The following U.S. patent applications filed on an even date with the instant application and assigned to the same assignee as the instant application are related to the instant application and are incorporated herein by reference.
1. "Logic Control System for Efficient Memory to CPU Transfers" by David E. Cushing, Richard A. Lemay, Philip E. Stanley and William E. Woods, having U.S. Ser. No. 302,902 and filed on Sept. 16, 1981.
2. "Instruction Decoding Logic System" by Philip E. Stanley, William E. Woods and Richard A. Lemay, having U.S. Ser. No. 302,897 and filed on Sept. 16, 1981.
3. "Flexible Logic Transfer and Instruction Decoding System" by William E. Woods, David E. Cushing, Richard A. Lemay and Philip E. Stanley, having U.S. Ser. No. 302,903 and filed on Sept. 16, 1981.
4. "Logic Transfer and Decoding System" by David E. Cushing, Richard A. Lemay, Philip E. Stanley and William E. Woods, having U.S. Ser. No. 302,898 and filed on Sept. 16, 1981.
Background of the Invention
1. Field of the Invention
The invention relates to a hardware/firmware control system for providing to a CPU (central processing unit) both instructions and procedural information such as constants, displacements, and addresses stored in a central memory system, and more particularly to a logic control system which may accommodate the transfer of information to the CPU without compromising either the memory system bandwidth or CPU execution speeds.
2. Prior Art
In logic control systems heretofore used in data processing systems, CPU (central processing unit) requests for instructions and procedural information stored in a central memory system incur transfer delays causing the CPU to enter into idle states awaiting either new instructions or procedural information required during the execution of an instruction. More particularly, a logic control system typically is initialized by the CPU to request a bus cycle from a communication bus to which the central memory system is attached. Upon acquiring the bus cycle, the logic control system requests and receives instructions and procedural information such as constants, displacements and addresses from the memory system. Upon the CPU receiving such information from the logic control system, the CPU executes the instructions with reference to the procedural information. The CPU execution speed thus is dependent not only upon internal execution speeds but also upon the information transfer rate between the central memory system and the CPU.
The transfer delays have been partially ameliorated by logic systems accommodating block transfers from the central memory system to directly accessible memory systems such as a cache memory system. Please refer to U.S. application Ser. No. 221,854 entitled, "Odd/Even Bank Structure For A Cache Memory", and now U.S. Pat. No. 4,424,561 which is assigned to the assignee of the present invention, and which particularly describes the structure and operation of a cache memory system. The CPU execution speeds, however, still have been limited to an undesirable extent by the transfer delays between the cache memory system and the CPU.
In the present invention, a logic control system including both a cache memory system and a transfer control logic unit is provided which accommodates the transfer of not only procedural information but also CPU instructions from a central memory system to a CPU. The rate of transfer is sufficiently high to avoid any compromise to either central memory system bandwidths or CPU execution speeds because of information transfer delays.
Summary of the Invention
The invention is directed to a logic control system comprised of a cache memory system and a transfer control logic unit for providing procedural and instruction words stored in a central memory system to a central processing unit (CPU) at rates compatible with the central memory system bandwidth and the execution speeds of the CPU.
More particularly, the cache memory system communicates with the central memory system by way of a system communication bus supporting other system devices, while the CPU, the cache memory system and the transfer control logic unit communicate by way of a local communication bus. The CPU thereby is isolated from transfer delays incurred in communicating with the central memory system by way of the system bus. Rather, CPU requests for information from central memory are forwarded by the transfer control logic unit by way of the cache memory system to the central memory system. If the requested information is stored in the cache memory system, the cache memory system honors the request without forwarding the request to the central memory system. If the requested information is not stored in the cache memory system, however, the request is forwarded by the cache memory system to the system bus, and the information received from the central memory system is both stored in the cache memory system and placed on the local communication bus for use by the transfer control logic unit in providing the information to the CPU.
In one aspect of the invention, the transfer control logic unit upon being initialized by the CPU issues requests for information to be transferred from the central memory system to an intermediate memory unit of the transfer control logic unit, and initiates the loading of information from the intermediate memory into selected ones of plural input registers of the transfer control logic unit upon the incipiency of an accessing of a remaining one of said plural input registers by the CPU. A time lead over the CPU access rate thereby is established in which at least a single word is available in the plural input registers for future use by the CPU at all times.
In another aspect of the invention, both single input register and input register pair selections may be made to accommodate single word and double word transfers to the CPU. Procedural information is separated from instruction words and provided to the CPU along independent information paths.
Description of the Drawings
For a more complete understanding of the present invention, and for further advantages and objects thereof, reference may now be had to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a functional block diagram of a transfer control logic unit comprising the invention;
FIG. 2 is a detailed logic diagram of the transfer control logic unit of FIG. 1; and
FIG. 3 is a functional block diagram of a data processing system embodying the invention.
Description of the Preferred Embodiments
Fig. 1
FIG. 1 illustrates in functional block diagram form a transfer control logic unit comprising part of the logic control system of the present invention. The transfer control logic unit is comprised of a thirty-two bit CPU (central processing unit) register 10, sixteen bit registers having reference numbers 11-14, respectively, multiplexers 15 and 16, multiplexers 19 and 20, an F-register logic unit 21 and an eight bit register referred to as an AS register 22.
The CPU register 10 receives instruction words and procedural information by way of a cache memory system comprising part of the present invention and a local communication bus 23. It is to be understood that the cache memory system is refreshed from a central memory system in electrical communication with the cache memory system by way of a system communication bus, which is not part of this invention and thus neither illustrated nor described. The cache memory system may be of the type disclosed in U.S. application Ser. No. 221,854 entitled "Odd/Even Bank Structure For A Cache Memory", and now U.S. Pat. No. 4,424,561 which is assigned to the assignee of the present invention.
The output of the register 10 is applied to the inputs of registers 11-14. The output of register 11 is applied to one input of multiplexer 15, and the output of register 12 is applied to a second input of multiplexer 15. The output of register 13 is applied to a first input of multiplexer 16, and the output of register 14 is applied to a second input of multiplexer 16. The outputs of multiplexers 15 and 16 are applied by way of a multiplexer 19 to a control bus 24 to supply procedural information such as constants, displacements, and addresses to the CPU. The outputs of multiplexers 15 and 16 further are applied by way of the multiplexer 20 to the F-register logic unit 21, which decodes computer instructions for use by the CPU. The logic unit 21 in turn supplies sixteen bits of information by way of a control bus 25 to the CPU. Such information is used by the CPU to control the selection of firmware algorithms, operand registers, index registers and base registers required in the execution of an instruction. The output of logic unit 21 further supplies to the CPU procedural constants and other control information derived from an instruction word. A single bit, bit 8 of the output of logic unit 21, is supplied to the register 22. The register 22 further receives seven bits of information from the CPU by way of a control bus 26. The eight bit output of the register 22 is applied to a second input of the F-register logic unit 21.
It is to be understood that the logic unit 21 may be any instruction decoder compatible with the CPU being used, and is not part of the present invention.
In operation, the CPU requests information from the central memory system by initializing the transfer control logic unit as shall be more particularly described. The transfer control logic unit forwards the request by way of the local communication bus 23 through the cache memory system to the central memory system. If the information requested is stored in the cache memory, the information is supplied from cache memory without forwarding the request to central memory. If the information is not in cache memory, however, the request is forwarded to the system bus for use by central memory. Information received from central memory is both stored in the cache memory system and placed on the local communication bus 23. Such information includes both instruction words and procedural information which is loaded into the register 10 under CPU control. The output of the register 10 is applied to the registers 11-14 and loaded into either registers 11 and 13 or registers 12 and 14 as shall be more particularly described. If, by way of example, the information is loaded into registers 11 and 13, the registers collectively shall contain a full 32 bit double word.
The multiplexers 19 and 20 independently may be caused to select between the outputs of multiplexers 15 and 16. The output of the multiplexer 15 may reflect the output of either the register 11 or the register 12, and the output of the multiplexer 16 may reflect the output of either the register 13 or the register 14. The outputs of the registers 11-14 in turn are enabled in the sequence 11, 13, 12, 14, 11, 13, . . . , beginning with register 11. As the register 11 is being read, the registers 12 and 14 may be loaded with a next occurring double word. As the contents of register 12 are being read, the registers 11 and 13 may be loaded with a third or next occurring double word. The logic system of FIG. 1, therefore, provides a means for looking ahead on a statistical average of approximately one and one-half words in supplying both CPU instructions and procedural information to the CPU at a rate compatible with both the central memory system bandwidth and the CPU execution speeds.
When the CPU requires the addressing of internal registers by CPU computed addresses rather than by the procedural addresses received from the registers 11-14, the CPU issues instruction field variations to the register 22 by way of the control bus 26. The right-most 8 bits of the information received by the F-register logic unit 21 from the registers 11-14 thereby may be replaced with the CPU field variations stored in the register 22.
Fig. 2
FIG. 2 discloses in detailed logic diagram form the transfer control logic unit of FIG. 1.
Referring to FIG. 2, the CPU register 10 receives a clock signal by way of a control line 50 and an output enable signal by way of a control line 51. Each of the lines lead from an output of a firmware control system. The CPU register 10 also receives thirty-two bits from either the central memory system or the cache memory system which are supplied by the cache memory system to the local communication bus 23. Output bits 0-15 of the register 10 are applied to the data inputs of registers 11 and 12. Output bits 16-31 of the register 10 are applied to the data inputs of registers 13 and 14.
The clock input to register 11 is connected to the clock input of register 13 and to the output of an AND gate 52. The output-enable input to register 11 is connected to the output of an inverter 53, the input to which is connected to the output-enable input of register 12. The input to inverter 53 further is connected by way of a control line 54 to one input of gate 52 and to the Q output of a J/K flip-flop 55. The output of register 11 is connected to a tristate bus 56 leading to the output of register 12 and to first inputs of multiplexers 19 and 20.
The clock input of register 12 is connected to the clock input of register 14 and to the output of an AND gate 57. The output-enable input to register 13 is connected to the output of an inverter 58, the input of which is connected to the output-enable input of register 14 and to the Q output of a J/K flip-flop 59. The output of register 13 is connected to a tristate bus 60, which in turn is connected to the output of register 14 and to second inputs of multiplexers 19 and 20.
It is to be understood that in comparing FIGS. 1 and 2 the functionality of multiplexers 15 and 16 in FIG. 1 is provided by the tristate buses 56 and 60 and the logic output-enable control of registers 11-14 in FIG. 2.
The select input to multiplexer 19 is connected to a control line 61, and the enable input of the multiplexer is connected to a control line 62 leading to an output of the firmware control system. The output of multiplexer 19 supplies bits 0-31 of the control bus 24 to the source bus of the CPU.
The select input to multiplexer 20 is connected to the Q output of a J/K flip-flop 63 and to a first input of the second stage of a four-stage multiplexer 64. The enable input to the multiplexer 20 is connected to a control line 65 leading from an output of the firmware control system, and also is connected to the output-enable input of an eight bit register 66. Output bits 0-7 of the multiplexer 20 are applied by way of a tristate bus 100 to the data input of register 66, and output bits 8-15 of the multiplexer are applied to a tristate bus 67 connected to the output of register 22 and to the data inputs of two four-bit counters 68 and 69.
The clock input to the register 66 is connected to the clock input of a D-type flip-flop 70 and to a control line 71 leading to an output of the firmware control system. The output of the register 66 is applied to an eight bit tristate control bus 72 leading to the CPU, and to an eight bit bidirectional tristate feed-back bus 101 connected to the data input of the register 66.
In the preferred embodiment disclosed herein, register 66 is an eight-stage register comprised of two integrated circuit chips, wherein each chip includes a four-stage register with each stage having both a tristate and a standard output. The register may be of the type manufactured and sold by Advanced Micro Devices of Sunnyvale, Calif., and represented to the public as register Model No. 2918.
The set input of the flip-flop 70 is connected to a logic zero source 73, to the reset input of the flip-flop and to the decrement input of the counter 68. The D input to the flip-flop 70 is connected to the bit 8 line of the tristate bus 67. The Q output of the flip-flop 70 is connected to one data input of the register 22 and to a control line 74 leading to the CPU.
The register 22 receives a clock input on a control line 75 leading from an output of the firmware control system. The output-enable input of the register is connected to a control line 76 also leading from an output of the firmware control system. As before stated, the register 22 in addition receives seven bits of information from the CPU by way of a control bus 26. The eight bit output of the register 22 is applied by way of the tristate bus 67 to the data inputs of counters 68 and 69.
The clock input to the counter 68 is connected to a control line 77 leading from an output of the firmware control system, and the load input to the counter is connected to a control line 78 leading from an output of the firmware control system. A second data input to the counter 68 is provided by way of a control line 79 leading from a further output of the firmware control system. The four bit output of the counter 68 is applied by way of a control bus 80 to the CPU.
The clock input to the counter 69 is supplied on a control line 82 by the firmware control system, and the load and decrement inputs to the counter are supplied on control lines 83 and 84, respectively, by the firmware control system. The four bit output of the counter is applied by way of a control cable 85 to the CPU.
The second input to AND gate 52 is connected to the output of an AND gate 87 and to one input of AND gate 57. The AND gate 87 receives three inputs from the firmware control system on control lines 88-90, respectively. A second input to AND gate 57 is connected to the Q complement output of the flip-flop 55.
The set input to the flip-flop 55 is connected by way of an inverter to a logic one source 91 and to the set inputs of flip-flops 59 and 63. The J and K inputs of the flip-flops 55 are connected to the output of the first stage of the multiplexer 64. The clock input to the flip-flop 55 is connected to the clock inputs of the flip-flops 59 and 63, and to a control line 92 leading to an output of the firmware control system. The reset input to the flip-flop 55 is connected to the reset inputs of the flip-flops 59 and 63, and to a control line 93 leading to an output of the firmware control system. The J and K inputs to the flip-flop 59 are connected to the output of the second stage of the multiplexer 64.
The J and K inputs to the flip-flop 63 are connected to the output of the third stage of multiplexer 64. The Q complement output of the flip-flop 63 is applied to the first input of the first stage of multiplexer 64. The second input to the first stage of the multiplexer is connected to the second input of the second stage, to the first input of the third stage and to the logic one source 91. The second input to the third stage of the multiplexer 64 is connected to ground. The select input to the multiplexer 64 is supplied by the firmware control system by way of a control line 95, and the enable input to the multiplexer is supplied by the firmware control system by way of a control line 96.
The Q output of flip-flop 63 further is connected to one input of an EXCLUSIVE OR gate 97, and the Q complement output of the flip-flop is connected to one input of an EXCLUSIVE OR gate 98. Second inputs of gates 97 and 98 are each connected to a control line 99 leading to an output of the firmware control system.
The output of gate 97 is applied to the J input of a J/K flip-flop 102, and the output of gate 98 is applied to the K input of the flip-flop. The set input of flip-flop 102 is connected to a logic zero source 103, and the clock input of the flip-flop is connected to control line 92. The reset input to flip-flop 102 is connected by way of a control line 104 to control line 93. The Q output of the flip-flop is connected to control line 61 leading to the select input of the multiplexer 19.
The Q output of flip-flop 63 in addition is connected by way of an inverter 105 to one input of an AND gate 106, the second input of which is connected to a control line 107 leading to an output of the firmware control system. The output of AND gate 106 is applied to one input of an OR gate 108, the second input of which is connected to a control line 109 leading to an output of the firmware control system. The output of gate 108 is applied to the D input of a D-type flip-flop 110.
The clock input to the flip-flop 110 is connected by way of a control line 111 to control line 92, and the clear input to the flip-flop is connected to a control line 112 leading to an output of the firmware control system. The Q output of the flip-flop is applied to a control line 113 leading to an input of the cache memory system.
The transfer control logic unit comprising part of the invention disclosed herein, includes registers 10-14; multiplexers 19, 20 and 64; flip-flops 55, 59, 63, 102 and 110; gates 52, 57, 87, 97, 98, 106 and 108; and inverters 53, 58 and 105.
Description of Operation
In the operation of the transfer control logic unit of FIG. 2, the system is initialized by the occurrence of a logic one signal on line 93 under firmware control. More particularly, flip-flops 55, 59, 63 and 102 are reset to cause the Q outputs of the flip-flops to transition to a logic zero level. Registers 11 and 13 thereby are enabled, while registers 12 and 14 are disabled. In addition, the multiplexers 19 and 20 are caused to select the tristate bus 56. The logic control system at this point is readied to begin transferring information into registers 11 and 13.
Procedural information and instruction words are received from the cache memory system and the central memory system by way of the local communication bus 23. Under firmware control, the register 10 is enabled by a logic one signal on line 51 and is loaded during the occurrence of a logic one signal on line 50. Bits 0-15 of the register 10 output are applied to the inputs of registers 11 and 12, and bits 16-31 of the register 10 output are applied to the inputs of registers 13 and 14.
The loading of the registers 11-14 is controlled by AND gates 52 and 57, the enablement of which is under the control of AND gate 87 and flip-flop 55. The flip-flops 55 and 59 collectively control the selection of those of the registers 11-14 from which information shall be read for input to the control bus 24 and the logic unit 21. The flip-flop 63 acts to cause the multiplexer 20 to select between tristate buses 56 and 60. The flip-flop 63, EXCLUSIVE OR gates 97 and 98, and flip-flop 102 act in concert to cause the multiplexer 19 to select between the tristate buses.
More particularly, AND gate 87 receives three control signals from the firmware control system on lines 88-90. The line 88 upon transitioning to a logic one level indicates that either computer instructions or procedural information next shall be loaded into the register 10. The lines 89 and 90 carry aperiodic timing control signals which are caused to transition to a logic one level to effect a transfer of information from register 10 to the registers 11-14.
When the output of gate 87 and the Q output of flip-flop 55 are each at a logic one level, the output of gate 52 transitions to a logic one level to load information from the register 10 into the registers 11 and 13. When the output of gate 87 and the Q complement output of flip-flop 55 are each at a logic one level, the output of AND gate 57 transitions to a logic one level to load information from the register 10 into the registers 12 and 14.
As before stated, the flip-flops 55 and 59 control the order in which information stored in the registers 11-14 is read. During any read cycle, the registers 11-14 may be selected individually or in pairs, but are always read sequentially in accordance with the following register order: 11, 13, 12, 14, 11, 13, . . . . A single sixteen bit word may be stored in any of the registers 11-14, and double words may be stored in the following register pairs: 11 and 13, 13 and 12, 12 and 14, and 14 and 11.
By way of example, the multiplexer 19 may be caused to select a single word from register 11 followed by a double word from registers 14 and 12 for output to the control bus 24. In like manner, a single word may be selected from register 13 followed by a double word from registers 12 and 14. Thus single and double words may be read in any combination as long as the registers selected are read in the indicated order.
The particular selection indicated by the outputs of the flip-flops 55, 59 and 63 is controlled by the multiplexer 64 which is under firmware control. More particularly, the firmware control signals on lines 95 and 96 are used to control the logic states of the J and K inputs of the J/K flip-flops 55, 59 and 63 prior to the occurrence of each clock pulse on line 92. The logic states of the flip-flops thereby may be controlled to indicate those of registers 11-14 which shall be read for input to the control bus 24 and the logic unit 21 during a next occurring read cycle.
The multiplexer 64 is enabled under firmware control only if a computer instruction or procedural information is to be read from registers 11-14. The firmware control system uses the line 95 to distinguish between a single register selection and a register pair selection. If line 95 is at a logic one level, the multiplexer 64 selects the second or lower inputs of each stage of the multiplexer. Upon the next occurrence of a clock pulse on line 92, flip-flops 55 and 59 change logic states while the flip-flop 63 remains in a same logic state to indicate a register pair selection. If line 95 transitions to a logic zero level, the multiplexer 64 selects the first or upper inputs. Upon the next occurrence of a clock pulse on line 92, the flip-flop 63 and either flip-flop 55 or flip-flop 59 change logic states to indicate a single register selection.
If a next sixteen bit digital word is to be read from the register 11, the Q output of flip-flop 55 shall be at a logic zero level to enable register 11. If the digital word is to be forwarded to the logic unit 21, the Q output of flip-flop 63 shall be at a logic zero level to cause the multiplexer 20 to select the tristate bus 56. Since the logic unit 21 is sixteen bits wide, only single sixteen bit word transfers are made to the logic unit.
If the word stored in register 11 is the first word of a double word being read for output on control bus 24, the other register selected is the register 13. The Q output of flip-flop 59 thus is at a logic zero level to enable the output of register 13. Thereafter, the Q output of flip-flop 55 is transitioned to a logic one level to enable the output of register 12.
In summary, if a next word is to be read from register 11, the Q output of the flip-flops 55, 59, and 63 shall be at a logic zero level. If a next word is to be read from register 12, the Q outputs of flip-flops 55 and 59 shall be at a logic one level, and the Q output of flip-flop 63 shall be at a logic zero level. If register 13 is to be selected next, the Q output of flip-flop 59 shall be at a logic zero level, and the Q outputs of flip-flops 55 and 63 shall be at a logic one level. If a next word is to be read from register 14, the Q output of flip-flop 55 shall be at a logic zero level, and the Q output of flip-flops 59 and 63 shall be at a logic one level.
In the preferred embodiment disclosed herein, CPU instructions are provided to the CPU by way of multiplexer 20 and logic unit 21.
As before stated in part, the bit 0-7 outputs of multiplexer 20 are applied to the tristate bus 100 leading to the input of register 66 of the F-register logic unit 21. The bit 8-15 outputs of the multiplexer are applied to the tristate bus 67. The bit 8 output of multiplexer 20 is connected by way of bus 67 to the bit 24 output of AS register 22 and to the D input of flip-flop 70. In like manner, the bit 9-11 outputs of multiplexer 20 are connected to the bit 25-27 outputs of register 22 and to first inputs of counter 68. The most significant bit of the four-bit data input to counter 68 is supplied by the firmware control system on line 79. The bit 12-15 outputs of multiplexer 20 are connected by way of bus 67 to the bit 28-31 outputs of register 22 and to a four-bit data input of counter 69.
When a sixteen-bit instruction word is to be provided to the CPU, register 66 captures bits 0-7 of the instruction, flip-flop 70 captures bit 8 of the instruction, counter 68 captures bits 9-11 of the instruction, and counter 69 captures the least significant bits 12-15.
The logic unit 21 is loaded under firmware control prior to the execution of each instruction. The counters 68 and 69 thereafter are triggered in response to a clock signal appearing on lines 77 and 82, respectively. The clock signal is aperiodic but synchronized to the initialization of each firmware step. In addition, counter 69 may be loaded under firmware control during the execution of an instruction to provide iteration and other sequencing control counts.
The most significant eight bits of an instruction are decoded by the firmware control system during the execution of an instruction. For this purpose, the firmware control system continuously monitors the bus 100. In order to free the registers 11-14 for further instruction and procedural information, the bus 100 is combined with the bidirectional tristate feed-back bus 101 to accommodate repeated decodes of parts of a same instruction word. More particularly, if mid-instruction execution reloads are required, the bus 101 is used to reload register 66 with the same instruction bits while new information is being loaded into the remaining devices comprising the logic unit 21. The bus 101 further is used to overcome timing limitations which occur because of a variance in delays between the time information is presented by the multiplexer 20 to the register 66, the time the register is loaded with such information, and the time the output of the register is enabled to forward the information to the CPU. The bus 101 allows information from multiplexer 20 to be applied to bus 72 at the same time such information is presented to the register 66.
The AS register 22 provides an information path from the W bus 26, the main output data bus of the CPU, to the tristate bus 67. A means for supplying computed variables to the counters 68 and 69 thereby is provided for use as necessary in controlling the execution of specialized algorithms.
When non-instruction procedural information is to be provided to the bus 24, the flip-flops 63 and 102 act in concert with gates 97 and 98 to control the operation of the multiplexer 19. More particularly, if a single word is to be provided to the bus 24, the line 99 is at a logic zero level. When the signal on line 92 triggers the flip-flop 102, the Q output of the flip-flop 102 transitions to the same logic state as the Q output of flip-flop 63.
If a double word is to be read from the registers 11-14 and supplied to the bus 24, the line 99 is at a logic one level. When the signal on line 92 triggers the flip-flop 102, the Q output of the flip-flop transitions to the same logic state as the Q complement output of flip-flop 63.
The above-described operation acts under firmware control to cause the multiplexer 19 to select both buses 56 and 60 during a double word read cycle, or any one of the two buses during a single word read cycle. More specifically, the Q output of the flip-flop 102 is made to track the logic state of the Q output of flip-flop 63 during single word transfers. During double word transfers to bus 24, the Q output of flip-flop 102 is made to track the logic state of the Q complement output of flip-flop 63. A first word thereby is provided to the more significant end of the bus 24 while a second word is transferred to the less significant portion of the bus.
The transfer control logic unit of FIG. 2 accommodates both the execution speeds of the CPU and the memory system bandwidth by synchronizing requests to memory for additional instruction and procedural information with the Q output of flip-flop 63. More particularly, flip-flop 110 and gates 106 and 108 act in concert with flip-flop 63 to request information from the memory system. If a single computer word is to be requested, the firmware control system causes the line 107 to transition to a logic one level. If the Q output of flip-flop 63 is at a logic zero level, gate 106 is enabled to cause the output of gate 108 to transition to a logic one level. Upon the next occurrence of a clock pulse on line 111, the Q output of flip-flop 110 transitions to a logic one level to request additional information from the memory system. When the request is accepted, the firmware control system causes line 112 to transition to a logic one level to reset the flip-flop 110. If the Q output of flip-flop 63 is at a logic one level when line 107 transitions to a logic one level, however, the Q output of flip-flop 110 remains at a logic zero level and no request for additional information is sent to the memory system.
In the event a double computer word is to be requested from the memory system, the firmware control system transitions line 109 to a logic one state to cause the output of gate 108 to transition to a logic one state. Upon the occurrence of a clock pulse on line 111, the Q output of the flip-flop 110 transitions to a logic one level as before described.
The transfer control logic unit as disclosed herein effects a loading of selected ones of registers 11-14 from register 10, and a reloading of register 10 from memory at the beginning of an access of remaining ones of registers 11-14 by the CPU. By way of example, if the CPU accesses register 11, a request for additional information from memory to be loaded into register 10 is issued by flip-flop 110, and registers 12 and 14 are loaded from register 10 at the beginning of the firmware step in which the CPU accesses the register 11. In this manner the logic control system is two words ahead of the CPU if the CPU is reading a single word from register 11, and one word ahead if the CPU is reading a double word from registers 11 and 13.
In the logic control system of FIG. 2, it is to be understood that the flow of information from the local communication bus through the register 10 and into registers 11-14 is synchronized by the firmware control system to the timing of the local communication bus 23. The flow of the information from the registers 11-14 through the multiplexers 19 and 20, onto the bus 24 and into the logic unit 21 is synchronized by the firmware control system to the clock signals appearing on lines 71, 75, 77, 82 and 92. The clock signals on lines 71 and 75 are in phase with the clock signals on line 92. The clock signals on lines 77 and 82, however, are one-hundred-eighty degrees out of phase with the clock signal on line 92. A clock pulse comprising the clock signal of line 92 is issued at the beginning of each firmware step. The occurrence of clock pulses in each of these clock signals, therefore, is aperiodic but synchronized to the initialization of each firmware step. In the event a branch instruction is executed by the firmware control system, the transfer control logic unit of FIG. 2 is again initialized by the occurrence of a logic one signal on line 93 as before stated, and the timing system continues as described above.
Fig. 3
FIG. 3 illustrates in functional block diagram form a data processing system in which the present invention may operate.
Referring to FIG. 3, I/O Controllers 120-121, and memory units 122-123 each communicate with the other units by way of a common system bus 124. The memory units 122-123 comprise a central memory system. A cache memory/memory management unit 125 is in electrical communication with bus 124, and further is in electrical communication by way of local communication bus 23 with a CPU 126 and transfer control logic unit 127. The CPU 126 and the logic unit 127 communicate with the common system bus 124 by way of the cache memory unit 125.
The function of the cache memory unit is to provide buffer storage of the current portion of central memory which is being used by the CPU, and to provide for the translation of central memory addresses. When the transfer control logic unit 127, in response to the CPU, requests information from the central memory system, the request is intercepted and honored by the cache unit 125 if the requested information is stored in the cache unit. Otherwise, the information shall be provided by main memory. In all information transfers from main memory, the information is supplied both to the cache unit 125 and to the local communication bus 23.
The CPU 126 further communicates by way of a dedicated bus 128 with the cache memory unit 125, and by way of a dedicated bus 129 with the logic unit 127. Further, the logic unit 127 communicates by way of a dedicated bus 130 with the cache memory unit 125.
In the computer environment illustrated in FIG. 3, average memory transfer cycle time periods of mini-computers such as, by way of example, Honeywell Level 6 computers, have been reduced on the order of 50 percent by having the logic unit 127 rather than the CPU interface with the system bus 124. The CPU messages thereby are confined to the buses 23, 128 and 129 which have faster bus cycle rates and incur less transfer delay because of shorter lengths and fewer loads. If as an example the average transfer cycle time of a system in which CPU 126 interfaces directly with the system bus 124 is of the order of 1000 nanoseconds, the use of a system such as the logic unit 127 to interface between the CPU and the system bus 124 in accessing the main memory shall effect a reduction in transfer cycle times of the order of 500 nanoseconds. If the logic unit 127 is used in conjunction with cache memory unit 125 as illustrated in FIG. 3, the average transfer cycle times may be further reduced to the order of 200 nanoseconds.
In accordance with the invention disclosed herein, a logic control system including a cache memory system and a transfer control logic unit is provided for accommodating the transfer of binary information including both procedural information and CPU instructions from a central memory system to a CPU without causing central transfer delays of such magnitude as to compromise the memory system bandwidth, the access rates of the cache memory system or the CPU execution speeds.
Having described the invention in connection with certain specific embodiments thereof, it is to be understood that further modifications may now suggest themselves to those skilled in the art, and it is intended to cover such modifications as fall within the scope of the appended claims.
Claims
What is claimed is:
1. A hardware/firmware logic control system in a data processing system including a central memory system and a central processing unit (CPU) with a firmware control system in electrical communication with said logic control system by way of a local communication bus, said logic control system which comprises: (a) cache memory means in electrical communication with said central memory system and having control means responsive to said CPU for requesting and receiving binary information including CPU instruction words and procedure words from said central memory system; (b) first register means responsive to said firmware control system for storing said binary information received from said cache memory means; (c) plural register means in electrical communication with said first register means and having both paired clock inputs for accommodating the receipt of plural single words in each register of said plural register means and double words in selected pairs of registers of said plural register means from said first register means, and independent output-enable inputs for accommodating the accessing of selected registers of said plural register means by said CPU; (d) multiplexer means in electrical communication with said CPU and responsive to said firmware control system and to selection control signals for receiving said binary information from said selected registers of said plural register means, and supplying said procedural words separately to said CPU; and (e) logic selection control means responsive to said firmware control system for issuing information requests to said central memory system by way of said cache memory means, enable signals to said output-enable inputs, said selection control signals to said multiplexer means, and clock signals to said paired clock inputs for loading said selected registers of said plural register means with said binary information from said first register means while accommodating the selectable accessing of remaining registers of said plural register means by said CPU to effect an information transfer rate compatible with the bandwith of said central memory system, the access rate of said cache memory means, and CPU execution speeds.
2. A hardware/firmware logic control system in a data processing system including a central memory system and a central processing unit (CPU) with a firmware control system, said logic control system which comprises: (a) a system communication bus in electrical communication with said central memory system; (b) cache memory means in electrical communication with said central memory system by way of said system communication bus and having control means responsive to said CPU for requesting and receiving binary information from said central memory system; (c) a local communication bus in electrical communication with said cache memory and said CPU; (d) first register means responsive to said firmware control system and in electrical communication with said local communication bus for storing said binary information including both binary CPU instruction words and binary procedural words received from either said central memory system or said cache memory means; (e) plural register means in electrical communication with said first register means and having independent output-enable inputs and paired clock inputs for accommodating the receipt of plural single words in each register of said plural register means and double words in selected pairs of registers of said plural register means from said first register means; (f) multiplexer means responsive to said firmware control system and to selection control signals for receiving from selected registers of said plural register means said binary CPU instruction words and said binary procedural words singularly or in pairs, and supplying said binary procedural words separately to said CPU; and (g) logic selection control means responsive to said firmware control system for issuing information requests to said central memory system by way of said cache memory means, clock signals to said paired clock inputs, output-enable signals to said output-enable inputs of said plural register means, and said selection control signals to said multiplexer means at the beginning of an access of said plural register means by said CPU for loading selected registers of said plural register means with said binary CPU instruction words and said binary procedural words from said first register means while accommodating the accessing of remaining registers of said plural register means by said multiplexer means for transfer to said CPU in such a manner as to accommodate the bandwidth of said central memory unit, the access rate of said cache memory unit and CPU execution speeds.
3. A hardware/firmware logic control system in a data processing system including a central memory system and a central processing unit (CPU) with a firmware control system, said logic control system which comprises: (a) a system communication bus in electrical communication with said central memory system; (b) cache memory means in electrical communication with said central memory system and having control means responsive to said CPU for requesting and receiving binary information from said central memory system; (c) a local communication bus in electrical communication with said cache memory means and said CPU; (d) first register means responsive to said firmware control system for receiving by way of said cache memory means both binary CPU instruction words and binary procedural words stored in said central memory system; (e) plural register means in electrical communication with said first register means and having independent output-enable inputs and paired clock inputs for accommodating the receipt of plural single words in each register of said plural register means and double words in selected pairs of registers of said plural register means from said first register means; (f) multiplexer means responsive to said firmware control system and to selection control signals for receiving from selected registers of said plural register means said binary CPU instruction words and said binary procedural words singularly or in pairs for transfer to said CPU, and supplying said binary procedural words separately to said CPU; and (g) logic selection control means responsive to said firmware control system for issuing information requests to said central memory system, clock signals to said paired clock inputs, output-enable signals to said output-enable inputs of said plural register means, and said selection control signals to said multiplexer means at the beginning of an access of said plural register means by said CPU for loading selected registers of said plural register means with said binary CPU instruction words and said binary procedural words from said first register means while accommodating the accessing of remaining registers of said plural register means by said multiplexer means in such a manner as to accommodate the bandwidth of said central memory unit, the access rate of said cache memory unit and CPU execution speeds.