US 4,459,686 AGrant
Semiconductor Device
Issue Date:1984-07-10
•12 Claims
•8 Drawing Sheets
Abstract
A semiconductor device, such as a bipolar semiconductor memory device, includes an internal circuit and a reference signal generating circuit. The difference in potential between at least one internal signal produced by the internal circuit and a reference signal, which is called a noise margin, is decreased during a test mode, rather than during a usual or normal mode, so that the device artificially obtains a high temperature state at room temperature.
Metadata
Assignee
- Fujitsu Limited
Inventor
- Kazuhiro Toyoda
Application Information
Application Number:US 3102963
Filing Date:1981-10-09
Priority Date:1980-10-09
Art Unit:235
Classifications
IPC:
G11C 1140
Field of Search:
365155;179;190;201;202;205;207;210
Patent Drawings (8 sheets)
Description
Background of the Invention
The present invention relates to a semiconductor device, such as a bipolar semiconductor memory device.
In general, when testing a completed semiconductor device, it is desirable to conduct the test under adverse conditions. For example, a test for a semiconductor device could be carried out at a high temperature. However, when considering the fluctuation characteristics of the internal elements within the semiconductor device, such an adverse condition cannot be easily accomplished. In addition, the process for heating a chip is necessary, and a number of complex test steps are required for realizing an adverse condition, such as that of a high temperature, which causes the cost of testing of the device to be high.
Summary of the Invention
Therefore, it is an object of the present invention to provide a semiconductor device in which a high temperature test can be carried out at room temperature.
According to the present invention, there is provided a semiconductor device including: an internal circuit for generating at least one internal signal and means for generating a reference signal. Also included are means, connected to the internal circuit and to the reference signal generating means, for sensing the difference in potential between the internal signal and the reference signal and means for changing the difference in potential between the internal signal and the reference signal based on a usual or normal mode and a test mode.
According to the present invention, there is also provided a semiconductor device including: a plurality of word lines, a plurality of hold lines and a plurality of pairs of bit lines. Also included are a plurality of word drivers each connected to one of the word lines and a plurality of memory cells, each including two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each such multi-emitter transistor connected to one of the bit lines and the other emitter of each such multi-emitter transistor connected to one of the hold lines. Each memory cell also includes two loads or resistors connected to the multi-emitter transistors and to one of the word lines. The semiconductor device further includes a plurality of pairs of sensing transistors having emitters connected to one of the pairs of bit lines and means, connected to the bases of the sensing transistors, for generating a read reference potential for each base of the sensing transistors. Additionally included is means for changing the difference in potential between the internal signal and the read reference potential in accordance with the usual or normal mode and the test mode.
The present invention will be more clearly understood from the following description contrasted with a conventional device and with reference to the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a block circuit diagram illustrating a conventional bipolar semiconductor memory device;
FIG. 2A is a circuit diagram of a memory cell C.sub.00 of FIG. 1;
FIG. 2B is a timing diagram illustrating signals appearing in the circuit of FIG. 2A;
FIG. 2C is a graph illustrating read reference potential V.sub.R of FIG. 2A;
FIG. 3A is a circuit diagram illustrating a first embodiment of a bipolar semiconductor memory device according to the present invention;
FIG. 3B is a timing diagram illustrating signals appearing in the circuit of FIG. 3A;
FIG. 4A is a circuit diagram illustrating a second embodiment of the bipolar semiconductor memory device according to the present invention;
FIG. 4B is a timing diagram illustrating signals appearing in the circuit of FIG. 4A;
FIG. 5 is a circuit diagram illustrating a third embodiment of the bipolar semiconductor memory device according to the present invention;
FIG. 6A is a circuit diagram illustrating a fourth embodiment of the bipolar semiconductor memory device according to the present invention; and
FIG. 6B is a timing diagram illustrating signals appearing in the circuit of FIG. 6A.
Description of the Preferred Embodiments
In FIG. 1, which illustrates a conventional bipolar semiconductor memory device, the bipolar semiconductor memory device comprises memory cells C.sub.00, . . . , C.sub.0,m-1, . . . , C.sub.n-1,0, . . . , C.sub.n-1,m-1 in n rows by m columns. Each memory cell is connected to one of the word lines W.sub.0, . . . , W.sub.n-1, to one of the hold lines H.sub.0, . . . , H.sub.n-1 and to one of the pairs of bit lines B.sub.0, B.sub.0 ; . . . ; B.sub.m-1, B.sub.m-1. The word lines W.sub.0, . . . , W.sub.n-1 are connected to word drivers T.sub.x0, . . . , T.sub.x,n-1, respectively, while the hold lines H.sub.0, . . . , H.sub.n-1 are connected to constant current sources I.sub.H0, . . . , I.sub.H,n-1, respectively. Further, pairs of sensing transistors T.sub.S0, T.sub.S0 '; . . . ; T.sub.S,m-1, T.sub.S,m-1 ' are connected to the pairs of bit lines B.sub.0 l , B.sub.0 ; . . . ; B.sub.m-1, B.sub.m-1, respectively. The bit lines are connected through bit line drivers BD.sub.0, . . . , BD.sub.m-1, respectively, to data bit lines DB and DB which are also connected to constant current sources I.sub.R0 and I.sub.R1, respectively.
A sense amplifier SA, which is activated by a chip selection circuit CS.sub.1, detects the data stored in the memory cells C.sub.00, . . . , C.sub.n-1,m-1 and generates a data signal D.sub.OUT. In this case, the chip selection circuit CS.sub.1 receives the inverted signal CS of a chip selection signal. On the other hand, a write amplifier WA receives a data input signal D.sub.IN and the inverted signal WE of a write enable signal. During a read mode, when the potential of the signal WE is high, the write amplifier WA generates two output signals having the same read reference potential V.sub.R, regardless of the data input signal D.sub.IN. However, during a write mode when the potential of the signal WE is low, the write amplifier WA generates two output signals having different potentials V.sub.D0 and V.sub.D1 in response to the potential of the data input signal D.sub.IN.
FIG. 2A is a circuit diagram of the memory cell C.sub.00 or internal circuit of FIG. 1. The memory cell C.sub.00 is of a flip-flop type which comprises two multi-emitter transistors T.sub.1 and T.sub.2 with bases and collectors cross-coupled to form a bistable circuit. Each of the transistors T.sub.1 and T.sub.2 has one emitter connected to one emitter of the other, while the other of the emitters is connected to the bit line B.sub.0 or B.sub.0. R.sub.1 and R.sub.2 are resistors, and D.sub.1 and D.sub.2 are diodes (for example, Schottky barrier diodes) for clamping the collector potentials of the transistors T.sub.1 and T.sub.2. Therefore, the transistors T.sub.1 and T.sub.2 do not enter into a saturation state. V.sub.W and V.sub.H are potentials of the word line W.sub.0 and the hold line H.sub.0, respectively, and V.sub.C and V.sub.B are potentials of the collector and the base of the transistor T.sub.1.
Referring to FIG. 2B, the operation of the circuit of FIG. 2A will now be explained. Assume that the transistors T.sub.1 and T.sub.2 are turned on and off, respectively. When the potential V.sub.W is changed from low (non-selected state) to high (selected state), the base potential V.sub.B rises slowly, while the collector potential V.sub.C rises quickly for a short time, as indicated by an arrow X. The reason for this will now be explained.
In the circuit of FIG. 2A, the resistors R.sub.1 and R.sub.2 are large enough to reduce the hold current I.sub.H in the non-selected state; however, in this case, in the selected state, the read current I.sub.R is so small that it takes a long time to charge the bit lines B.sub.0 and B.sub.0. To avoid this, the diodes D.sub.1 and D.sub.2 are arranged parallel to the resistors R.sub.1 and R.sub.2, respectively. Therefore, in the non-selected state, the diodes D.sub.1 and D.sub.2 are in an off-state and accordingly, the difference .DELTA.V.sub.1 between the potentials V.sub.W and V.sub.C is represented by
However, in the selected state, the diode D.sub.1 is turned on so that the difference .DELTA.V.sub.2 between the potentials V.sub.W and V.sub.C is equal to the forward voltage of the diode D.sub.1. This forward voltage is 0.7 to 0.8 V in a state when a sufficient current flows through the diode D.sub.1, while the forward voltage is smaller than 0.7 to 0.8 V in a state when a small current flows through the diode D.sub.1. Since the transistor T.sub.1 is in an on-state, V.sub.B >V.sub.R should be satisfied in order to for the read current I.sub.R to flow through the emitter of the transistor T.sub.1 to the bit line B.sub.0. In this case, when V.sub.B =V.sub.R, the read current I.sub.R equals I.sub.R0 /2, and when V.sub.B >V.sub.R or V.sub.B <V.sub.R, the read current I.sub.R equals I.sub.R0 or zero. Therefore, when V.sub.B <V.sub.R (non-selected), no current I.sub.R flows and accordingly, the collector potential V.sub.C is pulled up by the resistor R.sub.1 and the diode D.sub.1. That is, the collector potential V.sub.C follows the word line potential V.sub.W, as illustrated in FIG. 2B. As the collector potential V.sub.C is increased, the collector of the transistor T.sub.1 and the base of the transistor T.sub.2 are charged. In this case, due to the large resistance of the resistor R.sub.1, the charging current which is a collector current of the transistor T.sub.1 is so large that the diode D.sub.1 is turned on. As a result, the collector potential V.sub.C is rapidly increased, as indicated by the arrow X in FIG. 2B. Accordingly, as the base potential V.sub.B approaches the read reference potential V.sub.R, the read current I.sub.R begins to flow, so that the collector potential V.sub.C is again pulled down to a level which is determined by the diode D.sub.1 in the selected state. Thus, the collector potential V.sub.C rises once and then falls.
On the other hand, the collector of the transistor T.sub.2 and the base of the transistor T.sub.1 are also charged by the current flowing through the resistor R.sub.2 ; however, in this case, since the base potential V.sub.B is high in the non-selected state, the current flowing through the resistor R.sub.2, which is a base current of the transistor T.sub.1, is not large enough to turn on the diode D.sub.2. Therefore, the base potential V.sub.B rises slowly and, in addition, since the transistor T.sub.2 is turned off, the potential V.sub.B rises linearly.
As illustrated in FIG. 2B, the collector potential V.sub.C has a peak characteristic and, accordingly, there is a problem in that the maximum of the collector potential V.sub.C approaches the read reference potential V.sub.R. That is, the collector potential may rise as indicated by a dotted line V.sub.C ', because of the fluctuation characteristics of the diodes D.sub.1 and D.sub.2, and this causes a rise in the temperature of the chip or the like. At the worst, if V.sub.C >V.sub.R, in a current switch formed by the transistors T.sub.2 and T.sub.S0', the transistor T.sub.2 is turned on and, in turn, the transistor T.sub.1 is turned off, which may change the memory content stored in the cell C.sub.00. Therefore, the value (V.sub.R -V.sub.C) is called a noise margin. For example, in FIG. 2B, NM.sub.0 is a noise margin at room temperature, while NM.sub.1 is a noise margin at a high temperature.
As illustrated in FIG. 2C, in order to increase the noise margin, the value V.sub.R is set at an intermediate level between the base potential V.sub.B and the collector potential V.sub.C of memory cell or internal circuit; however, as the temperature rises, the difference between the potentials V.sub.B and V.sub.C becomes smaller, so that the noise margin also becomes smaller.
In a test for a finished semiconductor device, it is desirable to conduct such a test under adverse conditions. For example, such a test could be carried out at a high temperature. In other words, in a state where the noise margin is small, the device should be checked whether there is a cell in which V.sub.C >V.sub.R. However, in order to carry out such a test, a process for heating up a chip and various measuring steps are necessary, so that the cost of testing is high.
In FIG. 2B, note that the potential V.sub.R can be shifted toward the word line potential V.sub.W, in order to increase the noise margin; however, in this case, the difference between the potentials V.sub.R and V.sub.B becomes small, so that it is difficult to obtain read outputs at the bit lines B.sub.0 and B.sub.0. In conclusion, it is desirable that the potential V.sub.R be set at an intermediate level between the potentials V.sub.B and V.sub.C in the selected state, as mentioned above.
In a semiconductor device, such as a bipolar semiconductor memory device, it is necessary to check whether V.sub.C >V.sub.R is satisfied when the state is changed from non-selected to selected under an adverse condition, such as a high temperature condition.
FIG. 3A is a circuit diagram illustrating a first embodiment of a bipolar semiconductor memory device according to the present invention. In FIG. 3A, the elements which are the same as those of FIGS. 1 and 2A are denoted by the same reference characters. However, a circuit CS.sub.2 for decreasing the read reference potential V.sub.R in the test mode is added between the chip selection circuit CS.sub.1 and the write amplifier WA.
In more detail, the chip selection circuit CS.sub.1 comprises resistors R.sub.C1 and R.sub.C2, a transistor T.sub.C1 having a base to which a reference potential V.sub.R1 (.congruent.-1.3 V) is applied, a transistor T.sub.C2 having a base to which the inverted signal CS of a chip selection signal is supplied, and a constant current source I.sub.C1. In this case, the transistors T.sub.C1 and T.sub.C2 form a current switch with respect to the constant current source I.sub.C1. The chip selection circuit CS.sub.1 controls the sense amplifier SA. That is, when the potential of the signal CS is lower than the reference potential V.sub.R1, the transistors T.sub.C1 and T.sub.C2 are turned on and off, respectively, so that the low potential of the collector of the transistor T.sub.C1 activates the sense amplifier SA.
The write amplifier WA comprises transistors T.sub.W1 through T.sub.W6, resistors R.sub.W1 and R.sub.W2, diodes D.sub.11 and D.sub.12, and constant current sources I.sub.W1, I.sub.W2 and I.sub.W3. In this case, the transistors T.sub.W1 and T.sub.W2 form a current switch with respect to the constant current source I.sub.W1, while the transistors T.sub.W3 and T.sub.W4 also form a current switch with respect to the constant current source I.sub.W1. During the read mode, when the potential of the inverted signal WE is higher than a reference potential V.sub.R2, the transistor T.sub.W4 is turned on, so that an equivalent voltage (R.sub.W1 .times.1/2I.sub.W1 =R.sub.W2 .times.1/2I.sub.W1) is generated at each of the resistors R.sub.W1 and R.sub.W2 through the diodes D.sub.11 and D.sub.12. As a result, the base potentials V.sub.D0 and V.sub.D1 of the sensing transistors T.sub.S0 and T.sub.S0 ' are the same as the read reference potential V.sub.R produced by the emitter-follower transistors T.sub.W5 and T.sub.W6. However, during the write mode when the potential of the signal WE is lower than the reference potential V.sub.R2, the transistor T.sub.W3 is turned on and in addition, one of the transistors T.sub.W1 and T.sub.W2 is turned on in response to the data input signal D.sub.IN. For example, if the potential of the signal D.sub.IN is lower than a reference potential V.sub.R1, the transistor T.sub.W1 is turned on, while, if the potential of the signal D.sub. IN is higher than the reference potential V.sub.R1, the transistor T.sub.W2 is turned on. Therefore, the base potentials V.sub.D0 and V.sub.D1 of the transistors T.sub.S0 and T.sub.S0 ' are different from each other. The reference potential V.sub.R2 is, for example, -2.1 V.
The circuit CS.sub.2, for decreasing the read potential V.sub.R in the test mode, comprises two transistors T.sub.C3 and T.sub.C4 and a constant current source I.sub.C2. In this case, the transistors T.sub.C3 and T.sub.C4 form a current switch with respect to the constant current source I.sub.C2. The base of transistor T.sub.C4 is commonly connected to the base of the transistor T.sub.C2 of the chip selection circuit CS.sub.1 and, accordingly, the base of the transistor T.sub.C4 receives the chip selection signal CS. The collector of the transistor T.sub.C3 is commonly connected to the collector of the transistor T.sub.W4 of the write amplifier WA. A reference potential V.sub.R3, which is applied to the base of the transistor T.sub.C3, is much lower than the other reference potentials V.sub.R1 and V.sub.R2. Therefore, if the chip selection signal CS has a usual or normal level, the potential of the signal CS is never lower than the reference potential V.sub.R3, so that the transistor T.sub.C3 is always cut off. That is, during the usual or normal mode, the presence of the circuit CS.sub.2 has no effect. Therefore, a read reference potential V.sub.R having a sufficient noise margin NM.sub.0 with regard to the collector potential V.sub.C, as illustrated in FIG. 3B, is applied to the bases of the transistors T.sub.S0 and T.sub.S0 '.
During the test mode, the potential of the signal CS is much lower than the usual high and low levels (non-selected and selected levels), that the potential of the signal CS is lower than the reference potential V.sub.R3. As a result, the transistor T.sub.C3 is turned on, so that an equivalent current flows through each of the resistors R.sub.W1 and R.sub.W2 and each of the diodes D.sub.11 and D.sub.12. The equivalent currents both flow into the constant current source I.sub.C2. Therefore, if I.sub.C2 >I.sub.W1, the voltage drop in the resistors R.sub.W1 and R.sub.W2 (R.sub.W1 .times.1/2I.sub.C2 =R.sub.W2 .times.1/2I.sub.C2) is larger than the voltage drop in these resistors when the transistor T.sub.W4 is turned on during the read mode. As a result, the read reference potential V.sub.R ', that is, each of the base potentials of the sensing transistors T.sub.S0 and T.sub.S0 ', is lower than the read reference potential V.sub.R during the usual or normal mode, as illustrated in FIG. 3B. However, it should be noted that, even during the test mode, the potential of the signal WE is high, so that the currents I.sub.C2 and I.sub.W1 flow through the resistors R.sub.W1 and R.sub.W2. Therefore, the read reference potential V.sub.R ' during the test mode is lower than the read reference potential V.sub.R during the normal mode, without necessitating the condition I.sub.C2 >I.sub.W1. Therefore, when the read operation is carried out by the read reference potential V.sub.R ', the noise margin with respect to the collector potential V.sub.C of the memory cell or internal circuit is indicated by NM.sub.1 in FIG. 3B. This noise margin NM.sub.1 corresponds to a high temperature state. Therefore, without forcing the chip to be in a high temperature state, the checking or testing of the device at a high temperature state can be carried out at room temperature.
FIG. 4A is a circuit diagram illustrating a second embodiment of the bipolar semiconductor memory device according to the present invention. In FIG. 4A, the elements which are the same as those of FIG. 3A are denoted by the same reference characters. In FIG. 4A, the circuit CS.sub.2 ' for decreasing the read potential V.sub.R in the test mode comprises a resistor R.sub.C3 instead of the transistor T.sub.C4 and the constant current source I.sub.C3 of FIG. 3A. In FIGS. 3A and 3B, the read reference potential V.sub.R ' corresponding to a high temperature state can not be arbitrarily changed, even if the potential of the signal CS is changed. Contrary to this, in FIG. 4A, the read reference potential V.sub.R ' corresponding to a high temperature state can be arbitrarily changed by changing the potential of the signal CS. That is, in FIG. 4B, the read reference potential V.sub.R1 ' and V.sub.R2 ' correspond to a first high temperature state and a second high temperature state, respectively. In this case, the first high temperature is lower than the second high temperature.
In FIG. 4A, the reference potential V.sub.R3 is determined so as to cut off the transistor T.sub.C3 when the potential of the signal CS is at a usual level, which is different from a test level. During the test mode, the potential of the signal CS is lower than a value (V.sub.R3 -V.sub.BE) where V.sub.BE is the potential between the base and the emitter of the transistor T.sub.C3, so that the collector current I.sub.C3 to flows through the transistor T.sub.C3. This current I.sub.C3 is represented by ##EQU1## where V.sub.CS is the potential of the signal CS and V.sub.BE is a base-emitter voltage of the transistor T.sub.C3. Then the current I.sub.C3 is changed by changing the potential V.sub.CS, which also changes the each voltage drop in the resistors R.sub.W1 and R.sub.W2. Thus, the read reference potential V.sub.R can be arbitrarily changed, as illustrated in FIG. 4B. Thus, checking or testing of the device of FIG. 4A at various high temperature states can be carried out at room temperature.
FIG. 5 is a circuit diagram illustrating a third embodiment of the bipolar semiconductor memory device according to the present invention. In FIG. 5, the elements which are the same as those of FIG. 4A are denoted by the same reference characters. In FIG. 5, the base of the transistor T.sub.C4 of the circuit CS.sub.2 " is connected to a programmable element or a diode D.sub.p and to an external terminal TM, but not to the chip selection circuit CS.sub.1. That is, during the test mode, the diode D.sub.p is opened so that the potential of the base of the transistor T.sub.C4 is lower than the reference potential V.sub.R3. As a result, the transistor T.sub.C3 remains conductive. After testing, that is, during the usual or normal mode, the terminals of the diode D.sub.p are closed, so that the transistor T.sub.C4 is turned off. Thus, the operation of the circuit of FIG. 5 is similar to that of the circuit of FIG. 3A.
FIG. 6A is a circuit diagram illustrating a fourth embodiment of the bipolar semiconductor memory device according to the present invention. In FIG. 6A, the elements which are the same as those of FIG. 3A are denoted by the same reference characters. In FIG. 6A, a circuit CS.sub.2 '" for increasing the potential of the word line W.sub.0, which is similar to the circuit CS.sub.2 of FIG. 3A, is provided. The circuit CS.sub.2 '" also comprises two transistors T.sub.C3 and T.sub.C4 and a constant current source I.sub.C2. A reference potential V.sub.R3 is applied to the base of the transistor T.sub.C3, while the chip selection signal CS is supplied to the base of the transistor T.sub.C4. Note that a resistor R.sub.X1 is connected to a resistor R.sub.X2 of the word driver T.sub.X0.
During the normal mode when the potential of the signal CS is higher than the reference potential V.sub.R3, the transistor T.sub.C4 is turned on, so that the base potential of the word driver T.sub.X0 is low as compared with the ground level. Contrary to this, during the test mode when the potential CS is lower than the reference potential V.sub.R3, the transistor T.sub.C4 is cut off, so that the base potential of the word driver T.sub.X0 rises toward the ground level. As a result, as illustrated in FIG. 6A, the word line potential V.sub.W ', the base potential V.sub.B ' and the collector potential V.sub.C ' of the memory cell or internal circuit during the test mode are higher than the word line potential V.sub.W, the base potential V.sub.B and the collector potential V.sub.C during the usual or normal mode, respectively, as illustrated in FIG. 6B. However, the read reference potential V.sub.R is not changed regardless of the normal and test modes, since the read reference potential V.sub.R is determined by the write amplifier WA. Therefore, the noise margin NM.sub.1 during the test mode is smaller than the noise margin NM.sub.0 during the usual mode. Note that this small noise margin NM.sub.1 corresponds to a high temperature state. Thus, the checking or testing of the device of FIG. 6A at a high temperature state can be carried out at room temperature.
It should be noted that the present invention can be applied to a MOS (broadly, MIS) semiconductor device as well as the bipolar semiconductor device.
As explained hereinbefore, the semiconductor device according to the present invention has an advantage in that the checking or testing of the device at a high temperature state can be carried out at room temperature, since the noise margin is decreased by decreasing the read reference potential or by increasing the word line potential. Therefore, the manufacturing cost for the semiconductor device is low.
Claims
I claim:
1. A semiconductor device having normal and test modes, comprising: an internal circuit for generating at least one internal signal; means for generating a reference signal; means, operatively connected to said internal circuit and to said reference signal generating means, for sensing the difference in potential between said internal signal and said reference signal; and means for changing the difference in potential between said internal signal and said reference signal, where the difference in the normal mode is different from that in the test mode.
2. A semiconductor device as set forth in clam 1, wherein said changing means comprises means, operatively connected to said reference signal generating means, for decreasing the potential of said reference signal in the test mode, rather than in the normal mode.
3. A semiconductor device as set forth in claim 1, wherein said changing means comprises means, operatively connected to said internal circuit, for increasing the potential of said internal signal in the test mode, rather than in the normal mode.
4. A semiconductor device having normal and test modes, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode.
5. A semiconductor device as set forth in claim 4, wherein said changing means comprises means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode.
6. A semiconductor device as set forth in claim 4, wherein said changing means comprises means, operatively connected to said word drivers, for increasing the potentials of said word lines in the test mode, rather than in the normal mode.
7. A semiconductor device having normal and test modes and operatively connectable to receive a write enable signal and a data input signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors, said read reference potential generating means comprising a write amplifier, operatively connectable to receive the write enable signal and the data input signal and operatively connected to the bases of said sensing transistors, for receiving the write enable signal and the data input signal, and for generating said read reference potential for the bases of said sensing transistors when the potential of the write enable signal is a potential in a read mode; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode.
8. A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection potential, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; a second transistor having an emitter and a base for receiving the chip selection signal; and a constant current source operatively connected to the emitters of said first and second transistors; and the base potential of said second transistor being lower than the first reference potential when in the test mode.
9. A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; and a first load, operatively connected to the emitter of said first transistor and operatively connectable to receive the chip selection signal; and the emitter potential of said first transistor being lower than the first reference potential when in the test mode.
10. A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and having an external terminal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said reference potential generating means, for decreasing said read reference potential in the test mode, rather than in the normal mode, said read reference potential decreasing means comprising: a first transistor having an emitter, a collector operatively connected to said read reference potential generating means and a base for receiving the first reference potential; a second transistor having a base and an emitter; a constant current source operatively connected to the emitters of said first and second transistors; and a programmable element operatively connected to the base of said second transistor and to the external terminal, said programmable element being opened and closed in the test mode and the normal mode, respectively.
11. A semiconductor device as set forth in claim 10, wherein said programmable element is a diode.
12. A semiconductor device having normal and test modes and operatively connectable to receive a first reference potential and a chip selection signal, comprising: a plurality of word lines; a plurality of hold lines; a plurality of pairs of bit lines; a plurality of word drivers each operatively connected to one of said word lines; a plurality of memory cells for generating an internal signal, each memory cell comprising: two multi-emitter transistors having bases and collectors cross-coupled as a bistable circuit and having one emitter of each multi-emitter transistor operatively connected to one of said bit lines and the other emitter of each multi-emitter transistor operatively connected to one of said hold lines; and two resistors operatively connected to said multi-emitter transistors and to one of said word lines; a plurality of pairs of sensing transistors having emitters operatively connected to one of said pairs of bit lines and having bases; means, operatively connected to the bases of said sensing transistors, for generating a read reference potential for the bases of said sensing transistors; and means for changing the difference in potential between said internal signal and said read reference potential, where the difference in the normal mode is different from that in the test mode, said changing means comprising means, operatively connected to said word drivers, for increasing the potentials of said word lines in the test mode, rather than in the normal mode, said word line potential increasing means comprising: a third resistor operatively connected to said word drivers; a first transistor having an emitter and a base for receiving the first reference potential; a second transistor having an emitter, a collector operatively connected to said third resistor and a base for receiving the chip selection signal; and a constant current source operatively connected to the emitters of said first and second transistors; and the base potential of said second transistor being lower than the first reference potential in the test mode.