Dual-Gate MESFET Variable Gain Constant Output Power Amplifier

This invention relates to a constant output power amplifier, and more particularly to a constant output power amplifier employing field effect transistors (FET's).

A large number of system applications require an input amplifier with the capacity to handle a large dynamic signal range with variable gain and constant output power with extremely fast response. The conventional limiter is not capable of preserving amplitude modulation and phase coherence on a wide dynamic signal strength range.

Accordingly, it is an object of the present invention to generate an output signal of constant output power level in response to an input signal of varying power level.

Another object is to generate such signals over a large dynamic signal range with extremely fast response.

A further object is to generate such signals while preserving amplitude modulation and phase coherence on a wide dynamic signal strength range.

These and other objects of the present invention are achieved by a constant output amplifier comprising a plurality of signal-amplifying stages connected in cascade and having adjustable gains. A lesser plurality of gain control means are provided for preadjusting the gains of all but the first and last stages in response to variations in the power level of an input signal applied to the first stage. The action of the gain control means compensates in advance for the variations and maintains constant the power level of the output signal from the last stage. For high input power levels, the signal-amplifying stages do not run into saturation. Thus, the amplifier can retain the amplitude modulation of the input signal. A level control means is provided for adjusting the gain of the last stage to set the value of the constant power level of the output signal.

Additional advantages and features will become apparent as the subject invention becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of a constant output power amplifier according to one embodiment of the invention.

FIG. 2 is a circuit diagram of a signal amplifying stage-shown in FIG. 1.

FIGS. 3 and 4 graphically show the relationships between gain and the transistor second gate electrode voltage of the amplifying stage shown in FIG. 2.

FIG. 5 is a circuit diagram of a video amplifier shown in FIG. 1.

Referring to FIG. 1, the constant output power amplifier of the present invention includes five signal amplifying stages 11-15 connected in cascade. Three gain control means 19-21 are employed to preadjust the gains of the second through fourth stages 12-14 in response to variations in the power level of an input signal applied to the first stage 11 so as to compensate in advances for such variations and maintain constant the power level of the output signal from the fifth stage 15 in the face of such variations. A level control means 23 is provided to adjust the gain of the fifth stage 15 and set the value of the constant output power level.

Each signal-amplifying stage, typically of the form shown in FIG. 2, includes a metal semiconductor field effect transistor (MESFET) 25 having source S, drain D and first and second gate electrodes G.sub.1 and G.sub.2. The transistor 25 is connected by a signal input circuit and a signal output circuit in a commonsource amplifier configuration. The gain versus second gate electrode characteristic of the transistor 25 is such that the gain of the stage decreases over a range of second gate electrode voltages.

While each of the gain control means 19-21 may take a variety of forms, conveniently it may take the form illustrated in FIG. 1 of a directional coupler 26, such as a 10 dB coupler, whose main output port is connected to the transistor first gate electrode G.sub.1 of the stage whose gain is to be preadjusted, and whose main input port is connected to the transistor drain electrode D of the preceding stage, a detector 27, such as a diode peak rectifier, connected to the auxiliary output port of the directional coupler, a video amplifier 29 connected to the detector, and a coupling network 31 connected between the detector and the transistor second gate electrode G.sub.2 of the stage whose gain is to be preadjusted. The level control means 23 may comprise, for example, a terminal for applying a bias voltage to the transistor second gate electrode G.sub.2 of the fifth stage 15.

In operation, a radiofrequency input signal having a time-varying power level is applied to the first stage 11 of the constant output power amplifier and successively amplified in each of the five signal-amplifying stages 11-15. The three directional couplers 26 tap off portions of the amplifier-input-signal replicas appearing at their main input ports and transmit the remainder of the amplified-input-signal replicas to the first gate electrodes of the second through fourth stages 12-14. The three detectors 27 rectify and filter the tapped-off portions to produce error signals whose amplitudes increase in a predetermined polarity in response to increases in the power levels of the amplified-input-signal replicas. The three video amplifiers 29 amplify the error signals to produce gain correction signals therefrom, and the three coupling networks 31 feed the gain correction signals forward to the transistor second gate electrodes G.sub.2 of the second through fourth stages 12-14. The gain correction signals bias the transistors 25 in the decreasing gain range of second gate electrode voltages and cause the voltages on the transistor second gate electrodes G.sub.2 to vary over the decreasing gain range in response to increases in the power level of the amplified-input-signal replicas. In this manner, increases in the power levels of the amplified-input-signal replicas at the main input ports of the directional couplers 26, which increases are caused by increases in the power level of the radiofrequency input signal applied to the first stage, are compensated in advance by decreases in the gains of the second through fourth stages 12-14, and vice-versa. An appropriate bias voltage applied to the transistor second gate electrode G.sub.2 of the fifth stage 15 via terminal 23 adjusts the gain of the fifth stage to set the final (constant) power level of the radiofrequency output signal.

FIG. 2 shows an embodiment of a signal-amplifying stage, e.g., 12, which has provided satisfactory operation. The signal input and signal output circuits include matching transformers 33 for matching the transistor 25 to 50 ohm-line impedance so that the stages 11-15 can be directly cascaded with each other without the use of isolators.

FIGS. 3 and 4 are plots of gain versus second gate electrode voltage VG.sub.2 for the stage. The stage has a dynamic range of 10 dB to -30 dB gain for a change in the second gate electrode voltage from 1 V. to -3.5 V. over an octave band. For high input power levels, the stage does not run into saturation.

FIG. 5 shows an embodiment of the video amplifier 29 which has provided satisfactory operation. The video amplifier has a gain of 40 dB and a bandwidth greater than 350 MHz. to provide enough control voltage to the second gate electrode G.sub.2 of the transistor 25 for dynamically controlling the gain with a response time of 1 ns. The video amplifier is implemented in three stages with Motorola rf hybrid amplifiers MWA 110, MWA 120 and MWA 130 in cascade. The characteristics of each rf hybrid amplifier are given in Table 1.

The characteristics of the three-stage video amplifier are:

Bandwidth: 0.25 to 400 MHz

Gain: 40 dB

Voltage Output (max): 2.5 V

An embodiment of the constant output power amplifier has been implemented with the circuits of FIGS. 2 and 5 and tested over the 4-8 GHz. band. The variation of the output power level is within .+-.2 dB (3.+-.2 dBm) in the 4.5-7.5 GHz range for an input power range of -45 to 0 dBm. The response time of the constant output power amplifier is better than 15 ns. The constant output power amplifier detected simultaneously two pulses of different amplitude separated by 15 nsec. The constant output power amplifier retained a 3 MHz sinusoidal amplitude modulation.

Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.