Electronic Watthour Meter

This invention relates to electronic watthour meters, and more particularly to an electronic watthour meter in which its light load characteristic is improved and its characteristic with time is stabilized.

Since an electronic watthour meter has no mechanically movable components, its characteristic with time is more excellent than an induction type watthour meter which is essentially formed with mechanical components. Furthermore, its circuit is composed by integrated circuits, so that its size is small, it is suitable for mass production and the manufacturing cost can be reduced.

Accordingly, it seems that an electronic watthour meter will eventually replace the induction type watthour meter and will be the main type of watthour meter. A variety of electronic watthour meters have been proposed in the art.

These conventional electronic watthour meters have an equivalent circuit as shown in FIG. 1. Thus, the watthour meter comprises: a multiplication circuit 10 in which a voltage signal e.sub.v, proportional to the load voltage of the power supply lines, and a voltage signal e.sub.i, proportional to the consumption current of the power supply lines, are subjected to multiplication thereby to provide a voltage signal .sup.e o (.sup.e o=k.multidot.e.sub.v .multidot.e.sub.i, where k is a constant) proportional to the instantaneous power of the supply lines; and a voltage-to-frequency converter 11 in which the output voltage signal .sup.e o, of the multiplication circuit 10, is subjected to integration to provide a frequency signal f.sub.out. Accordingly, the integrated power value of the supply lines can be obtained by counting the frequency signal f.sub.out outputted by the voltage-to-frequency converter 11.

The accuracy of the watthour meter is expressed by the absolute error with respect to a true measurement value instead of relative error with respect to the full scale (rating). In the watthour meter, the multiplication circuit 10 and the voltage-to-frequency converter 11 are made up of operational amplifiers. To obtain the high accuracy required by a watthour meter, an offset voltage of the multiplication circuit and the voltage-to-frequency converter must be suppressed within an extremely small value of voltage when the input of the watthour meter is small and its load is light. It is necessary that the offset voltage should be suppressed within the absolute error even if the input of the watthour meter is 1/30 (3.33%) of the rating (100%), 1/50 (2%) or 1/100 (1%). If it is assumed that the rating of the voltage signal Vi, proportional to the consumption current, is 5 V for instance, then the error of 0.5% corresponds to an input 25 mV in conversion value, with the rating being 100%. Therefore, if the input in conversion value is on the order of 25 mV, the accuracy will not be so seriously affected. However, the input in conversion value is 0.5 mV in the case of 0.5% error with respect to a 1/50 input. Accordingly, it is necessary that the offset voltage induced by the operational amplifiers in the multiplication circuit 10 and the voltage-to-frequency converter 11 will be reduced less than 0.5 mV. However, it is quite difficult to suppress the offset voltage within an extremely small value range or to eliminate it. In addition, the offset voltage is varied with time and temperature, so that the accuracy of measurement of power tends to be low.

It is one object of this invention to provide an electronic watthour meter which can measure consumption power accurately. According to this invention, an electronic watthour meter comprises: first means for detecting a voltage signal which is proportional to a load voltage of power supply lines; second means for detecting a voltage signal which is proportional to a load current of the power supply lines; a pulse width modulation circuit for subjecting the voltage signal from the first means to pulse width modulation to obtain a pulse width duty cycle signal; a multiplication circuit for outputting a pulse signal of the product of the voltage signal from the first means and the voltage signal from the second means with switching operation by the pulse width duty cycle signal; a filter circuit for integrating the pulse signal from the multiplication circuit to positive and negative DC voltages; a current-to-frequency converter for outputting a pulse signal of which the frequency is proportional to the DC voltages; and an automatic offset compensation circuit for applying a feedback signal, which is an integration voltage of an output signal of the voltage-to-frequency converter, to the voltage-to-frequency converter.

FIG. 1 is a block diagram showing the fundamental arrangement of an electronic watthour meter;

FIG. 2 is a circuit diagram showing an example of an electronic watthour meter according to the invention;

FIG. 3 is a waveform diagram for a description of the operation of the pulse width modulation circuit shown in FIG. 2;

FIG. 4 is a waveform diagram for a description of the operation of the pulse width modulation circuit and a mutiplication circuit shown in FIG. 2;

FIG. 5 is an input-output characteristic graph of the voltage signals .sup.e op and .sup.e on;

FIG. 6 shows waveforms at various parts of the voltage-to-frequency converter shown in FIG. 2; and

FIG. 7 is a circuit diagram showing a second example of an electronic watthour meter according to the invention.

FIG. 2 is a circuit diagram showing one example of an electronic watthour meter according to this invention.

As shown in FIG. 2, a voltage signal .sup.e v, proportional to a load voltage across power supply lines 12, is detected by a potential transformer 13.

A pulse width modulation circuit (which is referred to hereinafter as "PWM circuit") 14 will be described hereinafter. One terminal of a resistor 15 is connected to one output of the potential transformer 13, and the other terminal is connected to the negative input of an operational amplifier 16. The positive input of the operational amplifier 16 is grounded. A capacitor 17 is interposed between the negative input of the operational amplifier 16 and the output of the same. The positive input of an operational amplifier 18 is connected to the output of the operational amplifier 16. A resistor 19 is interposed between the negative input of the operational amplifier 16 and the output of the operational amplifier 18. The input of an inverter circuit 20 is connected to the output of the operational amplifier 18. A resistor 21 is interposed between the output of the inverter circuit 20 and the negative input of the operational amplifier 18. A resistor 22 is interposed between the negative input of the operational amplifier 18 and the positive input of the operational amplifier 16. The input of an inverter 23 is connected to the output of the operational amplifier 18.

The PWM circuit 14, therefore, includes the resistors 15, 19, 21 and 22, the amplifiers 16 and 18, the capacitor 17, and the inverters 20 and 23.

The output of the PWM circuit 14 is a pulse width duty cycle signal D, and the inverted signal D is a pulse width duty cycle signal D. These signals D and D can be expressed as follows: ##EQU1##

Where .sup.e r is the reference voltage which is applied to the negative input of the operational amplifier 18 of the PWM circuit 14, .sup.e v is the output voltage signal of the potential transformer 13, the time width t.sub.a is the interval of the logic signal "1" of the pulse width duty cycle signal D, the time width t.sub.b is the interval of the logic signal "0" of the signal D and the time T is the cycle of the signal D.

However, the equations (1) and (2) are correct when the offset voltage of the operational amplifier 16 is zero in ideal. In a practical circuit, there is an offset voltage of the operational amplifier 16. If the offset voltage of the operational amplifier 16 is .sup.e oso, the pulse width duty cycle signals D and D are determined by the following equations in practice: ##EQU2## The operational amplifier 18 outputs the pulse width duty cycle signal D and the pulse width duty cycle signal D is outputted from the output of the inverter circuit 23. FIG. 3(a) is a waveform diagram of the voltage signal .sup.e v outputted by the potential transformer 13. FIG. 3(b) is a waveform diagram of the pulse width duty cycle signal D. In FIG. 3(b), the time width t.sub.a is the internval of the logic signal "1" and the time width t.sub.b is the interval of the logic signal "0".

A current signal i, proportional to a load current across the power supply lines 12, is detected by a current transformer 24.

A current-to-voltage converter 25 will be described hereinafter. An output of the current transformer 24 is connected to the negative input of an operational amplifier 26, and other output is connected to the positive input of the operational amplifier 26 and is grounded. A resistor 27 is interposed between the negative input of the operational amplifier 26 and the output of the same. The output of the operational amplifier 26 is connected to the negative input of an operational amplifier 29 through a resistor 28. The positive input of the operational amplifier 29 is grounded. A resistor 30 is interposed between the negative input of the operational amplifier 29 and the output of the same. The converter 25 includes the amplifiers 26 and 29 and the resistors 27, 28 and 30.

The current signal i outputted from the current transformer 24 is converted to a voltage signal (-.sup.e i) by the operational amplifier 26. The voltage signal (-.sup.e i) is proportional to an absolute value of the current signal i. The voltage signal (-.sup.e i) is converted to a voltage signal (+.sup.e i), proportional to the current signal i, by the operational amplifier 29 which has the amplification of (-1). The resistance of the resistor 28 is equal to that of the resistor 30 so that the operational amplifier 29 has the amplification of (-1). The current signal i of the current transformer 24 is directly applied to the operational amplifier 26. According to the feedback action of the operational amplifier 26, the output voltage of the current transformer 24 is nearly zero. As a result, a current transformer having a core the permeability .mu. of which is small can be used and the phase difference between the input signal and the output signal of the current transformer is small.

A multiplication circuit 31, comprising 4 analog switches, will be described hereinafter. Two analog switches 31a and 31b are connected to the output of the operational amplifier 29. Two analog switches 31c and 31d are connected to the output of the operational amplifier 26. Each gate of the analog switches 31a and 31d is connected to the operational amplifier 18, and each gate of the analog switches 31b and 31c is connected to the output of the inverter circuit 23. The outputs of the analog switches 31a and 31c are connected to each other, and those of the analog switches 31b and 31d are connected to each other.

The analog switches 31a, 31b, 31c and 31d are made of semiconductor devices such as junction field effect transistors or MOS field effect transistors.

The pulse width duty cycle signal D is applied to the gates of the analog switches 31a and 31d, and a logic signal "1" of the pulse width duty cycle signal D drives the analog switches 31a and 31d. The voltage signals (-.sup.e i) and (+.sup.e i), proportional to the load current of the power supply lines, are applied from the operational amplifiers 26 and 29 to the inputs of the analog switches 31a and 31d. The pulse width duty cycle signal D from the PWM circuit 14 is applied to the gates of the analog switches 31b and 31c. A logic signal "1" of the pulse width duty cycle signal D drives the analog switches 31b and 31c, and the voltage signals (-.sup.e i) and (+.sup.e i) are applied to the inputs of the analog switches 31b and 31c. Accordingly, the analog switches 31b and 31d output an instantaneous voltage signal .sup.e op. That is, the pulse width duty cycle signals D and D of the PWM circuit 14 drive the analog switches 31a, 31b, 31c and 31d. The instantaneous voltage signal .sup.e op or .sup.e on is the product of the voltage signal .sup.e v, proportional to the load voltage of the power supply lines, and the voltage signals (+.sup.e i) and (-.sup.e i), proportional to the load current. The voltage signals .sup.e op and .sup.e on can be expressed as follows:

When a DC offset voltage of the operational amplifier 26 is .sup.e os.sub.1 and that of the operational amplifier 29 is .sup.e os.sub.2, the voltage signals .sup.e op and .sup.e on can be expressed as follows:

If the equations (3) and (4) are substituted into the equations (7) and (8), then ##EQU3##

As is obvious from the equations (9) and (10), the first term is the value of the instantaneous power and the second term is the error which is caused by the DC offset voltage of the operational amplifiers 16, 26 and 29 in the PWM circuit 14 and the current-to-voltage converter 25.

FIG. 4(a) is a waveform diagram of the voltage signal .sup.e v, from the potential transformer 13, which is proportional to the load voltage of the power supply lines. FIGS. 4(b) and (c) are waveform diagrams of the voltage signals (+.sup.e i) and (-.sup.e i), from the current-to-voltage converter 25, which is proportional to the load current of the power supply lines. FIG. 4(d) is a waveform that is a part of the voltage signal .sup.e v for the period S in the part of FIG. 4(a). FIGS. 4(e) and (f) are waveform diagrams of the pulse width duty cycle signals D and D. FIG. 4(g) is a waveform diagram of the instantaneous power signal .sup.e on. In FIG. 4(d), T is the period of the pulse width duty cycle signals D and D.

A low-pass filter circuit 32, including resistors 33a and 33b and capacitors 34a and 34b, will be described hereinafter. A terminal of resistor 33a is connected to the outputs of the analog switches 31a and 31c. The other terminal of the resistor 33a is connected to a terminal of capacitor 34a. A terminal of resistor 33b is connected to the output of the analog switches 31b and 31d. The other terminal of the resistor 33b is connected to a terminal of capacitor 34b. The other terminals of the capacitors 34a and 34b are grounded. The resistance of the resistor 33a is equal to that of the resistor 33b. The capacitance of the capacitor 34a is equal to that of the capacitor 34b.

The instantaneous voltage signals .sup.e op and .sup.e on of the multiplication circuit 31 are integrated by the low-pass filter circuit 32. The low-pass filter circuit 32 outputs DC voltage signals .sup.e op and .sup.e on which include two components of the instantaneous voltage and the inherent offset voltages .sup.e os.sub.0, .sup.e os.sub.1 and .sup.e os.sub.2 of the PWM circuit 14 and the current-to-voltage converter 25. The number of the time division in the PWM circuit 14 is m. By the on and off control of the PWM circuit 14, the instantaneous voltage signals at each time of the time division, 1,2.about.m are .sup.e op.sub.1, .sup.e op.sub.2 .about..sup.e opm and .sup.e on.sub.1, .sup.e on.sub.2 .about..sup.e onm. The DC output voltages of the low-pass filter circuit 32 can be expressed as follows: ##EQU4##

Really, the number m of the time division will be regarded as the infinite. And, the infinite integration of the voltage signal .sup.e v will be regarded as zero. That is,

From the equations (9) (13), the voltage signals .sup.e op and .sup.e on can be expressed as follows: ##EQU5## From the equations (14) and (15), the first terms are equal in absolute value and are positive and negative DC voltage signals. The second terms of these equations are the inherent offset voltages from the operational amplifiers 16, 26 and 29.

FIG. 5 is an input-output characteristic graph of the DC voltage signals .sup.e op and .sup.e op from the equations (14) and (15). In this characteristic graph, the abscissa represents ##EQU6## and the ordinate represents the output voltages .sup.e op and .sup.e on. The constant K is the inherent offset voltage ##EQU7##

A voltage-to-frequency converter 35 will be described hereinafter. An input of an analog switch 36a is connected to the connection terminal of the resistor 33a and the capacitor 34a of the low-pass filter circuit 32. An input of an analog switch 36b is connected to the connection terminal of the resistor 33b and the capacitor 34b of the low-pass filter circuit 32. Outputs of the analog switches 36a and 36b are connected commonly. A terminal of a resistor 37 is connected to the connection terminal of the analog switches 36a and 36b. The other terminal of the resistor 37 is connected to the negative input of an operational amplifier 38. The positive input of the operational amplifier 38 is grounded. A capacitor 39 is interposed between the negative input and the output of the operational amplifier 38. The positive input of an operational amplifier 40 is connected to the output of the operational amplifier 38. A resistor 41 is interposed between the positive input of the operational amplifier 38 and the negative input of the operational amplifier 40. The input of an inverter circuit 42 is connected to the output of the operational amplifier 40. A resistor 43 is interposed between the negative input of the operational amplifier 40 and the output of the inverter circuit 42. The input of an inverter circuit 44 is connected to the output of the operational amplifier 40. The output of the inverter circuit 44 is connected to a gate of the analog switch 36b. The output of the operational amplifier 40 is connected to a gate of the analog switch 36a. A terminal of a resistor 45 is connected to the negative input of the operational amplifier 38. The voltage-to-frequency converter 35 therefore includes analog switches 36a and 36b, resistors 37, 41, 43 and 45, amplifiers 38 and 40, capacitor 39, and inverters 42 and 44.

The resistance of the resistor 37 is much greater than the resistance of the resistors 33a and 33b of the low-pass filter 32. And, the resistance of the resistor 41 is equal to the resistance of the resistor 43.

The on-off operations of the analog switches 36a and 36b connected to the input of the operational amplifier 38 which operates as an integration circuit are controlled by the output voltage signal of the operational amplifier 40 which is operated as a comparator circuit. The on-off operations of the analog switches 36a and 36b are asynchronous with that of the analog switches 31a, 31b, 31c and 31d of the multiplication circuit 31.

FIG. 6(a) is a waveform diagram of the analog switch 36a when it is closed. FIG. 6(b) is a waveform diagram of a voltage signal .sup.e m from the connection of the outputs of the analog switches 36a and 36b. FIG. 6(c) is a waveform diagram of a voltage signal .sup.e a from the operational amplifier 38. FIG. 6(d) is a waveform diagram of the standard voltage .sup.e c applied to the negative input of the operational amplifier 40. In FIG. 6(a), t.sub.c and t.sub.d show the on time of the analog switches 36a and 36b. In FIG. 6(b), .sup.e op.sub.1, .sup.e op.sub.2, . . . and .sup.e on.sub.1, .sup.e on.sub.2, . . . are the DC voltage of the low-pass filter circuit 32 by the on and off control of the analog switches 36a and 36b. In FIGS. 6(c) and (d), (+.sup.e p/2) and (- .sup.e p/2) are the standard voltages applied to the negative input of the operational amplifier 40. In FIG. 6(d), To is the time (t.sub.c +t.sub.d).

By the on and off operations of the analog switches 36a and 36b which are shown in FIG. 6(a), the voltage signal .sup.e m which is shown in FIG. 6(b) is obtained from the output of the analog switches 36a and 36b. The voltage signal shown in FIG. 6(c) is obtained from the operational amplifier 38 as an integration circuit. This triangular signal is applied to the positive input of the operational amplifier 40. The voltage signal .sup.e c is applied to the negative input of the operational amplifier 40, for comparison. As shown in FIG. 6(d), the voltage signal .sup.e c is (-.sup.e p/2) in the interval t.sub.c when the analog switch 36b is on. The voltage signal .sup.e c is (+.sup.e p/2) in the interval t.sub.d when the analog switch 36a is on. Accordingly, as the positive DC voltage .sup.e op is applied to the operational amplifier 38 in the interval t.sub.c, the output voltage of it shows the down characteristics shown in FIG. 6(c). When the integration output voltage .sup.e Q reaches (-.sup.e p/2), the output logic signal .sup.e f is inverted. After that, the analog switch 36b is cut off and the analog switch 36a is on, and the operation at the interval t.sub.d starts. At the interval t.sub.d, the negative DC voltage is applied to the operational amplifier 38 and the output voltage of it shows the up characteristic shown in FIG. 6(c). When the integration output voltage .sup.e Q reaches (+.sup.e p/2), the output logic signal .sup.e f is inverted. Consequently, the analog switch 36a is cut off and the analog switch 36a is on again, and the operation at the interval t.sub.c starts.

Accordingly, the invention period To of the output logic signal .sup.e f of the operational amplifier 40 can be expressed as follows:

where t.sub.c is the on interval of the analog switch 36b and t.sub.d is the on interval of the analog switch 36a. Therefore, the output frequency f.sub.o of the logic signal .sup.e f can be expressed as follows: ##EQU8##

The on intervals of t.sub.c and t.sub.d will be decided hereinafter. While the interval t.sub.c, the output voltage of the operational amplifier 38 is .sup.e Q(t.sub.c), and the output voltage of it is .sup.e Q(t.sub.d) while the interval is t.sub.d. The resistance of the resistor 37 is R.sub.2, and the capacitance of the capacitor 39 is C.sub.2, and the offset voltage of the operational amplifier 38 is .sup.e os.sub.3. The output voltage .sup.e Q(t.sub.c) can be expressed as follows: ##EQU9## Obviously, as shown in FIG. 6(c), the output voltage signal .sup.e Q(tc) decreases from (+.sup.e p/2) to (-.sup.e p/2).

From the equations (19) and (20), the interval tc can be expressed as follows: ##EQU10## Similarly, ##EQU11## From the equations (23) and (24), the interval td can be expressed as follows: ##EQU12## If the equations (14) and (15) are substituted into the equations (21) and (25), then ##EQU13## From the equations (26) and (27), if the component of the inherent offset voltage is .sup.e os.sub.T, then ##EQU14## From the equations (26), (27) and (28), the intervals tc and td can be expressed as follows: ##EQU15##

The frequency f.sub.o of the logic signal e.sub.f from the voltage-to-frequency converter 35 is 1/(tc+td). If the offset voltage .sup.e os.sub.T is zero, the frequency f.sub.o can be expressed as follows: ##EQU16## As is obvious from the equation (31), since .sup.e r, .sup.e p, R.sub.2 and C.sub.2 are all constant, the output frequency f.sub.o is correctly proportional to the DC voltage .sup.e i.multidot..sup.e v, that is the consumption power.

From the equations (29) and (30),

(A) If the offset voltage .sup.e os.sub.T is zero, .sup.t c is equal to .sup.t d.

(B) If the offset voltage .sup.e os.sub.T is positive, .sup.t c is smaller than td.

(C) If the offset voltage .sup.e os.sub.T is negative, tc is greater than td.

If the offset voltage is not zero, the frequency .sup.f o can be expressed as follows: ##EQU17## Under the condition ##EQU18## the frequency .sup.f o scarcely includes the error. When ##EQU19## is small, at the time of light load, the offset voltage .sup.e os.sub.T causes the frequency error.

An automatic offset compensation circuit 46 including an amplifier, a resistor and a capacitor, will be described hereinafter. A terminal of a resistor 47 is connected to the output of the inverter circuit 42 of the voltage-to-frequency converter 35. The other terminal of the resistor 47 is connected to the negative input of an operational amplifier 48. The positive input of the operational amplifier 48 is grounded. A capacitor 49 is interposed between the negative input and the output of the operational amplifier 48. The output of the operational amplifier 48 is connected to the negative input of the operational amplifier 38 through the resistor 45 of the voltage-to-frequency converter 35.

The operational amplifier 48 operates as an integration circuit. Its time constant is much greater than that of the operational amplifier 38, operating as an integration circuit, of the voltage-to-frequency converter 35. Accordingly, the operational amplifier 38 compensates to make the offset voltage of the voltage-to-frequency converter 35 zero.

From the items (A), (B) and (C) (which are aforementioned), the operation of the compensation is made by the feedback loop on the voltage-to-frequency converter 35. The logic signal .sup.e f is inverted to the voltage signal .sup.e q of the inverter circuit 42 of the voltage-to-frequency converter 35. The voltage signal .sup.e q has a positive or negative amplitude. The resistance of the resistor 47 is R4. The capacitance of the capacitor 49 is C3. The on time of the analog switch 36b is tc. The on time of the analog switch 36a is td. The output voltage .sup.e nf of the operational amplifier 48 can be expressed as follows: ##EQU20## If the condition is R.sub.4 .multidot.C.sub.3 >>tc, td, the equation (33) will become as follows:

If the equations (29) and (30) are substituted into the equation (34), then ##EQU21## From the equation (35), (D) If the offset voltage .sup.e os.sub.T is equal to zero, the voltage signal .sup.e nf is zero.

(E) If the offset voltage .sup.e os.sub.T is positive, the voltage signal .sup.e nf is negative.

(F) If the offset voltage .sup.e os.sub.T is negative, the voltage signal .sup.e nf is positive.

The feedback voltage .sup.e nf is applied to the negative input of the operational amplifier 38. Though the offset voltage .sup.e os.sub.T is high, the voltage .sup.e nf automatically cancels the offset voltage .sup.e os.sub.T. Accordingly, the interval tc is always equal to the interval td.

A display device 50 indicates the frequency .sup.f o of the logic signal .sup.e f of the voltage-to-frequency converter 35.

The operation of this example will be described hereinafter. As shown in FIG. 4(a), the load voltage of the power supply lines is converted to the voltage signal .sup.e v, proportional to the load voltage, by the potential transformer 13. As shown in FIGS. 4(d), (e) and (f), this voltage signal .sup.e v is converted to the pulse width duty cycle signal D, proportional to the amplitude of the voltage signal .sup.e v, by the PWM circuit 14 and this pulse width duty cycle signal D is inverted to the pulse width duty cycle signal D.

On the other hand, the load current of the power supply lines is converted to the current signal i, proportional to the load current, by the current transformer 24. As shown in FIGS. 4(b) and (c), the current signal i is converted to the voltage signal (+.sup.e i) which is different by 180.degree. from the voltage signal (-.sup.e i) by the current-to-voltage converter 25.

The voltage signal (+.sup.e i) is applied to the analog switches 31a and 31b of the multiplication circuit 31. On the other hand, the voltage signal (-.sup.e i) is applied to the analog switches 31c and 31d. And, the pulse width duty cycle signal D of the PWM circuit 14 is applied to the gates of the analog switches 31a and 31d, and the pulse width duty cycle signal D is applied to the gates of the analog switches 31b and 31c. As shown in FIG. 4(g), the instantaneous voltage signal .sup.e on can be obtained at the connection of the outputs of the analog switches 31a and 31c. And, the instantaneous voltage signal .sup.e op can be obtained at the outputs of the analog switches 31b and 31d of the multiplication circuit 31.

According to the process of this operation, the multiplication of the voltage signal .sup.e v and (.+-..sup.e i) can be done. The instantaneous voltage signals .sup.e on and .sup.e op comprises the component .vertline..+-..sup.e i.multidot..sup.e v.vertline., proportional to the instantaneous power, and the component of the DC offset voltage. The instantaneous voltage signal .sup.e on is applied to the resistor 33a of the low-pass filter circuit 32, and the voltage signal .sup.e op is applied to the resistor 33b of the filter circuit 32. Consequently, the instantaneous voltage signals .sup.e op and .sup.e on are integrated by the filter circuit 32, and the variation components of the offset voltage are eliminated. The integration voltage of the voltage signals .sup.e op and .sup.e on comprises the component of the inherent offset voltage. As a result, the DC voltage signal .sup.e on can be obtained at the connection of the resistor 33a and capacitor 34a of the low-pass filter circuit 32, and the DC voltage signal .sup.e op can be obtained at the connection of the resistor 33b and capacitor 34a of the filter circuit 32. These DC voltage signals .sup.e on and .sup.e op comprises the power component ##EQU22## and the inherent offset component.

The DC voltage signal .sup.e on is applied to the analog switch 36a of the voltage-to-frequency converter 35, and the DC voltage signal .sup.e op is applied to the analog switch 36b of the voltage-to-frequency converter 35. The logic signal .sup.e f of the operational amplifier 40 as a comparator circuit controls the gate of the analog switch 36a. On the other hand, the gate of the analog switch 36b is controlled by the inverted logic signal of the inverter circuit 42. These two switches 36a and 36b do not operate at the same time. As a result, the voltage signal .sup.e m shown in FIG. 6(b) can be obtained at the connection of the two analog switches 36a and 36b.

This voltage signal .sup.e m is applied to the negative input of the operational amplifier 38. Consequently, the triangular signal .sup.e Q in FIG. 6(c) can be obtained at the output of the operational amplifier 38.

This voltage signal .sup.e Q is applied to the negative input of the operational amplifier 40 as a comparator circuit. As shown in FIG. 6(d), when the voltage signal .sup.e c reaches the standard voltage signal (+.sup.e p/2) or (-.sup.e p/2), the output signal of the operational amplifier 40 is inverted by the inverter circuit 42 and the output signal of the inverter circuit 42 is applied to the negative input of the operational amplifier 48 as an integration circuit of the automatic offset compensation circuit 46. As a result, the operational amplifier 48 outputs the feedback voltage signal .sup.e nf which eliminates the DC offset voltage .sup.e os.sub.T of the voltage-to-frequency converter 35 and the feedback voltage signal .sup.e nf is applied to the negative input of the operational amplifier 38. The DC offset voltage .sup.e os.sub.T is automatically eliminated. The operational amplifier 40 of the voltage-to-frequency converter 35 outputs the logic signal .sup.e f, which is subject to the frequency ##EQU23## Therefore the error derived from the DC offset voltage .sup.e os.sub.T is eliminated. 1/2.multidot..sup.e r.multidot..sup.e p.multidot.R.sub.2 .multidot.C.sub.2 is constant. If 1/2.multidot..sup.e r.multidot..sup.e p.multidot.R.sub.2 .multidot.C.sub.2 is a constant, the frequency .sup.f o can be expressed as follows:

According to the equation (36), the frequency .sup.f o is correctly proportional to the consumption power .sup.e i.multidot..sup.e v. The display device 50 counts the frequency .sup.f o and indicates the value of the integrated power.

In the example described above, the offset voltage of the PWM circuit 14 and the current-to-voltage converter 25 as obtained through the low-pass filter 32 is the inherent offset voltage which can be eliminated. The automatic offset compensation circuit 46 outputs the feedback signal which eliminates the offset voltage of the voltage-to-frequency converter 35. The feedback signal is applied to the voltage-to-frequency converter 35. The voltage-to-frequency converter 35 can output the frequency signal .sup.f o which is correctly proportional to the consumption power without the influence of the offset voltage. According to this example, when the offset voltage influences highly the accuracy of the measurement and the load is light, the value of the consumption power can be obtained. These circuits are composed by an operational amplifier made of a monolithic IC. This electronic watthour meter can be mass-produced and the size of it can be minimized.

The first example has been described with reference to the single-phase two-line watthour meter. However, with a plurality of voltage detection sections, a plurality of current detection sections and a plurality of multiplication circuits, this invention can be applied to a polyphase watthour meter. In this polyphase watthour meter, the electrical energy is the sum of the powers of the phases. The voltage signals which are proportional to the load voltages of each power line are .sup.e v1, .sup.e v2, . . . , .sup.e vn. The voltage signals which are proportional to the load current of each power line are .sup.e i1, .sup.e i2, . . . , .sup.e in. And, the proportional constants are K.sub.1, K.sub.2, . . . K.sub.n. Accordingly, the power Po will be expressed as follows:

Similar to the first example of the operation of the multiplication circuit, the output signals of each multiplication circuit are added by the low-pass filter. As a result, the power Po satisfying the equation (37) can be obtained.

FIG. 7 is a circuit diagram of the second example of this invention applied to the polyphase watthour meter. In FIG. 7, those components which have previously been described with reference to FIG. 2 have been similarly numbered, and their operations are also similar to those described before. In this second example, a plurality of potential transformers 13, PWM circuits 14, current transformers 24, current-to-voltage converters 25 and multiplication circuits 31 are provided. Through the resistor 33a and the capacitor 33b of the low-pass filter 51, the output signal of each multiplication circuit 31 is applied to the voltage-to-frequency converter 35.

According to this example, the effect similar to the first example can be obtained.

This invention is not limited to the first and second examples described above. In the first and second examples, the voltage signal of the potential transformer 13 is modulated by the PWM circuit. The pulse width duty cycle signals D and D of the PWM circuit 14 control the multiplication circuit. However, the voltage signal .sup.e i of the current-to-voltage converter 25 instead of the voltage signal .sup.e v can be modulated by the PWM circuit. Operation similar to the first and second examples can thus be obtained. As a result, a similar effect can be obtained. Many modifications and variations of this invention are possible within the scope of the appended claim.

This invention described above is applied to an electronic watthour meter. Through the low-pass filter 32, the offset voltage of the PWM circuit 14 and the current-to-voltage converter 25 is obtained as the inherent offset voltage which can be eliminated. The feedback signal of the automatic offset compensation circuit 46 is applied to the voltage-to-frequency converter 35 in order to eliminate the offset voltage of the voltage-to-frequency converter 35 and the inherent offset voltage. Accordingly, the influence of the offset voltage can be eliminated. Though the offset voltage has the great influence at the light load, the power can be measured highly accurately. As these circuits are made of IC, the size of this watthour meter can be minimized and it can be mass-produced.