Process for Dislocation-Free Slot Isolations in Device Fabrication

1. Field of the Invention

This invention relates generally to providing slot isolation of electronic circuitry in semiconductor wafers, and more specifically to a process for forming dislocation-free slots in silicon wafers by reactive ion etching techniques.

2. Discussion of Background and Prior Art

Semiconductor wafers are fabricated with a number of circuit components. It is necessary to provide electronic isolation from one component to another in certain instances. One method for accomplishing this is to provide depressions in the semiconductor wafers which form a positive separation between adjacent circuit elements. Such depressions or slots are normally filled with an appropriate filler material such as amorphous silicon.

Depressions or slots in a semiconductor wafer are conventionally formed by covering the surface of the wafer with a protective layer, generally an oxide layer, covering the oxide layer with a photoresist layer, exposing and developing the photoresist layer to provide a series of troughs in positions corresponding to desired depression or slot location, and then etching through the thus exposed portions of the oxide layer to expose the underlying wafer. Thereafter, anisotropic reactive ion etching techniques are used to cut slots into the wafer of a desired depth. The ions in the plasma are accelerated generally towards the surface of the wafer due to a bias voltage induced on an electrode upon which the wafers sit.

A number of problems exist with prior art plasma etching techniques. One problem which exists is that impurities are introduced into the semiconductor wafer below the bottom of such slots due to the use of relatively high bias voltages which impart high energy to the ions. Such impurities can deleteriously affect the performance of circuitry embedded in the wafers. Another problem which exists is that the bottoms of such slots tend to be very angular in that they tend to come to an apex or to a series of sharp apexes or cusps. When this occurs, later oxidation cycles can lead to the generation of dislocations in the wafer which in turn can lead to device failure. Any solution to the above problems must take into account the fact that it is important in the production of semiconductor wafers that production time is not overly long.

It is object of the present invention to provide a novel method of etching a semiconductor wafer to provide a depression therein of a desired depth.

Another object of the present invention is to produce a depression in a semiconductor wafer having generally parallel walls and being generally free of apexes and cusps at its bottom.

Another object of the present invention is to provide a method of etching a semiconductor wafer which is of comparable speed with prior art methods and which produces wafers having reduced damage introduced by the etching process.

Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practicing the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities, methods and combinations particularly pointed out in the appended claims.

The above and other objects of the present invention are achieved in accordance with the purpose of the present invention, as embodied and broadly described herein, through etching a semiconductor wafer masked with a masking layer having an opening therethrough exposing a portion of the wafer which is to be etched to form a depression of a desired depth. The method comprises first, plasma etching the exposed portion under relatively high bias voltage-relatively high energy plasma etching conditions with a plasma which includes chlorine and a shape modifier species to a first depth which is less than the desired depth, and second, etching the depression under relatively low bias voltage-relatively low energy plasma etching conditions with a plasma which includes chlorine and is substantially free of the shape modifier species, from the first depth to the desired depth.

When operating in accordance with the present invention, slots are made in semiconductor wafers which have generally parallel side walls and generally rounded interiors, particularly at the bottoms of the slots. The amounts of impurities and the damage in the wafer are kept relatively low by use of the lower bias voltage-lower energy plasma for the lower or deeper parts of the slots.

By producing slots in semiconductor wafers which are low in impurities and in damage and which have generally parallel walls and a generally smooth bottom, good isolation of circuitry components within the wafer from nearby circuitry components is accomplished. Furthermore, such is provided without significantly increasing the time needed for etching the slot into the wafer.

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate an embodiment of the present invention and, together with the description, serve to explain the principle of the invention. In the drawings:

FIG. 1 illustrates, in side section view a semiconductor wafer prior to beginning the etching thereof;

FIG. 2 illustrates, in a view similar to FIG. 1, a semiconductor wafer after completion of the first plasma etching step of the present invention;

FIG. 3 illustrates, in a view similar to FIGS. 1 and 2, a semiconductor wafer following the completion of a second plasma etching step in accordance with the present invention.

Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings.

FIG. 1 shows a silicon wafer 10 having a portion 12 of its surface exposed through a masking layer 14. The masking layer 14 is in three parts. A lower part 16 is in contact with a surface 18 of the wafer 10. The lower part 16 is generally in the nature of a silicon dioxide layer which is commonly known as a field oxide layer. The field oxide layer can be conventionally produced by oxidation of the substrate using oxygen and/or steam as the oxidant. Atop the field oxide layer 16 is a middle layer 20 in the nature of silicon nitride. The silicon nitride layer is generally conventionally produced by chemical vapor deposition. Atop the silicon nitride layer is an upper silicon dioxide layer 22 which is generally known as a deposited oxide layer. The deposited oxide layer is generally conventionally produced by chemical vapor deposition.

An opening 23 in the deposited oxide layer 22 exposes the portion 12 of the wafer 10 which is to be anisotropically reactive ion etched. The opening 23 generally has been provided conventionally by providing a photoresist layer (not shown) atop the deposited oxide layer 22, developing the photoresist layer to expose the deposited oxide layer in the area over the portion 12 of the wafer 10 and then etching through the deposited oxide layer 22, the nitride layer 20 and the field oxide layer 16 to expose the portion 12 of the wafer 10. Such etching can be accomplished, for example, utilizing aqueous hydrogen fluoride or other conventional techniques such as plasma etching with a fluorine-containing plasma which form no part of the present invention.

FIG. 2 shows the silicon wafer 10 as it appears after the first step of the present invention. This step comprises reactive ion etching the portion 12 of the wafer 10 under relatively high bias voltage and relatively high energy plasma etching conditions with a plasma which includes chlorine and a shape modifier species. The shape modifier species serves the purpose of keeping side walls 24 of a depression or slot 26 being formed in the wafer 10 generally straight and parallel. Both the chlorine and the shape modifier species are necessary to provide the desired and advantageous shape to the slot 26.

While the plasma etching of this step is going on, the silicon substrate is damaged, due to the impinging ions, and also impurities are introduced in the area 28 of the silicon wafer 10 immediately below a bottom 29 of the slot 26. The damaged area 28 does not constitute a problem for reasons which will shortly become apparent. The first plasma etching step of the present invention thus provides rapid etching, since it is under relatively high bias-relatively high energy conditions, yet maintains the desired shape for the walls 24.

The chlorine may be added as chlorine itself. Alternatively, a chlorine-producing compound such as boron trichloride, silicon tetrachloride, sulfur hexachloride or carbon tetrachloride, alone, in combination with each other, or in combination with chlorine can serve to provide the needed chlorine. In the latter instances, the chlorine-producing compound can also serve as the shape modifier species.

FIG. 3 shows the slot 26 following the second plasma etching step of the present invention. The slot has now been cut to substantially its desired depth. The portion 28 (see FIG. 2) of the silicon wafer 10 which had contained impurities and damage due to the first plasma etching step has now itself been removed. The conditions of the second plasma etching step are significantly milder than those of the first plasma etching step. In particular, the second plasma etching step is carried out with a relatively low bias voltage and corresponding relatively low energy. Furthermore, the plasma, while it still includes chlorine, must now be substantially free of the previously mentioned shape modifier species; i.e., the chlorine must come from molecular chlorine (Cl.sub.2). Under these relatively mild conditions, few or no impurities of significance are provided in an area 30 in the wafer 10, which area 30 is below the area 28 seen in FIG. 2. While the walls 24 of the slot 26 taper inwardly somewhat during the second plasma etching step as seen in the area designated 32, such is relatively minor, and no cusps or apexes are formed in the bottom 29 of the slot 26.

The terms relatively high bias voltage-relatively high energy and relatively low bias voltage-relatively low energy are used to describe reactive ion etching conditions herein. The term relatively high bias voltage-relatively high energy is used to indicate a bias voltage of at least about 180 volts. The term relatively low bias voltage-relatively low energy is used to indicate a bias voltage of no more than about 180 volts. A Tokuda TRIE-303 parallel plate batch reactor has been used in carrying out the plasma etches described herein. In such an apparatus the wafers 10 sit upon an electrode which has a net negative bias relative to an opposed grounded electrode. Similar results have been obtained with another commercially available batch reactor.

It is advantageous to follow the second plasma etching step with a wet chemical etching treatment to remove a thin layer of damaged silicon. In particular, silicon seen in the area designated 32 in FIG. 3 is preferably etched out of the slot 26. Such wet chemical etching is then generally followed by a rinsing step to remove any undesired chemicals from the slot 26.

The shape modifier species utilized in the first plasma etching step of the present invention may be any of a number of chemical species. Argon, for example, has been found to be quite useful. Other useful shape modifier species include hydrogen, nitrogen and non-fluoride-containing boron trihalides, silicon tetrahalides, carbon tetrahalides and sulfur hexahalides, other inert gases than argon, and the like. The shape modifier species serves as a diluent for the plasma and serves to round off corners within the slot 26 and to keep the walls 24 straight. If chlorine is used alone under identical high bias voltage-high energy conditions as are used for the first plasma etching step of the present invention, the result is either a pair of cusps or a single apex at the bottom 29 of the slot 26. When the shape modifier species is utilized, rounded corners result instead of cusps and/or an apex. The particular amounts of the chlorine and the shape modifier species utilized may vary within wide limits. Generally, however, the chlorine will constitute from about 30% to about 90%, by mole, of the plasma, while the shape modifier species will constitute the remainder (10% to 70%) of the plasma.

The wet chemical etching fluid which may be utilized following the second plasma etching step of the present invention may be of any of a number of compositions. Generally, however, the wet chemical etching fluid will comprise an acidic fluoride-containing solution, with or without the presence of iodine. The wet chemical etching step will generally be utilized to remove at least about 250 Angstroms of damaged silicon from the walls 24 and bottom 29 of the slot 26, more preferably up to about 750 Angstroms. The wet chemical etching step also serves to improve the shape of the depression 26 by widening it adjacent the bottom 29 and to remove silicon and undesirable impurities and damaged areas from the sides 24 and bottom 29 of the slot 26. One useful etching solution comprises chromic oxide, hydrogen fluoride and water. Another useful solution comprises iodine, water, nitric acid and hydrogen fluoride. Still another wet chemical etching fluid comprises nitric acid, acetic acid and ammonium fluoride. Table 1, which follows, sets out four particular compositions which have been successfully utilized. The exact chemical constitution of the wet chemical etching fluid is not critical. What is necessary is that the fluid be selected to give a relatively slow etch which leaves no residue. The slot 26 must be thoroughly rinsed and dried to make sure that all traces of the wet chemical fluid have been removed following completion of the wet chemical etching step.

Thus, as illustrated in FIGS. 1-3, the method of the present invention provides slots 26 in silicon wafers 10 of desired shape with minimum impurities and minimum damage in the silicon wafers 10. Further, such is accomplished in a relatively short processing time.

The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variation are possible in light of the above teaching. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.