Power Efficient TTL Buffer for Driving Large Capacitive Loads

The present invention relates, in general, to high speed transistor-transistor logic (TTL) gates for driving output loads. In particular, a TTL gate is provided with a feedback circuit for driving a large capacitive load at high speed while minimizing the average current drain from the gate's power supply.

TTL gates are well-known in the prior art and are widely used commercially. These gates are typically designed to drive loads having a capacitance of approximately 30 pF. or less. When larger capacitive loads are driven, however, the speed of the gate is significantly reduced. This speed loss has been compensated for in the prior art by lowering the values of the resistors used in the gate. This reduction of resistance, however, results in a corresponding and undesirable increase in current drain from the gate power supply. This drain makes the efficient use of the TTL gate prohibitive for driving large capacitive loads.

It is known in the prior art to provide a TTL gate with a feedback circuit for improved gate response. One such circuit is seen in U.S. patent to Gamble et al, U.S. Pat. No. 3,641,368. This patent teaches the use of various feedback techniques for speeding up the turn-on and turn-off times of the gate output transistor. In particular, FIG. 1 of this patent discloses a feedback circuit comprising a transistor Q.sub.4C and a diode CR.sub.3, connected between the output node 20 and the drive transistor Q.sub.4A. When the output begins to fall to the logic low state, the transistor Q.sub.4C provides additional collector current for the drive transistor Q.sub.4A. Therefore, since Q.sub.4A has more available emitter current, the output transistor Q.sub.1A is saturated faster, such that the output node is discharged quicker without a corresponding increase of the collector current I.sub.CC drawn from the power supply V.sub.CC.

It is, therefore, known in the prior art to provide feedback means for a TTL gate to improve gate speed. However, the prior art does not disclose an efficient feedback circuit for a TTL gate which provides high speed response as well as reduction of the supply current I.sub.CC such that the gate is capable of driving large capacitive loads.

It is, therefore, an object of the present invention to provide an integrated TTL inverting gate suitable for use as an output buffer which can drive large capacitive loads with minimal current drain on the gate's power supply.

It is another object of the present invention to provide a TTL gate which can drive a large capacitive load at high speed.

It is a further object of the invention to provide a rapid method of tri-stating a TTL gate with minimal power supply current drain.

It is yet a further object of the invention to provide a TTL gate which is radiation-hardened.

These and other objects are attained in a TTL gate comprising a power supply for supplying collector current to the gate, input means for receiving an input signal, output means responsive to the input signal for providing logic high and low level outputs from the gate at an output node, and drive means connected between the input means and output means for driving the output load with the collector current. In particular, the TTL gate is provided with a feedback means, connected between the output of the drive means and the output means for reducing the collector current when the logic low output level is reached.

The drive means comprises a main drive transistor having a multi-emitter, and a auxiliary drive transistor. The emitter of the auxiliary drive transistor is connected to the first emitter of the main drive transistor to form a first current mirror circuit, which in the preferred embodiment of the invention, is a 3:1 current mirror such that an increase in the drive current available to the output means is provided.

The feedback means includes first and second feedback transistors which have their emitters tied to the output node and their bases tied to the common emitters of the first current mirror. The collector of the first feedback transistor is connected to the second emitter of the main drive transistor while the collector of the second feedback transistor is connected to the output means. The feedback transistors, in the preferred embodiment of the invention, form a second 3:1 current mirror circuit.

In operation, before the output reaches the logic low level, the feedback means and the second emitter of the main drive transistor are inactive. During this period, the drive current is provided to the output means by the first current mirror. As the logic low level is reached, the feedback means turns ON such that the second emitter of the main drive transistor steals some of the current from the first current mirror causing a reduction in the current in the first emitter of the main drive transistor. Since the collector current of the main drive transistor is held constant by the action of a clamp circuit, the current in the emitter of the auxiliary drive transistor tracks the decrease in the current in the first emitter of the main drive transistor. The collector current of auxiliary drive transistor, and thus the power supply collector current, is therefore decreased when the logic low output level is reached.

FIG. 1 is a complete schematic of a TTL gate incorporating the principle of the present invention.

FIG. 2A is a graph of the gate's output during a logic high to logic low to logic high output transition.

FIG. 2B is a graph of power supply collector current I.sub.CC of a prior art TTL gate for the output transitions of FIG. 2A.

FIG. 2C is a graph of power supply collector current I.sub.CC of a TTL gate incorporating the feedback circuit of the present invention for the output transitions of FIG. 2A.

The improved TTL gate 10 of the present invention is seen in FIG. 1. More specifically, the basic gate 10 comprises main input transistor 12, auxiliary input transistor 14, main drive transistor 16, pull-up transistors 18 and 20, and output transistor 22. These transistors are conventional and well-known in the prior art. The improved operation of the gate is provided by auxiliary drive transistor 24 and first and second feedback transistors 26 and 28 as will be described in detail below.

Before describing the circuit of FIG. 1 in detail, the general operation of the circuit can be seen with reference to the signal waveforms shown in FIG. 2. In particular, when the input signal applied to the gate 10 is logic low, the pull-up transistors 18 and 20 are conducting such that the output of the gate is pulled to logic high (V.sub.OH), as indicated at time t.sub.1 in FIG. 2A. The main and auxiliary drive transistors 16 and 24, first and second feedback transistors 26 and 28, and output transistor 22 are cut-off. However, when the input signal applied to the gate 10 starts its low-to-high transition, the gate output begins to fall from logic high to logic low (V.sub.OL) as seen at time t.sub.2 in FIG. 2A, and the drive transistors 16 and 24 begin to conduct. During this transition, the auxiliary input transistor 14 clamps the main drive transistor 16 out of saturation and holds the collector current of this transistor constant. Towards the end of the input low-to-high transition; i.e., at time t.sub.3 in FIG. 2A, the feedback transistors 26 and 28 begin to conduct to cause the collector current I.sub.CC drawn from the power supply V.sub.CC to be reduced, as seen in FIG. 2C. FIG. 2B shows the current I.sub.CC as a function of the V.sub.OL output without the feedback circuit as described in the prior art. It can be seen that the circuit of the present invention provides for reduction in the current I.sub.CC drawn from the power supply when the output of the gate 10 is driven to and maintained at V.sub.OL. This reduction allows the gate to drive higher capacitive loads as compared to prior art TTL gates.

Referring now to the details of the input circuit of FIG. 1, the input signal is applied to the gate 10 via the DATA-IN line of the main input transistor 12. As can be seen in this figure, the main input transistor 12 has a multi-emitter structure comprising first and second emitters 30 and 32. The DATA-IN line is connected to first emitter 30 while the second emitter 32 is connected to the TRI-STATE input of the gate for providing tri-state operation, as is well-known in the prior art. The main input transistor 12 is a Schottky transistor for improved speed response. The second emitter 32 of the main input transistor 12 is connected through Schottky diode 34 to node V.sub.A ; i.e., the collector of the main drive transistor 16 and the base of the pull-up transistor 18. The collector of the main input transistor 12 is connected to the supply voltage V.sub.CC through the resistors 30 and 36, and to the base of the auxiliary input transistor 14. The base of the main input transistor 12 is tied to the bases of main and auxiliary drive transistors 16 and 24, and is also connected to the emitter of the auxiliary input transistor 14. The collector of the auxiliary input transistor 14 is tied to V.sub.CC through resistor 30, while the base thereof is connected to the collector of the main drive transistor 16 through diode 38 and resistor 40. The main and auxiliary input transistors 12 and 14 define an input means of the gate 10 for receiving the input signals.

The power supply V.sub.CC is connected to the collectors of pull-up transistors 18 and 20 through resistor 30. These transistors form a Darlington active pull-up amplifier as is well-known in the prior art. This amplifier also includes resistor 39 connected between the base of pull-up transistor 20 and ground. The amplifier is connected between node V.sub.A and output node V.sub.OUT.

The main and auxiliary drive transistors 16 and 24 have a common base structure as seen in FIG. 1. The collector of the auxiliary drive transistor 24 is connected to V.sub.CC through resistor 30 while the emitter thereof is tied to node V.sub.B. The collector of the main drive transistor 16 is connected to node V.sub.A and tied to V.sub.CC through resistors 30 and 42. The main drive transistor 16 has a multi-emitter structure comprising first and second emitters 44 and 46. The first emitter 44 is tied to the emitter of the auxiliary input transistor 24 at node V.sub.B to form a first current mirror, and to the bases of the first and second feedback transistors 26 and 28. In the preferred embodiment of the invention, the base-emitter area of the auxiliary drive transistor 24 is 3.times. the emitter area of the first emitter 44 of main drive transistor 16. Therefore, these transistors form a 3:1 current mirror wherein the emitter current of auxiliary drive transistor 24 is 3.times. the emitter current in the first emitter 44 of main drive transistor 16. The second emitter 46 of main drive transistor 16 is connected to the collector of first feedback transistor 26. The drive transistors 16 and 24 define a drive means for driving the output transistor with the supply current I.sub.CC.

The output transistor 22 is connected between output node V.sub.OUT and ground. Specifically, the collector of output transistor 22 is tied to the emitter of pull-up transistor 20 and to the emitters of first and second feedback transistors 26 and 28. The base of the output transistor 22 is tied to the collector of the second feedback transistor 28, to ground through resistor 48, and to node V.sub.B through resistor 50. The output transistor 22 and resistors 48 and 50 define an output means responsive to the input signal for providing logic high and low level outputs from the gate 10 at output node V.sub.OUT.

The first and second feedback transistors 26 and 28 have their bases connected to node V.sub.B and their emitters tied to node V.sub.OUT. In the preferred embodiment of the invention, the emitter area of first feedback transistor 26 is 3.times. the emitter area of second feedback transistor 28 such that these transistors form a second 3:1 current mirror. The feedback transistors 26 and 28 define a feedback means connected between the drive means and the output means for reducing the current I.sub.CC drawn from the power supply V.sub.CC when V.sub.OL is reached. In particular, the first leg of the second current mirror; i.e., the collector of first feedback transistor 26, is connected to the second emitter 46 of the main drive transistor 16. Similarly, the second leg of the second current mirror, which is the collector of second feedback transistor 28, is connected to the base of output transistor 22 and node V.sub.B of the first current mirror through resistor 50.

Referring again to FIG. 1, the diodes 52, 54, 56 and 58 shown in phantom are compensation diodes which provide radiation hardness. These diodes may be omitted if desired.

The operation of the gate 10 can best be explained with reference to FIG. 1 and the waveforms seen in FIG. 2. In a TTL gate, the output of the gate goes from logic high to logic low when the input thereto goes from logic low to logic high. Therefore, if the DATA-IN line is at logic low, the voltage at output node V.sub.OUT is logic high as seen at time t.sub.1 in FIG. 2A. With a logic low data input and logic high tri-state input, the emitter 32 of the main input transistor 12 is logic high while emitter 30 is logic low. Under these conditions, the auxiliary input transistor 14 supplies only enough current to drive the base of the main input transistor 12, such that the main and auxiliary drive transistors 16 and 24 are cut-off. Resistor 42 charges the collector node V.sub.A of main drive transistor 16 to keep diode 38 reverse biased. The resistor 42 also supplies base drive to Darlington transistors 18 and 20 such that V.sub.OUT is logic high. The output transistor 22 is cut-off, as are first and second feedback transistors 26 and 28.

Assuming now that the DATA-IN line starts its low-to-high transition, such that the voltage at output node V.sub.OUT begins to go low as seen at time t.sub.2 in FIG. 2A. During the first part of this transition, the first and second feedback transistors 26 and 28 remain cut-off and no current flows in the second emitter 46 of the main drive transistor 16. However, since the tri-state input is logic high, the auxiliary input transistor 14 now becomes a low impedance emitter follower which provides sufficient current to charge the base of main and auxiliary drive transistors 16 and 24, as well as main input transistor 12. As the main drive transistor 16 begins to conduct, its collector voltage drops such that diode 38 becomes forward-biased. When this occurs, diode 38 and resistor 40 shunt base drive away from the auxiliary input transistor 14 such that this transistor cannot supply enough current to saturate the main drive transistor 16. Therefore, it can be seen that diode 38 and resistor 40 serve to clamp the main drive transistor 16 out of saturation and keep the voltage at node V.sub.A constant. This constant collector voltage keeps the collector current of main drive transistor 16 fixed during this part of the gate operation.

In the latter portion of the output high-to-low transition; i.e., at time t.sub.3 in FIG. 2A, the feedback means comprising first and second feedback transistors 26 and 28 becomes active to effect minimization of the average current drain from the power supply V.sub.CC. In particular, as V.sub.OL is reached, the second emitter 46 of the main drive transistor 16 becomes active and first and second feedback transistors 26 and 28 begin to conduct. At this stage of the gate operation, it is useful to define two distinct currents, I.sub.DRIVE and I.sub.CLAMP, which are present in the gate. Specifically, I.sub.DRIVE, which is a portion of I.sub.CC, is defined as the current in the base circuit of output transistor 22. This current is used to turn-on the output transistor 22 to pull the output to V.sub.OL. The other current I.sub.CLAMP, which is defined as the sum of the emitter currents of first and second feedback transistors 26 and 28, is used to ensure that the voltage at output node V.sub.OUT does not fall below V.sub.OL. From a D.C. standpoint, I.sub.CLAMP is a wasted current and should be minimized. This minimization is accomplished by the first and second feedback transistors 26 and 28 in conjunction with the main and auxiliary drive transistors 16 and 24, as will be described below.

The operation of the feedback means when V.sub.OL is reached can best be understood by examining the magnitudes of the currents I.sub.DRIVE and I.sub.CLAMP in the various transistors of the gate 10. Referring back to FIG. 1, since I.sub.CLAMP is defined as the sum of the emitter currents of first and second feedback transistors 26 and 28, and these transistors form a 3:1 current mirror, it can be seen that the collector currents of these transistors are approximately:

The second emitter 46 of main drive transistor 16 provides the 3/4 I.sub.CLAMP for first feedback transistor 26. The first current mirror, comprising the emitter of auxiliary drive transistor 24 and the first emitter 44 of the main drive transistor 16, provide the 1/4 I.sub.CLAMP for second feedback transistor 28 and the current I.sub.DRIVE for the output transistor 22. Since these transistors form a 3:1 current mirror, the emitter of auxiliary drive transistor 24 supplies 3/4 I.sub.DRIVE while the first emitter 44 of the main drive transistor supplies 1/4 I.sub.DRIVE. Also, the emitter of auxiliary drive transistor 24 supplies 3/4th's of the remaining 1/4 I.sub.CLAMP, or 3/16 I.sub.CLAMP, while the first emitter 44 of main drive transistor 16 supplies 1/4th of the remaining 1/4 I.sub.CLAMP, or 1/16 I.sub.CLAMP.

The currents in the collectors of the main and auxiliary drive transistors 16 and 24 are thus approximately:

Note that the 13/16 I.sub.CLAMP current in the collector of main drive transistor 16 is derived from the 3/4 I.sub.CLAMP in emitter 46 and 1/16 I.sub.CLAMP in emitter 44. The base current of the drive transistors 16 and 24 has been neglected since diode 38 and resistor 40 have clamped the main drive transistor 16 such that it operates in the active region. Normalizing the above collector currents to main drive transistor 16 illustrates the mirror ratio that exists for I.sub.DRIVE and I.sub.CLAMP :

The above table illustrates that the first current mirror provides a 4:1 gain in the current I.sub.DRIVE supplied to the base of the output transistor while at the same time I.sub.CLAMP is minimized. Note that the gain is 4.times. I.sub.DRIVE which represents the sum of the 3.times. I.sub.DRIVE provided by drive transistor 24, and the 1.times. I.sub.DRIVE provided by drive transistor 16. Referring back to FIG. 1, the minimization of I.sub.CLAMP serves to reduce the current I.sub.CC drawn from the power supply V.sub.CC. Specifically, before the feedback transistors are activated, I.sub.DRIVE is provided to the output transistor 22 by the first current mirror. As the feedback means turns ON, the second emitter 46 of main drive transistor 16 steals some of the current from the first current mirror causing a reduction in the current in the first emitter 44. Since the collector current of main drive transistor 16 is held constant by the action of diode 38 and resistor 40, the emitter of auxiliary drive transistor 24 tracks the decrease in the current in the first emitter 44 of main drive transistor 16. The collector current of auxiliary drive transistor 24, and thus I.sub.CC, is therefore correspondingly decreased by a factor of 4:1, given the 3:1 current mirror ratio.

It can, therefore, be seen that the feedback transistors 26 and 28 in conjunction with the drive transistors 16 and 24, provide for improved operation of the gate 10. In particular, the feedback transistors 26 and 28 form feedback means for reducing the current I.sub.CC when the output V.sub.OL is reached. Since the I.sub.CC current is reduced only during the time the gate is at a V.sub.OL level no sacrifice in speed results from the overall reduction in average I.sub.CC. Furthermore, the current required to tri-state the gate is reduced by approximately 3:1 over conventional gates of equivalent speed/load.

Although the invention has been described in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the invention being limited only to the terms of the appended claims.