Method and Apparatus for Pulse Train Synchronization in PCM Transceivers

The present invention relates generally to pulse code modulated transceivers, and more particularly, to a method and apparatus for synchronizing a binarily encoded data train with a fixed clock signal.

The T-1 type pulse code multiplex (PCM) transmission system commonly employed in the telephone industry uses a pulse format consisting of frames comprising twenty-four eight-bit segments representing the transmitted information on the twenty-four channels being multiplexed, plus one extra bit interposed between each twenty-four segment group. The extra bits are alternately main frame bits and signaling frame bits. They are arranged in a pattern such that the main frame bits alternate between 0 and 1 in even numbered frames, while the signaling frame bits alternate between 000 and 111 in odd-numbered frames. One of the basic functions of a PCM receiver is to determine which pulses in the pulse train are the main frame bits and to separate, based on that determination, the twenty-four channel segments from one another so that each segment can be fed into the proper channel after being decoded. A main frame time interval is defined as the time interval elapsing between each successive application of a main frame bit to the PCM receiver.

My copending U.S. patent application Ser. No. 950,840, filed Oct. 12, 1978, now issued as U.S. Pat. No. 4,314,368, the disclosure of which is hereby incorporated herein, discloses a framer which responds to a loss of main frame information in the incoming pulse train, or to a lack of proper synchronization between the pulse train and the receiver, by locating the main frame pulses in the pulse train and producing an output representative of the position of the main frame bit in the incoming pulse train.

In the conventional type of PCM receiver, the main frame position detected by the framer produces a reference with which the timing signal generator of the receiver is synchronized following an out-of-frame condition. This conventional framing method has a serious disadvantage in systems in which the remote transmitter is frame and bit synchronized to the remote receiver (i.e. in which the transmit circuitry and receive circuitry at the remote end use the same clock signals to reduce circuit complexity and clock distribution complexity). In such systems, the remote terminal, when equipped with a conventional framer, cannot be looped upon itself through an arbitrary delay for maintenance purposes because whenever the timing signal generator, used for both transmit and receive timing, is synchronized to the incoming frame position, that frame position shifts by an amount related to the loop delay. An out-of-frame condition immediately results.

The present invention overcomes the problems of the prior art by providing an arrangement in which the phase difference between the incoming pulse train and a fixed internal frame clock is detected by the transceiver and is used to automatically delay the incoming pulse train by the amount necessary to bring it into synchronism with the internal frame clock.

In accordance with one aspect of the invention, the device described herein accomplishes the required delay and synchronization by a very simple counting circuit.

FIG. 1 is a schematic block diagram showing a receiver according to the principles of the present invention;

FIG. 2 is a schematic block diagram of a preferred embodiment of a portion of the receiver of FIG. 1; and

FIG. 3 is a timing diagram illustrating the sequence of operations in the receiver of FIG. 1.

FIG. 1 shows a schematic block diagram of a portion of a PCM receiver constructed according to the principles of the present invention. A data train, generally being T-1 type pulse code multiplex (PCM) data converted to unipolar form, is applied to the receiver at input 10. Clock means such as master clock generator 12 are coupled to input 10 for receiving the data train. Clock information is extracted from the data train in the usual manner to develop master clock pulses at the bit rate of the incoming data train, main frame bits in the data train, and signal frame clock pulses at the same repetition rate but positioned midway between the main frame pulses.

A framer 14 is coupled to master clock generator 12 for receiving the incoming pulse train and each of the above described clock pulses or signals. A utilization device such as demultiplexer 18 is also coupled to master clock generator 12 for timing the separation of the data train into various channels. The proper operation of demultiplexer 18 depends on the synchronization of the incoming main frame bits with the main frame clock signal. A delay means 16 is also coupled to input 10 for receiving the incoming data train and delaying the data, as hereinafter described, for an appropriate time interval before applying it to demultiplexer 18 to obtain synchronization with the main frame clock signal. Delay means 16 also applies the data train to framer 14 for developing an out-of-frame (OOF) signal indicative of loss of synchronization between the main frame bit and the main frame clock signal, and a framing (FRAME) signal indicative of a main frame bit being applied to framer 14 after an out-of-frame condition has been recognized. Counter means 20 is coupled to master clock generator 12 and framer 14 for developing an output signal for application to delay means 16, the output signal being indicative of the number of bits by which the delay means 16 will delay the data train being applied at its input I.

When framer 14 develops an OOF signal, counter 20 is reset so that the output signal applied to delay means 16 will cause the data train to be passed through delay means 16 without any delay. A subsequent FRAME signal developed by framer 14 enables counter 20 to begin counting the number of master clock pulses occurring between the frame pulse of the incoming pulse trains located by framer 14, and the next pulse of the transceiver's internal main frame clock signal, thereby defining a delay interval. The output signal of counter 20 is indicative to this delay interval and is applied to delay means 16. Delay means 16 thereupon delays the data train before application to demultiplexer 18 for a time interval equal to the delay interval, thus assuring synchronization of the main frame bit with the main frame clock signal.

The general operation of master clock generator 12, frame 14 and demultiplexer 18 is conventional and has been described in my aforesaid copending U.S. patent application Ser. No. 950,840 now issued as U.S. Pat. No. 4,314,368.

FIG. 3 shows time amplitude representations of the above-described signals and their relationship to the data train. Lines 1 and 2 show the main frame clock (MFC) pulses at the beginning of each main frame and the signalling frame clock (SFC) pulses in the middle of each main frame.

Lines 3 and 4 represent, respectively, the main frame pulses of the PCM data train as applied to delay means 16 as developed at the output thereof. The lettered points in each data train representation indicate the position of an identical bit in each data train. The data applied to delay means 16, as shown by line 3, is not synchronized with the main frame clock signal (see the locations of main frame bits 22 and 24 at locations A and B respectively). However, main frame bits 22 and 24 are synchronized in the delay data representation of line 4.

Loss of synchronization may occur from time to time, as during an interruption of the reception of the data train at location C. When the data train reception has been resumed, main frame bit 26 is no longer synchronized with the main frame clock. When nonsynchronism occurs for two consecutive main frames as shown by main frames 3 and 4, the OOF signal of line 5 as developed by framer 14 goes high. This resets counter 20 so that the delay of delay means 16 is reset to zero. The effect of the output of delay means 16 when reset is best shown by locations D and E of the data trains of lines 3 and 4. The data bits applied to delay means 16 between location D and E are lost during the resetting process as shown by the coincidence of locations D and E on line 4.

The OOF signal of line 5 remains high until framer 14 has located a main frame bit 28 shown herein at location F. As will be hereinafter described, the reset signal for counter 20 shown in line 6 is cancelled by a next occurrence of a pulse 30 in the signal frame clock of line 2 after the OOF signal has gone high. The interval between main frame 5 and 25 is required for frame 14 to locate main frame bit 28 at location F, as described in my above-identified U.S. patent application Ser. No. 950,840 now issued as U.S. Pat. No. 4,314,368. Framer 14, upon locating main frame bit 28, develops pulse 32. This is the FRAME signal shown in line 7. When pulse 32 is applied to counter 20, a delay counter enable (DCE) signal, as shown in line 8, goes high and is terminated upon the next occurrence of the main frame clock signal, shown as pulse 34. The time interval between the DCE signal of line 8 going high and its resetting by pulse 34 defines a delay time interval. During the delay time interval, the raw data of line 3 applied to delay means 16 is loaded therein so as to be developed at the output of delay means 16 after the delay time interval as shown by location F of line 4. Delay means 16 will develop the main frame bit 28 of location F at its output upon the occurrence of pulse 34 of the main clock signal. Location G demonstrates that the data of line 4 has been delayed with respect to the raw data of line 3.

FIG. 2 shows a circuit diagram, partly in block form, of a preferred embodiment of delay means 16 and counter 20 of the present invention. Counter 20 includes a binary counter 36, a first D flip-flop 38 and a second D flip-flop 40, all of conventional design. First flip-flop 38 is clocked by the OOF signal which transfers the logical 1 at the D input to the Q output for resetting binary counter 36 when the OOF signal goes high. The delay counter reset (DRST) signal, shown on line 6 of FIG. 3, is reset by pulse 30 of the signal frame clock applied to the reset (R) input of flip-flop 38. The Q.sub.0 through Q.sub.8 outputs of binary counter 36 are reset to 0 when the DRST signal goes high. Binary counter 36 is enabled when the DCE signal, as hereinabove described, goes high. While DCE is high, counter 36 develops at its Q output a binary representation of the number of master clock (CCK) pulses occurring until the DCE signal is reset by the MFC signal applied to the R input of flip-flop 40. The number of CCK pulses counted is equal to the number of data bits by which the data train applied to delay means 16 must be delayed.

The delay means 16 include a plurality of switches 42, 44 and 46 which operate as follows: a logical 0 applied to input S connects input I.sub.0 to the output 0, and a logical 1 applied to input S connects input I.sub.1 to the output 0. The delay means 16 further include a variable shift register 48, a 64-bit shift regisfter 50, a 128-bit shift register 52, and a 256-bit shift register 54. The binary representation developed at the Q.sub.0 through Q.sub.5 output of binary counter 36 is applied to the L input of shift register 48, the binary representation corresponding with the number of bit positions enabled within shift register 48. The Q.sub.6, Q.sub.7 and Q.sub.8 outputs of binary counter 36 are coupled to the S inputs of switches 42, 44 and 46, respectively.

Variable shift register 48 can have any number of bits between 0 and 63. The binary representation at the Q outputs of binary counter 36 will select the appropriate inputs of switches 42, 44 and 46, and the bits available in variable shift register 48, to develop an overall shift register circuit. This circuit constitutes delay means 16. It has a number of bit positions, varying between 0 and 511 which is equal to the number of master clock pulses binarily represented by counter 36. The count developed by binary counter 36 thus corresponds to the number of bits by which delay means 16 will delay the data train applied thereto.

In the above discussion, it is assumed that the minimum delay through variable shift register 48 is zero, while commercially available variable shift registers generally have a minimum delay of one bit. It will be understood that such shift registers can be used as long as the additional bit of delay is compensated for in some conventional manner such as skewing the counter contents by one count.